coreboot-gerrit June 2020

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Change in coreboot[master]: mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad
by Johnny Li (Code Review) 30 Jun '20

30 Jun '20

Johnny Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42908 ) Change subject: mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad ...................................................................... mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad This change updates scl_lcnt,scl_hcnt,scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:157999726 TEST= Verified that I2C5 frequency is between 389-396kHz. Change-Id: I71d68f288c4e0560895fea144526f9319cefe888 --- M src/mainboard/google/volteer/variants/volteer/overridetree.cb 1 file changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/42908/1 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 203af28..29e14a4 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -88,23 +88,23 @@ end end end # PMC - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| GSPI1 | Fingerprint MCU | - #| I2C0 | Audio | - #| I2C1 | Touchscreen | - #| I2C2 | WLAN, SAR0 | - #| I2C3 | Camera, SAR1 | - #| I2C5 | Trackpad | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[0] = { .speed_mhz = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/42908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71d68f288c4e0560895fea144526f9319cefe888 Gerrit-Change-Number: 42908 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad
by Johnny Li (Code Review) 30 Jun '20

30 Jun '20

Johnny Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42907 ) Change subject: mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad ...................................................................... mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad This change updates scl_lcnt,scl_hcnt,scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:157999726 TEST= Verified that I2C5 frequency is between 389-396kHz. Change-Id: Ifd744f83296542e390263eb3725c8df3cfb7703d --- M src/mainboard/google/volteer/variants/volteer/overridetree.cb 1 file changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/42907/1 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 9e5ef4b..203af28 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -88,5 +88,49 @@ end end end # PMC + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" end end -- To view, visit https://review.coreboot.org/c/coreboot/+/42907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd744f83296542e390263eb3725c8df3cfb7703d Gerrit-Change-Number: 42907 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Jonas Löffelholz (Code Review) 30 Jun '20

30 Jun '20

Jonas Löffelholz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... Patch Set 59: (4 comments) https://review.coreboot.org/c/coreboot/+/37441/51//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37441/51//COMMIT_MSG@23 PS51, Line 23: 84 > decimal Done https://review.coreboot.org/c/coreboot/+/37441/51//COMMIT_MSG@25 PS51, Line 25: Tested with Intel Xeon E-2186G and 64 GB ECC RAM. > ~30sec. Done https://review.coreboot.org/c/coreboot/+/37441/49/Documentation/mainboard/s… File Documentation/mainboard/supermicro/x11-lga1151v2-series/x11-lga1151v2-series.md: https://review.coreboot.org/c/coreboot/+/37441/49/Documentation/mainboard/s… PS49, Line 19: - Intel ME can be cleaned using me_cleaner (~4.5 MB more free space) > Any consequences? Crippling the ME firmware usually breaks things. This statement is actually wrong, therefore i removed it. https://review.coreboot.org/c/coreboot/+/37441/51/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb: https://review.coreboot.org/c/coreboot/+/37441/51/src/mainboard/supermicro/… PS51, Line 38: . > Use_espi=1? this works. login is now possible via serial -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 59 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 30 Jun 2020 11:32:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonas Löffelholz Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Jonas Löffelholz (Code Review) 30 Jun '20

30 Jun '20

Jonas Löffelholz has uploaded a new patch set (#59) to the change originally created by Christian Walter. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F This commit adds initial support for the Supermicro X11SCH-F. What is working: * Aspeed AST2500 graphics output * Serial console * SuperIO devicetree config * Boots into Linux 5.5 * Tested payload EDK II * SATA slots * USB slots * IPMI KCS * LinuxBoot * No ACPI error in Windows/Linux * Windows 10 support * TPM Support (w/ patched IFD) - Patch IFD at 0x235=03 and 0x13E=84 Tested with Intel Xeon E-2186G and 64 GB ECC RAM. Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11-lga1151v2-series.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f_flash.jpg M MAINTAINERS A src/mainboard/supermicro/x11-lga1151v2-series/Kconfig A src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151v2-series/Makefile.inc A src/mainboard/supermicro/x11-lga1151v2-series/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/bootblock.c A src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb A src/mainboard/supermicro/x11-lga1151v2-series/dsdt.asl A src/mainboard/supermicro/x11-lga1151v2-series/memory.c A src/mainboard/supermicro/x11-lga1151v2-series/ramstage.c A src/mainboard/supermicro/x11-lga1151v2-series/romstage.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/Makefile.inc A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/gpio.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/include/variant/variants.h A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb 21 files changed, 1,006 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37441/59 -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 59 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Jonas Löffelholz (Code Review) 30 Jun '20

30 Jun '20

Jonas Löffelholz has uploaded a new patch set (#58) to the change originally created by Christian Walter. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F This commit adds initial support for the Supermicro X11SCH-F. What is working: * Aspeed AST2500 graphics output * Serial console * SuperIO devicetree config * Boots into Linux 5.5 * Tested payload EDK II * SATA slots * USB slots * IPMI KCS * LinuxBoot * No ACPI error in Windows/Linux * Windows 10 support * TPM Support (w/ patched IFD) - Patch IFD at 0x235=03 and 0x13E=84 Tested with Intel Xeon E-2186G and 64 GB ECC RAM. Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11-lga1151v2-series.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f_flash.jpg M MAINTAINERS A src/mainboard/supermicro/x11-lga1151v2-series/Kconfig A src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151v2-series/Makefile.inc A src/mainboard/supermicro/x11-lga1151v2-series/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/bootblock.c A src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb A src/mainboard/supermicro/x11-lga1151v2-series/dsdt.asl A src/mainboard/supermicro/x11-lga1151v2-series/memory.c A src/mainboard/supermicro/x11-lga1151v2-series/ramstage.c A src/mainboard/supermicro/x11-lga1151v2-series/romstage.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/Makefile.inc A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/gpio.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/include/variant/variants.h A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb 21 files changed, 1,007 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37441/58 -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 58 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer: Add support for passive USB-C daughterboard
by Caveh Jalali (Code Review) 30 Jun '20

30 Jun '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42905 ) Change subject: mb/google/volteer: Add support for passive USB-C daughterboard ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/42905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4bd97de8f974531f97469a5e47ecf4d948beca9 Gerrit-Change-Number: 42905 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 30 Jun 2020 11:02:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel: Add include guards on nvs.h
by Kyösti Mälkki (Code Review) 30 Jun '20

30 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42850 ) Change subject: sb/intel: Add include guards on nvs.h ...................................................................... sb/intel: Add include guards on nvs.h Change-Id: I110974f3161f2991536df50acdfe32f68bd2cc60 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/bd82x6x/nvs.h M src/southbridge/intel/i82801dx/nvs.h M src/southbridge/intel/ibexpeak/nvs.h M src/southbridge/intel/lynxpoint/nvs.h 4 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/42850/1 diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index ae3304e..b75e0ab 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef SOUTHBRIDGE_INTEL_BD82X6X_NVS_H +#define SOUTHBRIDGE_INTEL_BD82X6X_NVS_H + #include <commonlib/helpers.h> #include <stdint.h> #include "vendorcode/google/chromeos/gnvs.h" @@ -105,3 +108,5 @@ }; check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); + +#endif /* SOUTHBRIDGE_INTEL_BD82X6X_NVS_H */ diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h index 3cd0afb..1f8f6d1 100644 --- a/src/southbridge/intel/i82801dx/nvs.h +++ b/src/southbridge/intel/i82801dx/nvs.h @@ -1,5 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef SOUTHBRIDGE_INTEL_I82801DX_NVS_H +#define SOUTHBRIDGE_INTEL_I82801DX_NVS_H + +#include <stdint.h> + struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -96,3 +101,5 @@ u8 bten; u8 rsvd13[14]; }; + +#endif /* SOUTHBRIDGE_INTEL_I82801DX_NVS_H */ diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 834b3af..8823d83 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -1,6 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H +#define SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H + #include <commonlib/helpers.h> +#include <stdint.h> #include "vendorcode/google/chromeos/gnvs.h" struct __packed global_nvs { @@ -102,3 +106,5 @@ }; check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); + +#endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */ diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 4abe026..154e285 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H +#define SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H + #include <commonlib/helpers.h> #include <stdint.h> #include "vendorcode/google/chromeos/gnvs.h" @@ -79,3 +82,5 @@ }; check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); + +#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I110974f3161f2991536df50acdfe32f68bd2cc60 Gerrit-Change-Number: 42850 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Doc/mb/google/dragonegg: Drop abandoned project info
by Angel Pons (Code Review) 30 Jun '20

30 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42858 ) Change subject: Doc/mb/google/dragonegg: Drop abandoned project info ...................................................................... Doc/mb/google/dragonegg: Drop abandoned project info Commit 0013623 (mb/google/dragonegg: remove abandoned project) dropped this mainboard because it is no longer in development nor used. However, the associated documentation remained. Rest in pieces, Dragonegg. ;-; Change-Id: Idd2ee716717132ba3fa237ae97f34686007d3685 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- D Documentation/mainboard/google/dragonegg.md M Documentation/mainboard/index.md 2 files changed, 0 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/42858/1 diff --git a/Documentation/mainboard/google/dragonegg.md b/Documentation/mainboard/google/dragonegg.md deleted file mode 100644 index ef7e61b..0000000 --- a/Documentation/mainboard/google/dragonegg.md +++ /dev/null @@ -1,40 +0,0 @@ -# Google Dragonegg (Chromebook) - -This page describes how to run coreboot on the google dragonegg board. - -Dragonegg is based on Intel Ice Lake platform, please refer to below link to get more details -```eval_rst -:doc:`../../soc/intel/icelake/iceLake_coreboot_development` -``` - -## Building coreboot - -* Follow build instructions mentioned in Ice Lake document -```eval_rst -:doc:`../../soc/intel/icelake/iceLake_coreboot_development` -``` - -* The default options for this board should result in a fully working image: -```bash - # echo "CONFIG_VENDOR_GOOGLE=y" > .config - # echo "CONFIG_BOARD_GOOGLE_DRAGONEGG=y" >> .config - # make olddefconfig && make -``` - -## Flashing coreboot - -```eval_rst -+---------------------+------------+ -| Type | Value | -+=====================+============+ -| Socketed flash | no | -+---------------------+------------+ -| Vendor | Winbond | -+---------------------+------------+ -| Size | 32 MiB | -+---------------------+------------+ -| Internal flashing | yes | -+---------------------+------------+ -| External flashing | yes | -+---------------------+------------+ -``` diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index c5503e2..2f03c8f 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -51,10 +51,6 @@ - [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md) -## Google - -- [Dragonegg](google/dragonegg.md) - ## HP - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/42858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd2ee716717132ba3fa237ae97f34686007d3685 Gerrit-Change-Number: 42858 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] ACPI: Promote global_nvs_t related init
by Kyösti Mälkki (Code Review) 30 Jun '20

30 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42489 ) Change subject: [WIP] ACPI: Promote global_nvs_t related init ...................................................................... [WIP] ACPI: Promote global_nvs_t related init Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/include/soc/acpi.h M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/acpi.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/xeon_sp/skx/include/soc/acpi.h M src/southbridge/intel/bd82x6x/nvs.h M src/southbridge/intel/i82801gx/nvs.h M src/southbridge/intel/i82801ix/nvs.h M src/southbridge/intel/i82801jx/nvs.h M src/southbridge/intel/ibexpeak/nvs.h M src/southbridge/intel/lynxpoint/nvs.h 15 files changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/42489/1 diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h index fc8f8ab..98b8283 100644 --- a/src/soc/intel/baytrail/include/soc/acpi.h +++ b/src/soc/intel/baytrail/include/soc/acpi.h @@ -7,6 +7,5 @@ #include <soc/nvs.h> unsigned long acpi_madt_irq_overrides(unsigned long current); -void acpi_init_gnvs(global_nvs_t *gnvs); #endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index cc70f78..d475e63 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -56,7 +56,6 @@ } __packed global_nvs_t; check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -void acpi_create_gnvs(global_nvs_t *gnvs); /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h index 5bff07a..cd54f2c 100644 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -8,7 +8,6 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long acpi_madt_irq_overrides(unsigned long current); -void acpi_init_gnvs(global_nvs_t *gnvs); void southcluster_inject_dsdt(const struct device *device); unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 22ea10f..1dab2c0 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -58,7 +58,6 @@ } __packed global_nvs_t; check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -void acpi_create_gnvs(global_nvs_t *gnvs); /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index 46cc42a..0bf63a4 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -13,7 +13,6 @@ #define PSS_LATENCY_BUSMASTER 10 unsigned long acpi_madt_irq_overrides(unsigned long current); -void acpi_init_gnvs(global_nvs_t *gnvs); unsigned long northbridge_write_acpi_tables(const struct device *dev, unsigned long current, struct acpi_rsdp *rsdp); #endif diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 8772a02..cfbff20 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -48,7 +48,6 @@ } __packed global_nvs_t; check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -void acpi_create_gnvs(global_nvs_t *gnvs); /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 19dd68a..30855c8 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -42,7 +42,6 @@ * Defined as weak in common acpi as gnvs structure definition is * chipset specific. */ -void acpi_create_gnvs(struct global_nvs_t *gnvs); /* * get_cstate_map returns a table of processor specific acpi_cstate_t entries diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 00700a6..9bc5ed0 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -8,7 +8,6 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long acpi_madt_irq_overrides(unsigned long current); -void acpi_init_gnvs(global_nvs_t *gnvs); unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h index c1d61c9..0e00c2b 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h @@ -14,7 +14,6 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long acpi_madt_irq_overrides(unsigned long current); -void acpi_init_gnvs(global_nvs_t *gnvs); unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); void uncore_inject_dsdt(void); diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 075eae0..0d611eb 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -107,4 +107,3 @@ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -void acpi_create_gnvs(global_nvs_t *gnvs); diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index 6b697f2..fd4b053 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -96,4 +96,3 @@ u8 rsvd13[14]; } __packed global_nvs_t; -void acpi_create_gnvs(global_nvs_t *gnvs); diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index 3cd4c58..b97b450 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -98,6 +98,5 @@ u8 rsvd13[14]; } __packed global_nvs_t; -void acpi_create_gnvs(global_nvs_t *gnvs); #endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */ diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index 8dd012f..673c30c 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -96,4 +96,3 @@ u8 rsvd13[14]; } __packed global_nvs_t; -void acpi_create_gnvs(global_nvs_t *gnvs); diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 6b82de3..40b1e57 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -105,4 +105,3 @@ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -void acpi_create_gnvs(global_nvs_t *gnvs); diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index b5b6e9f..34db983 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -82,4 +82,3 @@ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -void acpi_create_gnvs(global_nvs_t * gnvs); -- To view, visit https://review.coreboot.org/c/coreboot/+/42489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Gerrit-Change-Number: 42489 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Add FSP version to coreboot table for cbmem to display
by Johnny Lin (Code Review) 30 Jun '20

30 Jun '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41760 ) Change subject: mb/ocp/deltalake: Add FSP version to coreboot table for cbmem to display ...................................................................... mb/ocp/deltalake: Add FSP version to coreboot table for cbmem to display Overwrite FSP version to coreboot table LB_TAG_EXTRA_VERSION. Tested=On OCP Delta Lake LinuxBoot, u-root shell cbmem can see "LB_TAG_EXTRA_VERSION": "FSPv2.1-0.0.1.120" Change-Id: I579fa87028b9ed0734b2fac206daf43ecae311be Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/41760/1 diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 0acef91..d0baca4 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -1,13 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include <boot/coreboot_tables.h> #include <console/console.h> #include <drivers/ipmi/ipmi_ops.h> #include <drivers/ocp/dmi/ocp_dmi.h> +#include <fsp/util.h> #include <soc/ramstage.h> +#include <string.h> #include "ipmi.h" +#define FSP_VER_LEN 30 + extern struct fru_info_str fru_strings; static void dl_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) @@ -67,6 +72,41 @@ printk(BIOS_ERR, "ipmi_set_ppin failed\n"); } +static void get_fsp_version(char *buf) +{ + /* FSP header has been read and validated at this stage */ + struct fsp_header *hdr = &fsps_hdr; + union { + uint32_t val; + struct { + uint8_t bld_num; + uint8_t revision; + uint8_t minor; + uint8_t major; + } rev; + } revision; + + revision.val = hdr->fsp_revision; + snprintf(buf, FSP_VER_LEN, "FSPv%u.%u-%u.%u.%u.%u", (hdr->spec_version >> 4), + hdr->spec_version & 0xf, revision.rev.major, + revision.rev.minor, revision.rev.revision, revision.rev.bld_num); +} + +/* Overwrite FSP version to coreboot table LB_TAG_EXTRA_VERSION */ +void lb_board(struct lb_header *header) +{ + struct lb_string *rec; + size_t len; + char fsp_version[FSP_VER_LEN] = {0}; + + get_fsp_version(fsp_version); + rec = (struct lb_string *)lb_new_record(header); + rec->tag = LB_TAG_EXTRA_VERSION; + len = strlen(fsp_version); + rec->size = ALIGN_UP(sizeof(*rec) + len + 1, 8); + memcpy(rec->string, fsp_version, len+1); +} + struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, .final = mainboard_final, -- To view, visit https://review.coreboot.org/c/coreboot/+/41760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I579fa87028b9ed0734b2fac206daf43ecae311be Gerrit-Change-Number: 41760 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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