coreboot-gerrit June 2020

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Change in coreboot[master]: Revert "amd/pi/hudson: Add GPIO get function"
by Kyösti Mälkki (Code Review) 30 Jun '20

30 Jun '20

Hello Marc Jones, build bot (Jenkins), Martin Roth, Marshall Dawson, Paul Menzel, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42743 to review the following change. Change subject: Revert "amd/pi/hudson: Add GPIO get function" ...................................................................... Revert "amd/pi/hudson: Add GPIO get function" This reverts commit dae95f0dfe9ad94922c940d3c0522d53284b4deb. Reason for revert: Filename conflict on with top-level <gpio.h> and incompatibility with it. Let's see if this code has any users. Change-Id: I120b0bfda1501e9941c71315852d87d251f76a5b --- M src/southbridge/amd/pi/hudson/Makefile.inc D src/southbridge/amd/pi/hudson/gpio.c D src/southbridge/amd/pi/hudson/gpio.h 3 files changed, 0 insertions(+), 162 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/42743/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index f6d7305..5f5b1c8 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -39,7 +39,6 @@ ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += sd.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += gpio.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c diff --git a/src/southbridge/amd/pi/hudson/gpio.c b/src/southbridge/amd/pi/hudson/gpio.c deleted file mode 100644 index 5b2eb4c..0000000 --- a/src/southbridge/amd/pi/hudson/gpio.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include "gpio.h" - -int gpio_get(gpio_t gpio_num) -{ - uint32_t reg; - - reg = read32((void*)(uintptr_t)gpio_num); - - return !!(reg & GPIO_PIN_STS); -} diff --git a/src/southbridge/amd/pi/hudson/gpio.h b/src/southbridge/amd/pi/hudson/gpio.h deleted file mode 100644 index 3863ed2..0000000 --- a/src/southbridge/amd/pi/hudson/gpio.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _HUDSON_GPIO_H_ -#define _HUDSON_GPIO_H_ - -#include <southbridge/amd/common/amd_defs.h> -#include <types.h> - -#define CROS_GPIO_DEVICE_NAME "AmdKern" - -#define GPIO_PIN_STS (1 << 16) -#define GPIO_OUTPUT_VALUE (1 << 22) -#define GPIO_OUTPUT_ENABLE (1 << 23) - -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) -/* GPIO_0 - GPIO_62 */ -#define GPIO_BANK0_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1500) -#define GPIO_0 (GPIO_BANK0_CONTROL + 0x00) -#define GPIO_1 (GPIO_BANK0_CONTROL + 0x04) -#define GPIO_2 (GPIO_BANK0_CONTROL + 0x08) -#define GPIO_3 (GPIO_BANK0_CONTROL + 0x0C) -#define GPIO_4 (GPIO_BANK0_CONTROL + 0x10) -#define GPIO_5 (GPIO_BANK0_CONTROL + 0x14) -#define GPIO_6 (GPIO_BANK0_CONTROL + 0x18) -#define GPIO_7 (GPIO_BANK0_CONTROL + 0x1C) -#define GPIO_8 (GPIO_BANK0_CONTROL + 0x20) -#define GPIO_9 (GPIO_BANK0_CONTROL + 0x24) -#define GPIO_10 (GPIO_BANK0_CONTROL + 0x28) -#define GPIO_11 (GPIO_BANK0_CONTROL + 0x2C) -#define GPIO_12 (GPIO_BANK0_CONTROL + 0x30) -#define GPIO_13 (GPIO_BANK0_CONTROL + 0x34) -#define GPIO_14 (GPIO_BANK0_CONTROL + 0x38) -#define GPIO_15 (GPIO_BANK0_CONTROL + 0x3C) -#define GPIO_16 (GPIO_BANK0_CONTROL + 0x40) -#define GPIO_17 (GPIO_BANK0_CONTROL + 0x44) -#define GPIO_18 (GPIO_BANK0_CONTROL + 0x48) -#define GPIO_19 (GPIO_BANK0_CONTROL + 0x4C) -#define GPIO_20 (GPIO_BANK0_CONTROL + 0x50) -#define GPIO_21 (GPIO_BANK0_CONTROL + 0x54) -#define GPIO_22 (GPIO_BANK0_CONTROL + 0x58) -#define GPIO_23 (GPIO_BANK0_CONTROL + 0x5C) -#define GPIO_24 (GPIO_BANK0_CONTROL + 0x60) -#define GPIO_25 (GPIO_BANK0_CONTROL + 0x64) -#define GPIO_26 (GPIO_BANK0_CONTROL + 0x68) -#define GPIO_39 (GPIO_BANK0_CONTROL + 0x9C) -#define GPIO_42 (GPIO_BANK0_CONTROL + 0xA8) - -/* GPIO_64 - GPIO_127 */ -#define GPIO_BANK1 (CONTROL AMD_SB_ACPI_MMIO_ADDR + 0x1600) -#define GPIO_64 (GPIO_BANK1_CONTROL + 0x00) -#define GPIO_65 (GPIO_BANK1_CONTROL + 0x04) -#define GPIO_66 (GPIO_BANK1_CONTROL + 0x08) -#define GPIO_67 (GPIO_BANK1_CONTROL + 0x0C) -#define GPIO_68 (GPIO_BANK1_CONTROL + 0x10) -#define GPIO_69 (GPIO_BANK1_CONTROL + 0x14) -#define GPIO_70 (GPIO_BANK1_CONTROL + 0x18) -#define GPIO_71 (GPIO_BANK1_CONTROL + 0x1C) -#define GPIO_72 (GPIO_BANK1_CONTROL + 0x20) -#define GPIO_74 (GPIO_BANK1_CONTROL + 0x28) -#define GPIO_75 (GPIO_BANK1_CONTROL + 0x2C) -#define GPIO_76 (GPIO_BANK1_CONTROL + 0x30) -#define GPIO_84 (GPIO_BANK1_CONTROL + 0x50) -#define GPIO_85 (GPIO_BANK1_CONTROL + 0x54) -#define GPIO_86 (GPIO_BANK1_CONTROL + 0x58) -#define GPIO_87 (GPIO_BANK1_CONTROL + 0x5C) -#define GPIO_88 (GPIO_BANK1_CONTROL + 0x60) -#define GPIO_89 (GPIO_BANK1_CONTROL + 0x64) -#define GPIO_90 (GPIO_BANK1_CONTROL + 0x68) -#define GPIO_91 (GPIO_BANK1_CONTROL + 0x6C) -#define GPIO_92 (GPIO_BANK1_CONTROL + 0x70) -#define GPIO_93 (GPIO_BANK1_CONTROL + 0x74) -#define GPIO_95 (GPIO_BANK1_CONTROL + 0x7C) -#define GPIO_96 (GPIO_BANK1_CONTROL + 0x80) -#define GPIO_97 (GPIO_BANK1_CONTROL + 0x84) -#define GPIO_98 (GPIO_BANK1_CONTROL + 0x88) -#define GPIO_99 (GPIO_BANK1_CONTROL + 0x8C) -#define GPIO_100 (GPIO_BANK1_CONTROL + 0x90) -#define GPIO_101 (GPIO_BANK1_CONTROL + 0x94) -#define GPIO_102 (GPIO_BANK1_CONTROL + 0x98) -#define GPIO_113 (GPIO_BANK1_CONTROL + 0xC4) -#define GPIO_114 (GPIO_BANK1_CONTROL + 0xC8) -#define GPIO_115 (GPIO_BANK1_CONTROL + 0xCC) -#define GPIO_116 (GPIO_BANK1_CONTROL + 0xD0) -#define GPIO_117 (GPIO_BANK1_CONTROL + 0xD4) -#define GPIO_118 (GPIO_BANK1_CONTROL + 0xD8) -#define GPIO_119 (GPIO_BANK1_CONTROL + 0xDC) -#define GPIO_120 (GPIO_BANK1_CONTROL + 0xE0) -#define GPIO_121 (GPIO_BANK1_CONTROL + 0xE4) -#define GPIO_122 (GPIO_BANK1_CONTROL + 0xE8) -#define GPIO_126 (GPIO_BANK1_CONTROL + 0xF8) - -/* GPIO_128 - GPIO_183 */ -#define GPIO_BANK2_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1700) -#define GPIO_129 (GPIO_BANK2_CONTROL + 0x04) -#define GPIO_130 (GPIO_BANK2_CONTROL + 0x08) -#define GPIO_131 (GPIO_BANK2_CONTROL + 0x0C) -#define GPIO_132 (GPIO_BANK2_CONTROL + 0x10) -#define GPIO_133 (GPIO_BANK2_CONTROL + 0x14) -#define GPIO_134 (GPIO_BANK2_CONTROL + 0x18) -#define GPIO_135 (GPIO_BANK2_CONTROL + 0x1C) -#define GPIO_136 (GPIO_BANK2_CONTROL + 0x20) -#define GPIO_137 (GPIO_BANK2_CONTROL + 0x24) -#define GPIO_138 (GPIO_BANK2_CONTROL + 0x28) -#define GPIO_139 (GPIO_BANK2_CONTROL + 0x2C) -#define GPIO_140 (GPIO_BANK2_CONTROL + 0x30) -#define GPIO_141 (GPIO_BANK2_CONTROL + 0x34) -#define GPIO_142 (GPIO_BANK2_CONTROL + 0x38) -#define GPIO_143 (GPIO_BANK2_CONTROL + 0x3C) -#define GPIO_144 (GPIO_BANK2_CONTROL + 0x40) -#define GPIO_145 (GPIO_BANK2_CONTROL + 0x44) -#define GPIO_146 (GPIO_BANK2_CONTROL + 0x48) -#define GPIO_147 (GPIO_BANK2_CONTROL + 0x4C) -#define GPIO_148 (GPIO_BANK2_CONTROL + 0x50) -#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) */ - -typedef uint32_t gpio_t; - -int gpio_get(gpio_t gpio_num); - -#endif /* _HUDSON_GPIO_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I120b0bfda1501e9941c71315852d87d251f76a5b Gerrit-Change-Number: 42743 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tgl: Add SkipCpuReplacementCheck to chip options
by Jamie Ryu (Code Review) 30 Jun '20

30 Jun '20

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42788 ) Change subject: soc/intel/tgl: Add SkipCpuReplacementCheck to chip options ...................................................................... soc/intel/tgl: Add SkipCpuReplacementCheck to chip options Add SkipCpuReplacementCheck to chip options to control UPD FSPM SkipCpuReplacementCheck from device tree. This UPD allows to skip CPU replacement check to avoid forced MRC traning with platforms with soldered down SoC. TEST=boot and verified with volteer Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/42788/1 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index c72698f..432f857 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -365,6 +365,12 @@ /* External Vnn Voltage in mV */ int vnn_sx_voltage_mv; } ext_fivr_settings; + + /* + * Enable(0)/Disable(1) CPU Replacement check. + * Default 0. Setting this to 1 skips checking CPU replacement. + */ + uint8_t SkipCpuReplacementCheck; }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 1a46b7a..3eba69a 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -199,6 +199,9 @@ /* Command Pins Mirrored */ m_cfg->CmdMirror[0] = config->CmdMirror; + + /* Skip CPU replacement check */ + m_cfg->SkipCpuReplacementCheck = config->SkipCpuReplacementCheck; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/42788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d Gerrit-Change-Number: 42788 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Avoid NULL pointer dereference
by John Zhao (Code Review) 30 Jun '20

30 Jun '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42836 ) Change subject: soc/intel/tigerlake: Avoid NULL pointer dereference ...................................................................... soc/intel/tigerlake: Avoid NULL pointer dereference Coverity detects dereferencing pointers that might be "NULL" when calling acpigen_write_scope and acpigen_write_device. Add sanity check for both of scope and name to prevent NULL pointer dereference. BUG=CID 1429981 TEST=Built and boot up to kernel. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Iea3801585e8c294fb889a8137b534bb932696025 --- M src/soc/intel/tigerlake/pmc.c 1 file changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/42836/1 diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 4d89870..561447d 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -101,8 +101,13 @@ static void soc_pmc_fill_ssdt(const struct device *dev) { - acpigen_write_scope(acpi_device_scope(dev)); - acpigen_write_device(acpi_device_name(dev)); + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + if (!scope || !name) + return; + + acpigen_write_scope(scope); + acpigen_write_device(name); acpigen_write_name_string("_HID", PMC_HID); acpigen_write_name_string("_DDN", "Intel(R) Tiger Lake IPC Controller"); -- To view, visit https://review.coreboot.org/c/coreboot/+/42836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea3801585e8c294fb889a8137b534bb932696025 Gerrit-Change-Number: 42836 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/drivers/intel: Avoid NULL pointer dereference
by John Zhao (Code Review) 30 Jun '20

30 Jun '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42835 ) Change subject: src/drivers/intel: Avoid NULL pointer dereference ...................................................................... src/drivers/intel: Avoid NULL pointer dereference Coverity detects dereferencing pointers that might be "NULL" when calling acpigen_write_scope and acpigen_write_device. Add sanity check for both of scope and name to prevent NULL pointer dereference. BUG=CID 1429979, 1429982 TEST=Built and boot up to kernel. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: If17d12861f562dc0d6c98a5c91a9d3c0360ca2c9 --- M src/drivers/intel/pmc_mux/con/con.c M src/drivers/intel/pmc_mux/mux.c 2 files changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/42835/1 diff --git a/src/drivers/intel/pmc_mux/con/con.c b/src/drivers/intel/pmc_mux/con/con.c index 08c38e8..ad95905 100644 --- a/src/drivers/intel/pmc_mux/con/con.c +++ b/src/drivers/intel/pmc_mux/con/con.c @@ -29,13 +29,20 @@ { struct drivers_intel_pmc_mux_con_config *config = dev->chip_info; struct acpi_dp *dsd; + const char *scope; + const char *name; if (!dev->enabled) return; /* Reference the existing scope and write CONx device */ - acpigen_write_scope(acpi_device_scope(dev)); - acpigen_write_device(acpi_device_name(dev)); + scope = acpi_device_scope(dev); + name = acpi_device_name(dev); + if (!scope || !name) + return; + + acpigen_write_scope(scope); + acpigen_write_device(name); acpigen_write_name_integer("_ADR", dev->path.generic.id); diff --git a/src/drivers/intel/pmc_mux/mux.c b/src/drivers/intel/pmc_mux/mux.c index 29ed1a9..e209915 100644 --- a/src/drivers/intel/pmc_mux/mux.c +++ b/src/drivers/intel/pmc_mux/mux.c @@ -13,8 +13,14 @@ static void mux_fill_ssdt(const struct device *dev) { - acpigen_write_scope(acpi_device_scope(dev)); - acpigen_write_device(acpi_device_name(dev)); + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + + if (!scope || !name) + return; + + acpigen_write_scope(scope); + acpigen_write_device(name); acpigen_write_name_string("_HID", TGL_PMC_MUX_HID); acpigen_write_name_string("_DDN", dev->chip_ops->name); -- To view, visit https://review.coreboot.org/c/coreboot/+/42835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If17d12861f562dc0d6c98a5c91a9d3c0360ca2c9 Gerrit-Change-Number: 42835 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Remove uneeded white spaces
by HAOUAS Elyes (Code Review) 30 Jun '20

30 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42795 ) Change subject: src: Remove uneeded white spaces ...................................................................... src: Remove uneeded white spaces Remove white spaces before tabs. Change-Id: I73695152ec8d8ab2dabf8421ef2405f70de0f4ba Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb M src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex M src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex M src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex M src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex M src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex M src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/common/acpi/lpit.asl M src/soc/intel/tigerlake/acpi/tcss.asl M src/soc/intel/tigerlake/acpi/tcss_dma.asl M src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl 17 files changed, 24 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/42795/1 diff --git a/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb index 541db02..77d3bb0 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb @@ -3,8 +3,8 @@ chip southbridge/intel/i82371eb # Southbridge register "gpo" = "0x7fbfb9ff" register "gpo22_enable" = "1" # GPO22 controls LVD port termination (0=enabled) - # GPO23 controls SCSI-50 port termination (1=enabled) - # SCSI-68 port is always terminated + # GPO23 controls SCSI-50 port termination (1=enabled) + # SCSI-68 port is always terminated device pci 4.0 on # ISA bridge chip superio/winbond/w83977tf # Super I/O device pnp 3f0.a off # ACPI diff --git a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex index bce16cc..c51a5b901 100644 --- a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -170,7 +170,7 @@ 00 # 33 SDRAM device type -# byte [1:0] : 00b = Signal Loading not specified +# byte [1:0] : 00b = Signal Loading not specified # byte [6:4] : 000b = Die count not specified # byte [7] : 0 = Standard Monolithic DRAM Device 00 diff --git a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex index fa55389..5007a26 100644 --- a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -170,7 +170,7 @@ 00 # 33 SDRAM device type -# byte [1:0] : 00b = Signal Loading not specified +# byte [1:0] : 00b = Signal Loading not specified # byte [6:4] : 000b = Die count not specified # byte [7] : 1 = Non-Standard Device 80 diff --git a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex index 11ec821..c3b71d6 100644 --- a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -168,7 +168,7 @@ # 33 SDRAM device type # byte [1:0] : 01b = multi load stack -# byte [6:4] : 100b = 8 die +# byte [6:4] : 100b = 8 die # byte [7] : 0 = Standard Device 41 diff --git a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex index bce16cc..c51a5b901 100644 --- a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex +++ b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -170,7 +170,7 @@ 00 # 33 SDRAM device type -# byte [1:0] : 00b = Signal Loading not specified +# byte [1:0] : 00b = Signal Loading not specified # byte [6:4] : 000b = Die count not specified # byte [7] : 0 = Standard Monolithic DRAM Device 00 diff --git a/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex index fa55389..5007a26 100644 --- a/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex +++ b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -170,7 +170,7 @@ 00 # 33 SDRAM device type -# byte [1:0] : 00b = Signal Loading not specified +# byte [1:0] : 00b = Signal Loading not specified # byte [6:4] : 000b = Die count not specified # byte [7] : 1 = Non-Standard Device 80 diff --git a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex index 11ec821..c3b71d6 100644 --- a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex +++ b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -168,7 +168,7 @@ # 33 SDRAM device type # byte [1:0] : 01b = multi load stack -# byte [6:4] : 100b = 8 die +# byte [6:4] : 100b = 8 die # byte [7] : 0 = Standard Device 41 diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index c55ac92..532254b 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -34,7 +34,7 @@ device pci 00.0 on end # Aspeed 2500 VGA end end # PCIe - device pci 1f.0 on # LPC Interface + device pci 1f.0 on # LPC Interface chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 3388239..0de19ef 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -25,7 +25,7 @@ # Enumeration starts at 0 for PCIE1 # Ports are not hotplugable register "PcieRpEnable[0]" = "1" # Slot3 x4 - # Set MaxPayload to 256 bytes + # Set MaxPayload to 256 bytes register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" # Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 4074bae..be50408 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -93,7 +93,7 @@ device pci 1c.0 on end # - eMMC device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO - device pci 1f.0 on # - LPC + device pci 1f.0 on # - LPC chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 723ecb3..33664fe 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -108,7 +108,7 @@ device pci 1c.0 on end # - eMMC device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO - device pci 1f.0 on # - LPC + device pci 1f.0 on # - LPC chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index 3b52f65..a865f9f 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -72,7 +72,7 @@ device pci 1c.0 off end # - eMMC device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO - device pci 1f.0 on # - LPC + device pci 1f.0 on # - LPC chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index ae0afc8..8e1de1e 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -82,7 +82,7 @@ * containing one bit for each function index, starting * with zero. * Bit 0 - Indicates whether there is support for any - * functions other than function 0 + * functions other than function 0 * Bit 1 - Indicates support to clear power control * register * Bit 2 - Indicates support to set power control diff --git a/src/soc/intel/common/acpi/lpit.asl b/src/soc/intel/common/acpi/lpit.asl index b81275e..348ae56 100644 --- a/src/soc/intel/common/acpi/lpit.asl +++ b/src/soc/intel/common/acpi/lpit.asl @@ -69,7 +69,7 @@ /* * Save the current PM bits then * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG - */ + */ If (CondRefOf (\_SB.PCI0.EGPM)) { \_SB.PCI0.EGPM () diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 3f51ecc..c635bb1 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -356,7 +356,7 @@ * Poll pCode MailBox Ready * * Return 0xFF - Timeout - * 0x00 - Ready + * 0x00 - Ready */ Method (PMBY, 0) { @@ -382,13 +382,13 @@ * DATA[1:1] TCSS_DEVEN_REQUEST_STATUS: * 0 - IDLE. TCSS DEVEN has reached its final requested state. * 1 - In Progress. TCSS DEVEN is currently in progress of switching state - * according to given request (bit 0 reflects source state). + * according to given request (bit 0 reflects source state). * * Return 0x00 - TCSS Deven in normal state - * 0x01 - TCSS Deven is cleared by BIOS Mailbox request - * 0x1x - TCSS Deven is in progress of switching state according to given request - * 0xFE - Command timeout - * 0xFF - Command corrupt + * 0x01 - TCSS Deven is cleared by BIOS Mailbox request + * 0x1x - TCSS Deven is in progress of switching state according to given request + * 0xFE - Command timeout + * 0xFF - Command corrupt */ Method (DSGS, 0) { diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index 8eab92f..3d44d92 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -56,7 +56,7 @@ */ Method (D3CX, 0, Serialized) { - DD3E = 0 /* Disable DMA RTD3 */ + DD3E = 0 /* Disable DMA RTD3 */ STAT = 0x1 } @@ -65,7 +65,7 @@ */ Method (D3CE, 0, Serialized) { - DD3E = 1 /* Enable DMA RTD3 */ + DD3E = 1 /* Enable DMA RTD3 */ STAT = 0 } diff --git a/src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl index d83bf26..0505152 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl +++ b/src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl @@ -6,7 +6,7 @@ * The mapping fields ae Address, Pin, Source, Source Index. */ -#define GEN_PCIE_LEGACY_IRQ() \ +#define GEN_PCIE_LEGACY_IRQ() \ Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ Package () { 0x0001FFFF, 0x01, LNKB, 0x00 }, \ Package () { 0x0002FFFF, 0x02, LNKC, 0x00 }, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/42795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73695152ec8d8ab2dabf8421ef2405f70de0f4ba Gerrit-Change-Number: 42795 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

7 19

Change in coreboot[master]: src/mb: Use macro for access_size
by HAOUAS Elyes (Code Review) 30 Jun '20

30 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42728 ) Change subject: src/mb: Use macro for access_size ...................................................................... src/mb: Use macro for access_size Change-Id: I275c86ef5833d87378cff1e1bd228776e007dad3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/mainboard.c M src/mainboard/lenovo/x60/mainboard.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/42728/1 diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 509784f..447837b 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -17,7 +17,7 @@ .space_id = ACPI_ADDRESS_SPACE_FIXED, .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = 0, + .access_size = ACPI_ACCESS_SIZE_UNDEFINED, .addrl = 0, .addrh = 0, } @@ -30,7 +30,7 @@ .space_id = ACPI_ADDRESS_SPACE_FIXED, .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = 0, + .access_size = ACPI_ACCESS_SIZE_UNDEFINED, .addrl = 0x10, .addrh = 0, } diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index f88ff00..1623ddc 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -20,7 +20,7 @@ .space_id = ACPI_ADDRESS_SPACE_FIXED, \ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ - .access_size = 0, \ + .access_size = ACPI_ACCESS_SIZE_UNDEFINED, \ .addrl = (((state) << 4) | (sub_state)), \ .addrh = 0, \ } -- To view, visit https://review.coreboot.org/c/coreboot/+/42728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I275c86ef5833d87378cff1e1bd228776e007dad3 Gerrit-Change-Number: 42728 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: mb/lenovo/x60: Use tabs for aligning the "\"
by HAOUAS Elyes (Code Review) 30 Jun '20

30 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42854 ) Change subject: mb/lenovo/x60: Use tabs for aligning the "\" ...................................................................... mb/lenovo/x60: Use tabs for aligning the "\" Change-Id: Id4ada670d35208c40f2eb07308e6732c2a85dbe1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/x60/mainboard.c 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/42854/1 diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index f88ff00..5210040 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -15,15 +15,15 @@ #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT -#define MWAIT_RES(state, sub_state) \ - { \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ - .access_size = 0, \ - .addrl = (((state) << 4) | (sub_state)), \ - .addrh = 0, \ - } +#define MWAIT_RES(state, sub_state) \ + { \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = 0, \ + .addrl = (((state) << 4) | (sub_state)), \ + .addrh = 0, \ + } static acpi_cstate_t cst_entries[] = { { -- To view, visit https://review.coreboot.org/c/coreboot/+/42854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4ada670d35208c40f2eb07308e6732c2a85dbe1 Gerrit-Change-Number: 42854 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI F...
by Johnny Lin (Code Review) 30 Jun '20

30 Jun '20

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40308 ) Change subject: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data ...................................................................... Patch Set 48: (1 comment) https://review.coreboot.org/c/coreboot/+/40308/44/src/drivers/ocp/dmi/ocp_d… File src/drivers/ocp/dmi/ocp_dmi.h: https://review.coreboot.org/c/coreboot/+/40308/44/src/drivers/ocp/dmi/ocp_d… PS44, Line 15: extern msr_t xeon_sp_ppin[]; > Yes, it makes sense to move the PPIN read functions to xeon_sp directory. Split read PPIN function to CB:42901 -- To view, visit https://review.coreboot.org/c/coreboot/+/40308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c958dfad83216cd12545760a19d205efc2515b Gerrit-Change-Number: 40308 Gerrit-PatchSet: 48 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 30 Jun 2020 05:52:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI F...
by Johnny Lin (Code Review) 30 Jun '20

30 Jun '20

Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Patrick Rudolph, Jonathan Zhang, Maxim Polyakov, David Hendricks, Jingle Hsu, Morgan Jang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40308 to look at the new patch set (#48). Change subject: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data ...................................................................... drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data It implements the SMBIOS IPMI FRU mapping table defined in https://www.opencompute.org/documents/facebook-xeon-motherboard-v31 22.3 SMBIOS FRU mapping table. Mainboard needs to configure the correct values for FRU_DEVICE_ID and BMC_KCS_BASE. For type 11 string 1 to 6 are common and implemented in this driver, the rest are project dependent and can be added in the mainboard code. Tested on OCP Tioga Pass. Change-Id: I08c958dfad83216cd12545760a19d205efc2515b Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- A src/drivers/ocp/dmi/Kconfig A src/drivers/ocp/dmi/Makefile.inc A src/drivers/ocp/dmi/ocp_dmi.h A src/drivers/ocp/dmi/smbios.c 4 files changed, 293 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/40308/48 -- To view, visit https://review.coreboot.org/c/coreboot/+/40308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c958dfad83216cd12545760a19d205efc2515b Gerrit-Change-Number: 40308 Gerrit-PatchSet: 48 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google: Drop aliases for APM_CNT_ACPI_xx
by Kyösti Mälkki (Code Review) 30 Jun '20

30 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42848 ) Change subject: mb/google: Drop aliases for APM_CNT_ACPI_xx ...................................................................... mb/google: Drop aliases for APM_CNT_ACPI_xx Use defines found in <cpu/x86/smm.h>. Change-Id: Ib75df13021120fb2c056782c252e97d6b036c7da Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/butterfly/mainboard_smi.c M src/mainboard/google/link/mainboard_smi.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/stout/mainboard_smi.c 4 files changed, 8 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/42848/1 diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/mainboard_smi.c index ab0c5b27..d4f2b99 100644 --- a/src/mainboard/google/butterfly/mainboard_smi.c +++ b/src/mainboard/google/butterfly/mainboard_smi.c @@ -33,20 +33,17 @@ } } -#define APMC_ACPI_EN 0xe1 -#define APMC_ACPI_DIS 0x1e - int mainboard_smi_apmc(u8 apmc) { printk(BIOS_DEBUG, "mainboard_smi_apmc: %x\n", apmc); switch (apmc) { - case APMC_ACPI_EN: + case APM_CNT_ACPI_ENABLE: printk(BIOS_DEBUG, "APMC: ACPI_EN\n"); /* Clear all pending events and enable SCI */ ec_write_cmd(EC_CMD_ENABLE_ACPI_MODE); break; - case APMC_ACPI_DIS: + case APM_CNT_ACPI_DISABLE: printk(BIOS_DEBUG, "APMC: ACPI_DIS\n"); /* Clear all pending events and tell the EC that ACPI is disabled */ ec_write_cmd(EC_CMD_DISABLE_ACPI_MODE); diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index 8899271..e7ec332 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -76,19 +76,16 @@ google_chromeec_set_wake_mask(LINK_EC_S3_WAKE_EVENTS); } -#define APMC_ACPI_EN 0xe1 -#define APMC_ACPI_DIS 0x1e - int mainboard_smi_apmc(u8 apmc) { switch (apmc) { - case APMC_ACPI_EN: + case APM_CNT_ACPI_ENABLE: google_chromeec_set_smi_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); google_chromeec_set_sci_mask(LINK_EC_SCI_EVENTS); break; - case APMC_ACPI_DIS: + case APM_CNT_ACPI_DISABLE: google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index a71b2a3..abfe3a3 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -68,14 +68,11 @@ } } -#define APMC_ACPI_EN 0xe1 -#define APMC_ACPI_DIS 0x1e - int mainboard_smi_apmc(u8 apmc) { printk(BIOS_DEBUG, "mainboard_smi_apmc: %x\n", apmc); switch (apmc) { - case APMC_ACPI_EN: + case APM_CNT_ACPI_ENABLE: printk(BIOS_DEBUG, "APMC: ACPI_EN\n"); /* Clear all pending events */ /* EC cmd:59 data:E8 */ @@ -85,7 +82,7 @@ /* Set LID GPI to generate SCIs */ gpi_route_interrupt(EC_LID_GPI, GPI_IS_SCI); break; - case APMC_ACPI_DIS: + case APM_CNT_ACPI_DISABLE: printk(BIOS_DEBUG, "APMC: ACPI_DIS\n"); /* Clear all pending events */ /* EC cmd:59 data:e9 */ diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 9c2aff8..cf7fcae 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -70,22 +70,19 @@ ec_it8518_enable_wake_events(); } -#define APMC_ACPI_EN 0xe1 -#define APMC_ACPI_DIS 0x1e - int mainboard_smi_apmc(u8 apmc) { switch (apmc) { case APM_CNT_FINALIZE: stout_ec_finalize_smm(); break; - case APMC_ACPI_EN: + case APM_CNT_ACPI_ENABLE: /* * TODO(kimarie) Clear all pending events and enable SCI. */ ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER); break; - case APMC_ACPI_DIS: + case APM_CNT_ACPI_DISABLE: /* * TODO(kimarie) Clear all pending events and enable SMI. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib75df13021120fb2c056782c252e97d6b036c7da Gerrit-Change-Number: 42848 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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