coreboot-gerrit June 2020

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Change in coreboot[master]: mainboard/lenovo/x230: remove unnecessary code and comments for x230s
by Bill XIE (Code Review) 29 Jun '20

29 Jun '20

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41390 ) Change subject: mainboard/lenovo/x230: remove unnecessary code and comments for x230s ...................................................................... mainboard/lenovo/x230: remove unnecessary code and comments for x230s There are some unnecessary code and comments remaining before x230s support ( https://review.coreboot.org/c/coreboot/+/41168 ) gets accepted. This commit will remove them. Change-Id: Id59cdc5479aaf70809dd1ca613056263661455eb Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/mainboard/lenovo/x230/variants/x230s/early_init.c M src/mainboard/lenovo/x230/variants/x230s/gma-mainboard.ads 2 files changed, 1 insertion(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/41390/1 diff --git a/src/mainboard/lenovo/x230/variants/x230s/early_init.c b/src/mainboard/lenovo/x230/variants/x230s/early_init.c index 0b4c084..17810fc 100644 --- a/src/mainboard/lenovo/x230/variants/x230s/early_init.c +++ b/src/mainboard/lenovo/x230/variants/x230s/early_init.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* FIXME: Check if all includes are needed. */ - #include <stdint.h> #include <string.h> #include <timestamp.h> @@ -33,17 +31,7 @@ { 1, 1, -1 }, }; -void bootblock_mainboard_early_init(void) -{ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); -} - -/* FIXME: Put proper SPD map here. */ void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x52, id_only); - read_spd(&spd[2], 0x51, id_only); - read_spd(&spd[3], 0x53, id_only); } diff --git a/src/mainboard/lenovo/x230/variants/x230s/gma-mainboard.ads b/src/mainboard/lenovo/x230/variants/x230s/gma-mainboard.ads index fb75293..fd2a5d5 100644 --- a/src/mainboard/lenovo/x230/variants/x230s/gma-mainboard.ads +++ b/src/mainboard/lenovo/x230/variants/x230s/gma-mainboard.ads @@ -16,7 +16,7 @@ HDMI2, HDMI3, Analog, - EDP, + eDP, others => Disabled); end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/41390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id59cdc5479aaf70809dd1ca613056263661455eb Gerrit-Change-Number: 41390 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: Refactor GPIO SCI/SMI interrupts
by Patrick Georgi (Code Review) 29 Jun '20

29 Jun '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42687 ) Change subject: soc/amd/common: Refactor GPIO SCI/SMI interrupts ...................................................................... soc/amd/common: Refactor GPIO SCI/SMI interrupts Change-Id: Ib2c7cd70ab38d0d8e745b0a611b780d2b0b8dc5b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42687 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/gpio_banks/gpio.c M src/soc/amd/common/block/include/amdblocks/gpio_banks.h 2 files changed, 59 insertions(+), 51 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index c5f8e98..4d6d164 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -32,11 +32,8 @@ write32(address, reg32); } -static void program_smi(uint32_t flag, int gevent_num) +static void program_smi(uint32_t trigger, int gevent_num) { - uint32_t trigger; - - trigger = flag & FLAGS_TRIGGER_MASK; /* * Only level trigger is allowed for SMI. Trigger values are 0 * through 3, with 0-1 being level trigger and 2-3 being edge @@ -46,38 +43,58 @@ assert(trigger < GPIO_TRIGGER_EDGE_LOW); if (trigger == GPIO_TRIGGER_LEVEL_HIGH) - configure_gevent_smi(gevent_num, SMI_MODE_SMI, - SMI_SCI_LVL_HIGH); + configure_gevent_smi(gevent_num, SMI_MODE_SMI, SMI_SCI_LVL_HIGH); + if (trigger == GPIO_TRIGGER_LEVEL_LOW) - configure_gevent_smi(gevent_num, SMI_MODE_SMI, - SMI_SCI_LVL_LOW); + configure_gevent_smi(gevent_num, SMI_MODE_SMI, SMI_SCI_LVL_LOW); } -static void get_sci_config_bits(uint32_t flag, uint32_t *edge, uint32_t *level) -{ - uint32_t trigger; +struct sci_trigger_regs { + uint32_t mask; + uint32_t polarity; + uint32_t level; +}; - trigger = flag & FLAGS_TRIGGER_MASK; - switch (trigger) { - case GPIO_TRIGGER_LEVEL_LOW: - *edge = SCI_TRIGGER_LEVEL; - *level = 0; - break; - case GPIO_TRIGGER_LEVEL_HIGH: - *edge = SCI_TRIGGER_LEVEL; - *level = 1; - break; - case GPIO_TRIGGER_EDGE_LOW: - *edge = SCI_TRIGGER_EDGE; - *level = 0; - break; - case GPIO_TRIGGER_EDGE_HIGH: - *edge = SCI_TRIGGER_EDGE; - *level = 1; - break; - default: - break; - } +/* + * For each general purpose event, GPE, the choice of edge/level triggered + * event is represented as a single bit in SMI_SCI_LEVEL register. + * + * In a similar fashion, polarity (rising/falling, hi/lo) of each GPE is + * represented as a single bit in SMI_SCI_TRIG register. + */ +static void fill_sci_trigger(uint32_t trigger, int gpe, struct sci_trigger_regs *regs) +{ + uint32_t mask = 1 << gpe; + + regs->mask |= mask; + + /* Select level vs. edge triggered event. */ + if ((trigger == GPIO_TRIGGER_LEVEL_LOW) || (trigger == GPIO_TRIGGER_LEVEL_HIGH)) + regs->level |= mask; + else + regs->level &= ~mask; + + /* Select rising/high vs falling/low trigger. */ + if ((trigger == GPIO_TRIGGER_EDGE_HIGH) || (trigger == GPIO_TRIGGER_LEVEL_HIGH)) + regs->polarity |= mask; + else + regs->polarity &= ~mask; +} + +/* TODO: See configure_scimap() implementations. */ +static void set_sci_trigger(const struct sci_trigger_regs *regs) +{ + uint32_t value; + + value = smi_read32(SMI_SCI_TRIG); + value &= ~regs->mask; + value |= regs->polarity; + smi_write32(SMI_SCI_TRIG, value); + + value = smi_read32(SMI_SCI_LEVEL); + value &= ~regs->mask; + value |= regs->level; + smi_write32(SMI_SCI_LEVEL, value); } uintptr_t gpio_get_address(gpio_t gpio_num) @@ -166,17 +183,13 @@ void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) { uint32_t *gpio_ptr; - uint32_t control, control_flags, edge_level, direction; - uint32_t mask, bit_edge, bit_level; + uint32_t control, control_flags; uint8_t mux, index, gpio; int gevent_num; const struct soc_amd_event *gev_tbl; + struct sci_trigger_regs sci_trigger_cfg = { 0 }; size_t gev_items; - direction = 0; - edge_level = 0; - mask = 0; - /* * Disable blocking wake/interrupt status generation while updating * debounce registers. Otherwise when a debounce register is updated @@ -227,16 +240,16 @@ case GPIO_SMI_FLAG: mem_read_write32(gpio_ptr, control, INT_SCI_SMI_MASK); - program_smi(control_flags, gevent_num); + + program_smi(control_flags & FLAGS_TRIGGER_MASK, gevent_num); break; case GPIO_SCI_FLAG: mem_read_write32(gpio_ptr, control, INT_SCI_SMI_MASK); - get_sci_config_bits(control_flags, &bit_edge, - &bit_level); - edge_level |= bit_edge << gevent_num; - direction |= bit_level << gevent_num; - mask |= (1 << gevent_num); + + fill_sci_trigger(control_flags & FLAGS_TRIGGER_MASK, gevent_num, + &sci_trigger_cfg); + soc_route_sci(gevent_num); break; default: @@ -259,11 +272,8 @@ */ master_switch_set(GPIO_INTERRUPT_EN); - /* Set all SCI trigger direction (high/low) */ - mem_read_write32((void *)(acpimmio_smi + SMI_SCI_TRIG), direction, mask); - - /* Set all SCI trigger level (edge/level) */ - mem_read_write32((void *)(acpimmio_smi + SMI_SCI_LEVEL), edge_level, mask); + /* Set all SCI trigger polarity (high/low) and level (edge/level). */ + set_sci_trigger(&sci_trigger_cfg); } int gpio_interrupt_status(gpio_t gpio) diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index da65e08..4a8a5ae 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -114,8 +114,6 @@ }; #define GPIO_TRIGGER_INVALID -1 -#define SCI_TRIGGER_EDGE 0 -#define SCI_TRIGGER_LEVEL 1 #define GPIO_SPECIAL_FLAG (1 << 31) #define GPIO_DEBOUNCE_FLAG (1 << 30) -- To view, visit https://review.coreboot.org/c/coreboot/+/42687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2c7cd70ab38d0d8e745b0a611b780d2b0b8dc5b Gerrit-Change-Number: 42687 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common: Refactor GPIO_MASTER_SWITCH interrupt enable
by Patrick Georgi (Code Review) 29 Jun '20

29 Jun '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42686 ) Change subject: soc/amd/common: Refactor GPIO_MASTER_SWITCH interrupt enable ...................................................................... soc/amd/common: Refactor GPIO_MASTER_SWITCH interrupt enable There is no GPIO_63 but the register position is used for interrupt controls. Change-Id: I754a2f6bbee12d637f8c99a9d330ab0ac8187247 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42686 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 15 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 9125308..c5f8e98 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -105,6 +105,18 @@ __gpio_update32(gpio_num, -1UL, or); } +static void master_switch_clr(uint32_t mask) +{ + const uint8_t master_reg = GPIO_MASTER_SWITCH / sizeof(uint32_t); + __gpio_and32(master_reg, ~mask); +} + +static void master_switch_set(uint32_t or) +{ + const uint8_t master_reg = GPIO_MASTER_SWITCH / sizeof(uint32_t); + __gpio_or32(master_reg, or); +} + int gpio_get(gpio_t gpio_num) { uint32_t reg; @@ -153,7 +165,7 @@ void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) { - uint32_t *gpio_ptr, *inter_master; + uint32_t *gpio_ptr; uint32_t control, control_flags, edge_level, direction; uint32_t mask, bit_edge, bit_level; uint8_t mux, index, gpio; @@ -161,7 +173,6 @@ const struct soc_amd_event *gev_tbl; size_t gev_items; - inter_master = (void *)(acpimmio_gpio0 + GPIO_MASTER_SWITCH); direction = 0; edge_level = 0; mask = 0; @@ -176,7 +187,7 @@ * Additionally disable interrupt generation so we don't get any * spurious interrupts while updating the registers. */ - mem_read_write32(inter_master, 0, GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN); + master_switch_clr(GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN); soc_get_gpio_event_table(&gev_tbl, &gev_items); @@ -246,7 +257,7 @@ * debounce registers while the drivers load. This will cause interrupts * to be missed during boot. */ - mem_read_write32(inter_master, GPIO_INTERRUPT_EN, GPIO_INTERRUPT_EN); + master_switch_set(GPIO_INTERRUPT_EN); /* Set all SCI trigger direction (high/low) */ mem_read_write32((void *)(acpimmio_smi + SMI_SCI_TRIG), direction, mask); -- To view, visit https://review.coreboot.org/c/coreboot/+/42686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I754a2f6bbee12d637f8c99a9d330ab0ac8187247 Gerrit-Change-Number: 42686 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: [WIP] soc/amd/common/blocks: Drop ACPIMMIO gpio1_ and gpio2_ banks
by Kyösti Mälkki (Code Review) 29 Jun '20

29 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42522 ) Change subject: [WIP] soc/amd/common/blocks: Drop ACPIMMIO gpio1_ and gpio2_ banks ...................................................................... [WIP] soc/amd/common/blocks: Drop ACPIMMIO gpio1_ and gpio2_ banks The banks are one after each other in the ACPIMMIO space. Also there is space for more banks and existing ASL takes advantage of this property. Change-Id: Ib78559a60b5c20d53a60e1726ee2aad1f38f78ce Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h 3 files changed, 0 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/42522/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 60a9efd..c5f82f9 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -22,8 +22,6 @@ DECLARE_ACPIMMIO(acpimmio_misc, MISC); DECLARE_ACPIMMIO(acpimmio_dpvga, DPVGA); DECLARE_ACPIMMIO(acpimmio_gpio0, GPIO0); -DECLARE_ACPIMMIO(acpimmio_gpio1, GPIO1); -DECLARE_ACPIMMIO(acpimmio_gpio2, GPIO2); DECLARE_ACPIMMIO(acpimmio_xhci_pm, XHCIPM); DECLARE_ACPIMMIO(acpimmio_acdc_tmr, ACDCTMR); DECLARE_ACPIMMIO(acpimmio_aoac, AOAC); diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 3d0a17b..3caed11 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -344,68 +344,6 @@ write32(acpimmio_gpio0 + reg, value); } -/* GPIO bank 1 */ -static inline uint8_t gpio1_read8(uint8_t reg) -{ - return read8(acpimmio_gpio1 + reg); -} - -static inline uint16_t gpio1_read16(uint8_t reg) -{ - return read16(acpimmio_gpio1 + reg); -} - -static inline uint32_t gpio1_read32(uint8_t reg) -{ - return read32(acpimmio_gpio1 + reg); -} - -static inline void gpio1_write8(uint8_t reg, uint8_t value) -{ - write8(acpimmio_gpio1 + reg, value); -} - -static inline void gpio1_write16(uint8_t reg, uint16_t value) -{ - write16(acpimmio_gpio1 + reg, value); -} - -static inline void gpio1_write32(uint8_t reg, uint32_t value) -{ - write32(acpimmio_gpio1 + reg, value); -} - -/* GPIO bank 2 */ -static inline uint8_t gpio2_read8(uint8_t reg) -{ - return read8(acpimmio_gpio2 + reg); -} - -static inline uint16_t gpio2_read16(uint8_t reg) -{ - return read16(acpimmio_gpio2 + reg); -} - -static inline uint32_t gpio2_read32(uint8_t reg) -{ - return read32(acpimmio_gpio2 + reg); -} - -static inline void gpio2_write8(uint8_t reg, uint8_t value) -{ - write8(acpimmio_gpio2 + reg, value); -} - -static inline void gpio2_write16(uint8_t reg, uint16_t value) -{ - write16(acpimmio_gpio2 + reg, value); -} - -static inline void gpio2_write32(uint8_t reg, uint32_t value) -{ - write32(acpimmio_gpio2 + reg, value); -} - static inline uint8_t xhci_pm_read8(uint8_t reg) { return read8(acpimmio_xhci_pm + reg); diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 5d1e881..912e891 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -178,8 +178,6 @@ extern uint8_t *MAYBE_CONST acpimmio_misc; extern uint8_t *MAYBE_CONST acpimmio_dpvga; extern uint8_t *MAYBE_CONST acpimmio_gpio0; -extern uint8_t *MAYBE_CONST acpimmio_gpio1; -extern uint8_t *MAYBE_CONST acpimmio_gpio2; extern uint8_t *MAYBE_CONST acpimmio_xhci_pm; extern uint8_t *MAYBE_CONST acpimmio_acdc_tmr; extern uint8_t *MAYBE_CONST acpimmio_aoac; -- To view, visit https://review.coreboot.org/c/coreboot/+/42522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib78559a60b5c20d53a60e1726ee2aad1f38f78ce Gerrit-Change-Number: 42522 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Change pmc_set_acpi_mode() run after BS_DEV_INIT.
by William Wei (Code Review) 29 Jun '20

29 Jun '20

William Wei has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42677 ) Change subject: soc/intel/tigerlake: Change pmc_set_acpi_mode() run after BS_DEV_INIT. ...................................................................... soc/intel/tigerlake: Change pmc_set_acpi_mode() run after BS_DEV_INIT. pmc_set_acpi_mode() should run after Chrome EC deal with all host event bits, like SMI mask (otherwise the FAFT firmware_FWScreenCloseLid test will fail.) BUG=b:153249055 TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage Change the GBB flag to 0x140 then check SMI mask during depthcharge phase, make sure it's 0x0000000000000001. Signed-off-by: William Wei <wenxu.wei(a)bitland.corp-partner.google.com> Change-Id: Icfff5cc5550f23938343e4d26ef76093bb9cf7c3 --- M src/soc/intel/tigerlake/pmc.c 1 file changed, 25 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42677/1 diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 4d89870..a65aeb8 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -7,6 +7,7 @@ */ #include <acpi/acpigen.h> +#include <bootstate.h> #include <console/console.h> #include <device/mmio.h> #include <device/device.h> @@ -77,8 +78,6 @@ pmc_set_power_failure_state(true); pmc_gpe_init(); - pmc_set_acpi_mode(); - config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); config_deep_sx(config->deep_sx_config); @@ -142,6 +141,30 @@ return child; } +static void soc_acpi_mode_init(void *unused) +{ + /* + * PMC initialization happens earlier for this SoC because FSP-Silicon + * init hides PMC from PCI bus. However, pmc_set_acpi_mode, which + * disables ACPI mode doesn't need to happen that early and can be + * delayed till typical BS_DEV_INIT. This ensures that ACPI mode + * disabling happens the same way for all SoCs and hence the ordering of + * events is the same. + * + * This is important to ensure that the ordering does not break the + * assumptions of any other drivers (e.g. ChromeEC) which could be + * taking different actions based on disabling of ACPI (e.g. flushing of + * all EC hostevent bits). + * + * P.S.: This cannot be done as part of pmc_soc_init as PMC device is + * hidden and hence the PMC driver never gets enumerated and so init is + * not called for it. + */ + pmc_set_acpi_mode(); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_acpi_mode_init, NULL); + struct device_operations pmc_ops = { .read_resources = soc_pmc_read_resources, .set_resources = noop_set_resources, -- To view, visit https://review.coreboot.org/c/coreboot/+/42677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfff5cc5550f23938343e4d26ef76093bb9cf7c3 Gerrit-Change-Number: 42677 Gerrit-PatchSet: 1 Gerrit-Owner: William Wei <wenxu.wei(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Pass GNVS as parameter to SMM module
by Kyösti Mälkki (Code Review) 29 Jun '20

29 Jun '20

Hello build bot (Jenkins), David Guckian, Furquan Shaikh, Vanessa Eusebio, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42427 to look at the new patch set (#6). Change subject: arch/x86: Pass GNVS as parameter to SMM module ...................................................................... arch/x86: Pass GNVS as parameter to SMM module Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/smm/smm_module_handler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c 28 files changed, 5 insertions(+), 184 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/42427/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/42427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Gerrit-Change-Number: 42427 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Pass GNVS as parameter to SMM module
by Kyösti Mälkki (Code Review) 29 Jun '20

29 Jun '20

Hello build bot (Jenkins), David Guckian, Furquan Shaikh, Vanessa Eusebio, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42427 to look at the new patch set (#5). Change subject: arch/x86: Pass GNVS as parameter to SMM module ...................................................................... arch/x86: Pass GNVS as parameter to SMM module Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/smm/smm_module_handler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c 28 files changed, 3 insertions(+), 180 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/42427/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/42427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Gerrit-Change-Number: 42427 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Pass GNVS as parameter to SMM module
by Kyösti Mälkki (Code Review) 29 Jun '20

29 Jun '20

Hello build bot (Jenkins), David Guckian, Furquan Shaikh, Vanessa Eusebio, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42427 to look at the new patch set (#4). Change subject: arch/x86: Pass GNVS as parameter to SMM module ...................................................................... arch/x86: Pass GNVS as parameter to SMM module Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/smm/smm_module_handler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c 28 files changed, 3 insertions(+), 177 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/42427/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/42427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Gerrit-Change-Number: 42427 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/intel/i82801gx,ix,jx: Drop invalid GNVS update routine
by Kyösti Mälkki (Code Review) 29 Jun '20

29 Jun '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42426 to look at the new patch set (#6). Change subject: sb/intel/i82801gx,ix,jx: Drop invalid GNVS update routine ...................................................................... sb/intel/i82801gx,ix,jx: Drop invalid GNVS update routine The smm_setup_structures() calls placed GNVS address into register %ebx. Old code on i82801dx used these low memory addresses. Change-Id: I407b9b9fd44db027a62356e2470f6c39ed3bff49 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c 3 files changed, 9 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42426/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/42426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I407b9b9fd44db027a62356e2470f6c39ed3bff49 Gerrit-Change-Number: 42426 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI F...
by Johnny Lin (Code Review) 29 Jun '20

29 Jun '20

Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Patrick Rudolph, Jonathan Zhang, Maxim Polyakov, David Hendricks, Jingle Hsu, Morgan Jang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40308 to look at the new patch set (#46). Change subject: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data ...................................................................... drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data It implements the SMBIOS IPMI FRU mapping table defined in https://www.opencompute.org/documents/facebook-xeon-motherboard-v31 22.3 SMBIOS FRU mapping table. Mainboard needs to configure the correct values for FRU_DEVICE_ID and BMC_KCS_BASE. For type 11 string 1 to 6 are common and implemented in this driver, the rest are project dependent and can be added in the mainboard code. Tested on OCP Tioga Pass. Change-Id: I08c958dfad83216cd12545760a19d205efc2515b Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- A src/drivers/ocp/dmi/Kconfig A src/drivers/ocp/dmi/Makefile.inc A src/drivers/ocp/dmi/ocp_dmi.h A src/drivers/ocp/dmi/smbios.c 4 files changed, 324 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/40308/46 -- To view, visit https://review.coreboot.org/c/coreboot/+/40308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c958dfad83216cd12545760a19d205efc2515b Gerrit-Change-Number: 40308 Gerrit-PatchSet: 46 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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