coreboot-gerrit June 2020

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Change in coreboot[master]: mb/google/zork: update DRAM SPD table for morphius
by Kevin Chiu (Code Review) 28 Jun '20

28 Jun '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42816 ) Change subject: mb/google/zork: update DRAM SPD table for morphius ...................................................................... mb/google/zork: update DRAM SPD table for morphius Add Samsung K4A8G165WC-BCWE x2 BUG=b:159418770 BRANCH=master TEST=emerge-zork coreboot Change-Id: I200a1074d3c9fe79a8a2c69f42b0612e745f36f5 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/morphius/spd/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42816/1 diff --git a/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc index 4f0929f..080d468 100644 --- a/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc @@ -18,7 +18,7 @@ APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0110 APCB_SOURCES += samsung-K4AAG165WA-BCWE_x2 # 0b0111 APCB_SOURCES += hynix-H5ANAG6NCMR-XNC_x2 # 0b1000 -APCB_SOURCES += empty # 0b1001 +APCB_SOURCES += samsung-K4A8G165WC-BCWE_x2 # 0b1001 APCB_SOURCES += empty # 0b1010 APCB_SOURCES += empty # 0b1011 APCB_SOURCES += empty # 0b1100 -- To view, visit https://review.coreboot.org/c/coreboot/+/42816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I200a1074d3c9fe79a8a2c69f42b0612e745f36f5 Gerrit-Change-Number: 42816 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/reef/variants/: add Samsung K4F8E3S4HD-MGCL support
by Kevin Chiu (Code Review) 28 Jun '20

28 Jun '20

Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42772 to review the following change. Change subject: mb/google/reef/variants/: add Samsung K4F8E3S4HD-MGCL support ...................................................................... mb/google/reef/variants/: add Samsung K4F8E3S4HD-MGCL support Add Samsung K4F8E3S4HD-MGCL DRAM support. DRAMID: 0x8 BUG=b:145094527 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Ic450c4abebfeaed050a7b8fcae74b87a148dd5cd Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/reef/variants/baseboard/memory.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/42772/1 diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c index 260b6fa..aac160b 100644 --- a/src/mainboard/google/reef/variants/baseboard/memory.c +++ b/src/mainboard/google/reef/variants/baseboard/memory.c @@ -131,6 +131,13 @@ .ch1_rank_density = LP4_16Gb_DENSITY, .part_num = "K4F6E3S4HM-MGCJ", }, + /* K4F8E3S4HD-MGCL - both logical channels */ + [8] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "K4F8E3S4HD-MGCL", + }, }; static const struct lpddr4_cfg lp4cfg = { -- To view, visit https://review.coreboot.org/c/coreboot/+/42772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic450c4abebfeaed050a7b8fcae74b87a148dd5cd Gerrit-Change-Number: 42772 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: Makefile.inc: Simplify fsp submodule check
by Angel Pons (Code Review) 28 Jun '20

28 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42778 ) Change subject: Makefile.inc: Simplify fsp submodule check ...................................................................... Makefile.inc: Simplify fsp submodule check TEST=Building Asrock H110M using FSP from repo updates the submodule. Change-Id: I25023af88d878353a04db456009249da67e41521 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/42778/1 diff --git a/Makefile.inc b/Makefile.inc index 7f61a5e..bbb6685 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -196,7 +196,7 @@ # until expressly requested and enabled with --checkout forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs)) forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode)) -ifeq ($(CONFIG_PLATFORM_USES_FSP1_0)$(CONFIG_PLATFORM_USES_FSP1_1)$(CONFIG_PLATFORM_USES_FSP2_0),y) +ifeq ($(CONFIG_FSP_USE_REPO),y) forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp)) endif ifeq ($(CONFIG_USE_AMD_BLOBS),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/42778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25023af88d878353a04db456009249da67e41521 Gerrit-Change-Number: 42778 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/xeon_sp/cpx: Define MSR PPIN related registers
by Johnny Lin (Code Review) 28 Jun '20

28 Jun '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41278 ) Change subject: soc/xeon_sp/cpx: Define MSR PPIN related registers ...................................................................... soc/xeon_sp/cpx: Define MSR PPIN related registers These changes are in accordance with the documentation: [*] page 208-209 Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US Tested on OCP DeltaLake with change https://review.coreboot.org/c/coreboot/+/40308/ Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Change-Id: I87134b2e98c9b0c031be9375b75a2aa1284ae9bb --- M src/soc/intel/xeon_sp/cpx/include/soc/msr.h 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/41278/1 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/msr.h b/src/soc/intel/xeon_sp/cpx/include/soc/msr.h index 6004490..b3eede7 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/msr.h @@ -110,4 +110,13 @@ #define EPB_ENERGY_POLICY_SHIFT 3 #define EPB_ENERGY_POLICY_MASK (0xf << EPB_ENERGY_POLICY_SHIFT) +/* MSR Protected Processor Inventory Number */ +#define MSR_PPIN_CTL 0x04e +#define MSR_PPIN_CTL_LOCK 0x1 +#define MSR_PPIN_CTL_ENABLE_SHIFT 1 +#define MSR_PPIN_CTL_ENABLE (0x1 << MSR_PPIN_CTL_ENABLE_SHIFT) +#define MSR_PPIN 0x04f +#define MSR_PPIN_CAP_SHIFT 23 +#define MSR_PPIN_CAP (0x1 << MSR_PPIN_CAP_SHIFT) + #endif /* _SOC_MSR_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87134b2e98c9b0c031be9375b75a2aa1284ae9bb Gerrit-Change-Number: 41278 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: drivers/ipmi: Read all FRU data fields for Product, Board and Chassis...
by Johnny Lin (Code Review) 28 Jun '20

28 Jun '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40522 ) Change subject: drivers/ipmi: Read all FRU data fields for Product, Board and Chassis Info ...................................................................... drivers/ipmi: Read all FRU data fields for Product, Board and Chassis Info Tested on OCP Tioga Pass Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Change-Id: Ib05fdb34b2b324b6eb766de15727668ce91d2844 --- M src/drivers/ipmi/ipmi_fru.c M src/drivers/ipmi/ipmi_ops.h 2 files changed, 174 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/40522/1 diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c index c16b8f6..cecaa0b 100644 --- a/src/drivers/ipmi/ipmi_fru.c +++ b/src/drivers/ipmi/ipmi_fru.c @@ -211,40 +211,44 @@ return ret; } -static void read_fru_board_info_area(const int port, const uint8_t id, +static enum cb_err read_fru_board_info_area(const int port, const uint8_t id, uint8_t offset, struct fru_board_info *info) { uint8_t length; struct ipmi_read_fru_data_req req; - uint8_t *data_ptr; + uint8_t *data_ptr, *end, *custom_data_ptr; + int ret = CB_SUCCESS; + + if (!offset) + return CB_ERR; offset = offset * OFFSET_LENGTH_MULTIPLIER; - if (!offset) - return; req.fru_device_id = id; /* Read Board Info Area length first. */ req.fru_offset = offset + 1; req.count = sizeof(length); if (ipmi_read_fru(port, &req, &length) != CB_SUCCESS || !length) { printk(BIOS_ERR, "%s failed, length: %d\n", __func__, length); - return; + return CB_ERR; } length = length * OFFSET_LENGTH_MULTIPLIER; data_ptr = (uint8_t *)malloc(length); if (!data_ptr) { printk(BIOS_ERR, "malloc %d bytes for board info failed\n", length); - return; + return CB_ERR; } - + end = data_ptr + length; /* Read Board Info Area data. */ req.fru_offset = offset; req.count = length; if (ipmi_read_fru(port, &req, data_ptr) != CB_SUCCESS) { printk(BIOS_ERR, "%s failed to read fru\n", __func__); + ret = CB_ERR; goto out; } if (checksum(data_ptr, length)) { printk(BIOS_ERR, "Bad FRU board info checksum.\n"); + ret = CB_ERR; goto out; } printk(BIOS_DEBUG, "Read board manufacturer string\n"); @@ -263,45 +267,86 @@ data_ptr += length + 1; length = read_data_string(data_ptr, &info->part_number); + printk(BIOS_DEBUG, "Read board FRU file ID string.\n"); + data_ptr += length + 1; + length = read_data_string(data_ptr, &info->fru_file_id); + + /* Check how many valid custom fields first. */ + info->custom_count = 0; + custom_data_ptr = data_ptr; + while ((data_ptr < end) && ((data_ptr[0] != FRU_END_OF_FIELDS))) { + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) + info->custom_count++; + data_ptr += length + 1; + } + if (!info->custom_count) + goto out; + + info->board_custom = malloc(info->custom_count * sizeof(char *)); + if (!info->board_custom) { + printk(BIOS_ERR, "%s failed to malloc %ld bytes for " + "board custom data array.\n", __func__, + info->custom_count * sizeof(char *)); + ret = CB_ERR; + goto out; + } + + /* Start reading custom board data. */ + data_ptr = custom_data_ptr; + int count = 0; + while ((data_ptr < end) && ((data_ptr[0] != FRU_END_OF_FIELDS))) { + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + length = read_data_string(data_ptr, info->board_custom + count); + count++; + } + data_ptr += length + 1; + } + out: free(data_ptr); + return ret; } -static void read_fru_product_info_area(const int port, const uint8_t id, +static enum cb_err read_fru_product_info_area(const int port, const uint8_t id, uint8_t offset, struct fru_product_info *info) { uint8_t length; struct ipmi_read_fru_data_req req; - uint8_t *data_ptr; + uint8_t *data_ptr, *end, *custom_data_ptr; + int ret = CB_SUCCESS; + + if (!offset) + return CB_ERR; offset = offset * OFFSET_LENGTH_MULTIPLIER; - if (!offset) - return; - req.fru_device_id = id; /* Read Product Info Area length first. */ req.fru_offset = offset + 1; req.count = sizeof(length); if (ipmi_read_fru(port, &req, &length) != CB_SUCCESS || !length) { printk(BIOS_ERR, "%s failed, length: %d\n", __func__, length); - return; + return CB_ERR; } length = length * OFFSET_LENGTH_MULTIPLIER; data_ptr = (uint8_t *)malloc(length); if (!data_ptr) { printk(BIOS_ERR, "malloc %d bytes for product info failed\n", length); - return; + return CB_ERR; } - + end = data_ptr + length; /* Read Product Info Area data. */ req.fru_offset = offset; req.count = length; if (ipmi_read_fru(port, &req, data_ptr) != CB_SUCCESS) { printk(BIOS_ERR, "%s failed to read fru\n", __func__); + ret = CB_ERR; goto out; } if (checksum(data_ptr, length)) { printk(BIOS_ERR, "Bad FRU product info checksum.\n"); + ret = CB_ERR; goto out; } printk(BIOS_DEBUG, "Read product manufacturer string.\n"); @@ -328,8 +373,46 @@ printk(BIOS_DEBUG, "Read asset tag string.\n"); length = read_data_string(data_ptr, &info->asset_tag); + printk(BIOS_DEBUG, "Read product FRU file ID string.\n"); + data_ptr += length + 1; + length = read_data_string(data_ptr, &info->fru_file_id); + + /* Check how many valid custom fields first. */ + info->custom_count = 0; + custom_data_ptr = data_ptr; + while ((data_ptr < end) && ((data_ptr[0] != FRU_END_OF_FIELDS))) { + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) + info->custom_count++; + data_ptr += length + 1; + } + if (!info->custom_count) + goto out; + + info->product_custom = malloc(info->custom_count * sizeof(char *)); + if (!info->product_custom) { + printk(BIOS_ERR, "%s failed to malloc %ld bytes for " + "product custom data array.\n", __func__, + info->custom_count * sizeof(char *)); + ret = CB_ERR; + goto out; + } + + /* Start reading custom board data. */ + data_ptr = custom_data_ptr; + int count = 0; + while ((data_ptr < end) && ((data_ptr[0] != FRU_END_OF_FIELDS))) { + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + length = read_data_string(data_ptr, info->product_custom + count); + count++; + } + data_ptr += length + 1; + } + out: free(data_ptr); + return ret; } void read_fru_areas(const int port, const uint8_t id, uint16_t offset, @@ -420,3 +503,69 @@ break; } } + +void print_fru_areas(struct fru_info_str *fru_info_str) +{ + int count = 0; + if (fru_info_str == NULL) { + printk(BIOS_ERR, "FRU data is null pointer\n"); + return; + } + struct fru_product_info prod_info = fru_info_str->prod_info; + struct fru_board_info board_info = fru_info_str->board_info; + struct fru_chassis_info chassis_info = fru_info_str->chassis_info; + + printk(BIOS_DEBUG, "Printing Product Info Area...\n"); + if (prod_info.manufacturer != NULL) + printk(BIOS_DEBUG, "manufacturer: %s\n", prod_info.manufacturer); + if (prod_info.product_name != NULL) + printk(BIOS_DEBUG, "product name: %s\n", prod_info.product_name); + if (prod_info.product_partnumber != NULL) + printk(BIOS_DEBUG, "product part numer: %s\n", prod_info.product_partnumber); + if (prod_info.product_version != NULL) + printk(BIOS_DEBUG, "product version: %s\n", prod_info.product_version); + if (prod_info.serial_number != NULL) + printk(BIOS_DEBUG, "serial number: %s\n", prod_info.serial_number); + if (prod_info.asset_tag != NULL) + printk(BIOS_DEBUG, "asset tag: %s\n", prod_info.asset_tag); + if (prod_info.fru_file_id != NULL) + printk(BIOS_DEBUG, "FRU file ID: %s\n", prod_info.fru_file_id); + + for (count = 0; count < prod_info.custom_count; count++) { + if (*(prod_info.product_custom + count) != NULL) + printk(BIOS_DEBUG, "product custom data %i: %s\n", count, + *(prod_info.product_custom + count)); + } + + printk(BIOS_DEBUG, "Printing Board Info Area...\n"); + if (board_info.manufacturer != NULL) + printk(BIOS_DEBUG, "manufacturer: %s\n", board_info.manufacturer); + if (board_info.product_name != NULL) + printk(BIOS_DEBUG, "product name: %s\n", board_info.product_name); + if (board_info.serial_number != NULL) + printk(BIOS_DEBUG, "serial number: %s\n", board_info.serial_number); + if (board_info.part_number != NULL) + printk(BIOS_DEBUG, "part number: %s\n", board_info.part_number); + if (board_info.fru_file_id != NULL) + printk(BIOS_DEBUG, "FRU file ID: %s\n", board_info.fru_file_id); + + for (count = 0; count < board_info.custom_count; count++) { + if (*(board_info.board_custom + count) != NULL) + printk(BIOS_DEBUG, "board custom data %i: %s\n", count, + *(board_info.board_custom + count)); + } + + printk(BIOS_DEBUG, "Printing Chassis Info Area...\n"); + printk(BIOS_DEBUG, "chassis type: %d\n", chassis_info.chassis_type); + if (chassis_info.chassis_partnumber != NULL) + printk(BIOS_DEBUG, "part number: %s\n", chassis_info.chassis_partnumber); + if (chassis_info.serial_number != NULL) + printk(BIOS_DEBUG, "serial number: %s\n", chassis_info.serial_number); + + for (count = 0; count < chassis_info.custom_count; count++) { + if (*(chassis_info.chassis_custom + count) != NULL) + printk(BIOS_DEBUG, "chassis custom data %i: %s\n", count, + *(chassis_info.chassis_custom + count)); + } + +} diff --git a/src/drivers/ipmi/ipmi_ops.h b/src/drivers/ipmi/ipmi_ops.h index a6d9e59..dbc0c79 100644 --- a/src/drivers/ipmi/ipmi_ops.h +++ b/src/drivers/ipmi/ipmi_ops.h @@ -110,6 +110,9 @@ char *product_version; char *serial_number; char *asset_tag; + char *fru_file_id; + char **product_custom; + int custom_count; /* Number of custom fields */ }; struct fru_board_info { @@ -117,6 +120,9 @@ char *product_name; char *serial_number; char *part_number; + char *fru_file_id; + char **board_custom; + int custom_count; }; struct fru_chassis_info { @@ -124,7 +130,7 @@ char *chassis_partnumber; char *serial_number; char **chassis_custom; - int custom_count; /* Number of custom fields */ + int custom_count; }; struct fru_info_str { @@ -173,4 +179,7 @@ /* Add a SEL record entry, returns CB_SUCCESS on success and CB_ERR * if an error occurred */ enum cb_err ipmi_add_sel(const int port, struct sel_event_record *sel); + +/* Print all IPMI read FRU data */ +void print_fru_areas(struct fru_info_str *fru_info_str); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/40522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib05fdb34b2b324b6eb766de15727668ce91d2844 Gerrit-Change-Number: 40522 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/faffy: Enable USB2 port6
by Tim Chen (Code Review) 28 Jun '20

28 Jun '20

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42766 to review the following change. Change subject: mb/google/faffy: Enable USB2 port6 ...................................................................... mb/google/faffy: Enable USB2 port6 Due to faffy has PL-2303 connect to USB2 port6(count from port0), needs to enable it. BUG=b:159760559 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage boot on puff board Change-Id: Icc805757b043e7fac4d05188cbf2f9c9c56c2a2e Signed-off-by: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/faffy/overridetree.cb 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/42766/1 diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb index 55ce5ea..ffb9cb3 100644 --- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb @@ -62,7 +62,14 @@ .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[6]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # PL2303 register "usb2_ports[7]" = "USB2_PORT_EMPTY" register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/42766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc805757b043e7fac4d05188cbf2f9c9c56c2a2e Gerrit-Change-Number: 42766 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/amd/mandolin: factor out EMMC GPIO pin mux setup
by Felix Held (Code Review) 28 Jun '20

28 Jun '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42842 ) Change subject: mb/amd/mandolin: factor out EMMC GPIO pin mux setup ...................................................................... mb/amd/mandolin: factor out EMMC GPIO pin mux setup This also makes the calling of the EMMC GPIO mux setup function conditional on PICASSO_LPC_IOMUX instead of AMD_LPC_DEBUG_CARD which only makes the selection of PICASSO_LPC_IOMUX user-configurable. Change-Id: Ic49a668f82fbc1b851c07d312b543d2889fe4734 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/emmc_gpio.c M src/mainboard/amd/mandolin/gpio.c M src/mainboard/amd/mandolin/gpio.h M src/mainboard/amd/mandolin/mainboard.c 5 files changed, 38 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/42842/1 diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index 56dd5e2..761c3f8 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -6,6 +6,10 @@ ramstage-y += gpio.c ramstage-y += port_descriptors.c +ifneq ($(CONFIG_PICASSO_LPC_IOMUX),y) +ramstage-y += emmc_gpio.c +endif # CONFIG_PICASSO_LPC_IOMUX + # APCB_mandolin.bin APCB_SOURCES = mandolin diff --git a/src/mainboard/amd/mandolin/emmc_gpio.c b/src/mainboard/amd/mandolin/emmc_gpio.c new file mode 100644 index 0000000..2ae72a6 --- /dev/null +++ b/src/mainboard/amd/mandolin/emmc_gpio.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include "gpio.h" + +/* eMMC controller driving either an SD card or eMMC device. */ +static const struct soc_amd_gpio emmc_gpios[] = { + PAD_NF(GPIO_21, EMMC_CMD, PULL_UP), + PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_UP), + PAD_NF(GPIO_68, EMMC_CD, PULL_UP), + PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), + PAD_NF(GPIO_104, EMMC_DATA0, PULL_UP), + PAD_NF(GPIO_105, EMMC_DATA1, PULL_UP), + PAD_NF(GPIO_106, EMMC_DATA2, PULL_UP), + PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), + PAD_NF(GPIO_74, EMMC_DATA4, PULL_UP), + PAD_NF(GPIO_75, EMMC_DATA6, PULL_UP), + PAD_NF(GPIO_87, EMMC_DATA7, PULL_UP), + PAD_NF(GPIO_88, EMMC_DATA5, PULL_UP), + PAD_NF(GPIO_109, EMMC_DS, PULL_UP), +}; + +/* Don't call this if the board uses the LPC bus. */ +void mainboard_program_emmc_gpios(void) +{ + program_gpios(emmc_gpios, ARRAY_SIZE(emmc_gpios)); +} diff --git a/src/mainboard/amd/mandolin/gpio.c b/src/mainboard/amd/mandolin/gpio.c index a60f00e..0d2e2fa 100644 --- a/src/mainboard/amd/mandolin/gpio.c +++ b/src/mainboard/amd/mandolin/gpio.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <soc/gpio.h> - #include "gpio.h" /* @@ -32,30 +30,7 @@ PAD_GPO(GPIO_89, HIGH), }; -/* eMMC controller driving either an SD card or eMMC device. */ -static const struct soc_amd_gpio emmc_gpios[] = { - PAD_NF(GPIO_21, EMMC_CMD, PULL_UP), - PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_UP), - PAD_NF(GPIO_68, EMMC_CD, PULL_UP), - PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), - PAD_NF(GPIO_104, EMMC_DATA0, PULL_UP), - PAD_NF(GPIO_105, EMMC_DATA1, PULL_UP), - PAD_NF(GPIO_106, EMMC_DATA2, PULL_UP), - PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), - PAD_NF(GPIO_74, EMMC_DATA4, PULL_UP), - PAD_NF(GPIO_75, EMMC_DATA6, PULL_UP), - PAD_NF(GPIO_87, EMMC_DATA7, PULL_UP), - PAD_NF(GPIO_88, EMMC_DATA5, PULL_UP), - PAD_NF(GPIO_109, EMMC_DS, PULL_UP), -}; - void mainboard_program_gpios(void) { program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram)); - - /* Re-muxing LPCCLK0 can hang the system if LPC is in use. */ - if (CONFIG(AMD_LPC_DEBUG_CARD)) - printk(BIOS_INFO, "eMMC not available due to LPC requirement\n"); - else - program_gpios(emmc_gpios, ARRAY_SIZE(emmc_gpios)); } diff --git a/src/mainboard/amd/mandolin/gpio.h b/src/mainboard/amd/mandolin/gpio.h index 04c98c5..f4d0b5c 100644 --- a/src/mainboard/amd/mandolin/gpio.h +++ b/src/mainboard/amd/mandolin/gpio.h @@ -5,5 +5,6 @@ void mainboard_program_early_gpios(void); /* bootblock GPIO configuration */ void mainboard_program_gpios(void); /* ramstage GPIO configuration */ +void mainboard_program_emmc_gpios(void); /* ramstage EMMC pin mux configuration */ #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index c0b9dac..c22ed34 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -115,6 +115,12 @@ cfg->sd_emmc_config = SD_EMMC_EMMC_HS400; mainboard_program_gpios(); + + /* Re-muxing LPCCLK0 can hang the system if LPC is in use. */ + if (CONFIG(PICASSO_LPC_IOMUX)) + printk(BIOS_INFO, "eMMC not available due to LPC requirement\n"); + else + mainboard_program_emmc_gpios(); } static void mandolin_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/42842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic49a668f82fbc1b851c07d312b543d2889fe4734 Gerrit-Change-Number: 42842 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: mb/amd/mandolin: factor out port descriptors from mainboard.c
by Felix Held (Code Review) 28 Jun '20

28 Jun '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42784 ) Change subject: mb/amd/mandolin: factor out port descriptors from mainboard.c ...................................................................... mb/amd/mandolin: factor out port descriptors from mainboard.c Change-Id: Ia2101cc0bae0d68cea1954424d18833aa22670c6 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/Makefile.inc M src/mainboard/amd/mandolin/mainboard.c A src/mainboard/amd/mandolin/port_descriptors.c 3 files changed, 212 insertions(+), 208 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42784/1 diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index 52ad9c6..56dd5e2 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -4,6 +4,7 @@ bootblock-y += early_gpio.c ramstage-y += gpio.c +ramstage-y += port_descriptors.c # APCB_mandolin.bin APCB_SOURCES = mandolin diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index 2e66c65..c0b9dac 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -8,8 +8,6 @@ #include <soc/cpu.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> -#include <soc/platform_descriptors.h> -#include <soc/soc_util.h> #include <types.h> #include <commonlib/helpers.h> #include <chip.h> @@ -119,212 +117,6 @@ mainboard_program_gpios(); } -static const fsp_pcie_descriptor pco_pcie_descriptors[] = { - { /* MXM */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 8, - .end_lane = 15, - .device_number = 1, - .function_number = 1, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ6 - }, - { /* SSD */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 0, - .end_lane = 1, - .device_number = 1, - .function_number = 7, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ5 - }, - { /* WLAN */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 4, - .end_lane = 4, - .device_number = 1, - .function_number = 2, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0 - }, - { /* LAN */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 5, - .end_lane = 5, - .device_number = 1, - .function_number = 3, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1 - }, - { /* WWAN */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 2, - .end_lane = 2, - .device_number = 1, - .function_number = 4, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ2 - }, - { /* WIFI */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 3, - .end_lane = 3, - .gpio_group_id = 1, - .device_number = 1, - .function_number = 5, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ3 - }, - { /* SATA EXPRESS */ - .port_present = true, - .engine_type = SATA_ENGINE, - .start_lane = 6, - .end_lane = 7, - .gpio_group_id = 1, - .channel_type = SATA_CHANNEL_LONG, - } -}; - -static const fsp_pcie_descriptor dali_pcie_descriptors[] = { - { // MXM - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 8, - .end_lane = 11, - .device_number = 1, - .function_number = 1, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ6 - }, - { // SSD - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 0, - .end_lane = 1, - .device_number = 1, - .function_number = 7, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ5 - }, - { // WLAN - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 4, - .end_lane = 4, - .device_number = 1, - .function_number = 2, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0 - }, - { // LAN - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 5, - .end_lane = 5, - .device_number = 1, - .function_number = 3, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1 - } -}; - -static const fsp_ddi_descriptor pco_ddi_descriptors[] = { - { // DDI0 - DP - .connector_type = DP, - .aux_index = AUX1, - .hdp_index = HDP1 - }, - { /* DDI1 - eDP */ - .connector_type = EDP, - .aux_index = AUX2, - .hdp_index = HDP2 - }, - { /* DDI2 - DP */ - .connector_type = DP, - .aux_index = AUX3, - .hdp_index = HDP3, - }, - { /* DDI3 - DP */ - .connector_type = DP, - .aux_index = AUX4, - .hdp_index = HDP4, - } -}; - -static const fsp_ddi_descriptor dali_ddi_descriptors[] = { - { // DDI0 - DP - .connector_type = DP, - .aux_index = AUX1, - .hdp_index = HDP1 - }, - { // DDI1 - eDP - .connector_type = EDP, - .aux_index = AUX2, - .hdp_index = HDP2 - }, - { // DDI2 - DP - .connector_type = DP, - .aux_index = AUX3, - .hdp_index = HDP3, - } -}; - -void mainboard_get_pcie_ddi_descriptors( - const fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, - const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) -{ - /* Dali */ - if (soc_is_dali()) { - *pcie_descs = dali_pcie_descriptors; - *pcie_num = ARRAY_SIZE(dali_pcie_descriptors); - *ddi_descs = dali_ddi_descriptors; - *ddi_num = ARRAY_SIZE(dali_ddi_descriptors); - } - /* Picasso and default */ - else { - *pcie_descs = pco_pcie_descriptors; - *pcie_num = ARRAY_SIZE(pco_pcie_descriptors); - *ddi_descs = pco_ddi_descriptors; - *ddi_num = ARRAY_SIZE(pco_ddi_descriptors); - } -} - static void mandolin_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/mandolin/port_descriptors.c b/src/mainboard/amd/mandolin/port_descriptors.c new file mode 100644 index 0000000..436c63d --- /dev/null +++ b/src/mainboard/amd/mandolin/port_descriptors.c @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/platform_descriptors.h> +#include <soc/soc_util.h> +#include <types.h> + +static const fsp_pcie_descriptor pco_pcie_descriptors[] = { + { /* MXM */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 8, + .end_lane = 15, + .device_number = 1, + .function_number = 1, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ6 + }, + { /* SSD */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 0, + .end_lane = 1, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ5 + }, + { /* WLAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 4, + .end_lane = 4, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0 + }, + { /* LAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 5, + .end_lane = 5, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1 + }, + { /* WWAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 2, + .end_lane = 2, + .device_number = 1, + .function_number = 4, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2 + }, + { /* WIFI */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 3, + .end_lane = 3, + .gpio_group_id = 1, + .device_number = 1, + .function_number = 5, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ3 + }, + { /* SATA EXPRESS */ + .port_present = true, + .engine_type = SATA_ENGINE, + .start_lane = 6, + .end_lane = 7, + .gpio_group_id = 1, + .channel_type = SATA_CHANNEL_LONG, + } +}; + +static const fsp_pcie_descriptor dali_pcie_descriptors[] = { + { /* MXM */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 8, + .end_lane = 11, + .device_number = 1, + .function_number = 1, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ6 + }, + { /* SSD */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 0, + .end_lane = 1, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ5 + }, + { /* WLAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 4, + .end_lane = 4, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0 + }, + { /* LAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 5, + .end_lane = 5, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1 + } +}; + +static const fsp_ddi_descriptor pco_ddi_descriptors[] = { + { /* DDI0 - DP */ + .connector_type = DP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { /* DDI1 - eDP */ + .connector_type = EDP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { /* DDI2 - DP */ + .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + }, + { /* DDI3 - DP */ + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +static const fsp_ddi_descriptor dali_ddi_descriptors[] = { + { /* DDI0 - DP */ + .connector_type = DP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { /* DDI1 - eDP */ + .connector_type = EDP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { /* DDI2 - DP */ + .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + } +}; + +void mainboard_get_pcie_ddi_descriptors( + const fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + /* Dali */ + if (soc_is_dali()) { + *pcie_descs = dali_pcie_descriptors; + *pcie_num = ARRAY_SIZE(dali_pcie_descriptors); + *ddi_descs = dali_ddi_descriptors; + *ddi_num = ARRAY_SIZE(dali_ddi_descriptors); + } + /* Picasso and default */ + else { + *pcie_descs = pco_pcie_descriptors; + *pcie_num = ARRAY_SIZE(pco_pcie_descriptors); + *ddi_descs = pco_ddi_descriptors; + *ddi_num = ARRAY_SIZE(pco_ddi_descriptors); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2101cc0bae0d68cea1954424d18833aa22670c6 Gerrit-Change-Number: 42784 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: soc/amd/picasso/soc_util: add function to detect defeatured SKU
by Felix Held (Code Review) 28 Jun '20

28 Jun '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42833 ) Change subject: soc/amd/picasso/soc_util: add function to detect defeatured SKU ...................................................................... soc/amd/picasso/soc_util: add function to detect defeatured SKU Change-Id: I9eb57595da6f806305552128b0c077ceeb7c4661 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/include/soc/soc_util.h M src/soc/amd/picasso/soc_util.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/42833/1 diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h index 2459207..e7f13d4 100644 --- a/src/soc/amd/picasso/include/soc/soc_util.h +++ b/src/soc/amd/picasso/include/soc/soc_util.h @@ -39,4 +39,7 @@ /* function to determine the iGPU type */ bool soc_is_raven2(void); +/* function to determine if SoC has less USB and PCIe lanes */ +bool soc_is_defeatured_sku(void); + #endif /* __PICASSO_SOC_UTIL_H__ */ diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c index 2aa9daa..8a1f8ef 100644 --- a/src/soc/amd/picasso/soc_util.c +++ b/src/soc/amd/picasso/soc_util.c @@ -208,3 +208,8 @@ { return get_silicon_type() == SILICON_RV2; } + +bool soc_is_defeatured_sku(void) +{ + return get_silicon_type() == SILICON_RV2 || get_soc_type() == SOC_DALI; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9eb57595da6f806305552128b0c077ceeb7c4661 Gerrit-Change-Number: 42833 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

4 20

Change in coreboot[master]: soc/intel: Configure PAVP at compile-time
by Paul Menzel (Code Review) 28 Jun '20

28 Jun '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42745 ) Change subject: soc/intel: Configure PAVP at compile-time ...................................................................... Patch Set 5: (3 comments) https://review.coreboot.org/c/coreboot/+/42745/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42745/5//COMMIT_MSG@11 PS5, Line 11: What is the FSP default? Please mention, that for Jasper Lake it’s enabled now by default. https://review.coreboot.org/c/coreboot/+/42745/5/src/soc/intel/common/Kconf… File src/soc/intel/common/Kconfig.common: https://review.coreboot.org/c/coreboot/+/42745/5/src/soc/intel/common/Kconf… PS5, Line 40: Set this option to n to disable support Please add a dot/period at the end. https://review.coreboot.org/c/coreboot/+/42745/5/src/soc/intel/common/Kconf… PS5, Line 33: config PAVP : bool "Enable PAVP (Protected Audio-Video Path) support" : default y : help : Protected Audio-Video Path is an Intel technology used to enforce : digital rights protections on multimedia content. : : Set this option to n to disable support Could you please extend this a little bit, why disabling this option might be wanted? Will it save energy, or shut down certain hardware blocks? -- To view, visit https://review.coreboot.org/c/coreboot/+/42745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Gerrit-Change-Number: 42745 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 28 Jun 2020 07:49:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2020