coreboot-gerrit June 2020

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Change in coreboot[master]: sb/intel/i82801ix: Use common early SPI code
by Angel Pons (Code Review) 27 Jun '20

27 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42663 ) Change subject: sb/intel/i82801ix: Use common early SPI code ...................................................................... sb/intel/i82801ix: Use common early SPI code Change-Id: Iafcf7aecb20b4c8be79fa562ff267fd54f672862 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801ix/bootblock.c 1 file changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/42663/1 diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index 479c588..7a66b47 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -2,16 +2,12 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> +#include <southbridge/intel/common/early_spi.h> #include "i82801ix.h" -static void enable_spi_prefetch(void) -{ - pci_update_config8(PCI_DEV(0, 0x1f, 0), 0xdc, ~(3 << 2), 2 << 2); -} - void bootblock_early_southbridge_init(void) { - enable_spi_prefetch(); + enable_spi_prefetching_and_caching(); i82801ix_early_init(); i82801ix_lpc_setup(); -- To view, visit https://review.coreboot.org/c/coreboot/+/42663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafcf7aecb20b4c8be79fa562ff267fd54f672862 Gerrit-Change-Number: 42663 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801gx: Use common early SPI code
by Angel Pons (Code Review) 27 Jun '20

27 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42662 ) Change subject: sb/intel/i82801gx: Use common early SPI code ...................................................................... sb/intel/i82801gx: Use common early SPI code Change-Id: I44de4698d062508dd24f37b37014e09d95726c71 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801gx/bootblock.c 1 file changed, 2 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/42662/1 diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index b0f73e8..51fb24f 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -2,22 +2,12 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> +#include <southbridge/intel/common/early_spi.h> #include "i82801gx.h" -static void enable_spi_prefetch(void) -{ - u8 reg8; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, BIOS_CNTL, reg8); -} - void bootblock_early_southbridge_init(void) { - enable_spi_prefetch(); + enable_spi_prefetching_and_caching(); i82801gx_setup_bars(); -- To view, visit https://review.coreboot.org/c/coreboot/+/42662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44de4698d062508dd24f37b37014e09d95726c71 Gerrit-Change-Number: 42662 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x: Use common early SPI code
by Angel Pons (Code Review) 27 Jun '20

27 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42661 ) Change subject: sb/intel/bd82x6x: Use common early SPI code ...................................................................... sb/intel/bd82x6x: Use common early SPI code Change-Id: If4843e93c993ed2de60b2b6064c2c9e98637ce9a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/bootblock.c 1 file changed, 2 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/42661/1 diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 3a99f51..a3228e7 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -2,16 +2,9 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> +#include <southbridge/intel/common/early_spi.h> #include "pch.h" -/* - * Enable Prefetching and Caching. - */ -static void enable_spi_prefetch(void) -{ - pci_update_config8(PCH_LPC_DEV, BIOS_CNTL, ~(3 << 2), 2 << 2); -} - static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC */ @@ -40,7 +33,7 @@ void bootblock_early_southbridge_init(void) { - enable_spi_prefetch(); + enable_spi_prefetching_and_caching(); early_pch_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/42661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4843e93c993ed2de60b2b6064c2c9e98637ce9a Gerrit-Change-Number: 42661 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common: Add early SPI code
by Angel Pons (Code Review) 27 Jun '20

27 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42660 ) Change subject: sb/intel/common: Add early SPI code ...................................................................... sb/intel/common: Add early SPI code All Intel southbridges with SPI perform this write. Put it inside a function in common code. Use a different name to avoid a name clash. Change-Id: I3c284d6cffd22949d50b4c4f9846ceaef38d7cda Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/early_spi.c A src/southbridge/intel/common/early_spi.h 3 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/42660/1 diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index b3c48fa..3ebc5fb 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -24,6 +24,8 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += early_spi.c + all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c ifeq ($(CONFIG_SPI_FLASH_SMM),y) smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c diff --git a/src/southbridge/intel/common/early_spi.c b/src/southbridge/intel/common/early_spi.c new file mode 100644 index 0000000..77e2309 --- /dev/null +++ b/src/southbridge/intel/common/early_spi.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <southbridge/intel/common/early_spi.h> + +void enable_spi_prefetching_and_caching(void) +{ + pci_update_config8(PCI_DEV(0, 0x1f, 0), BIOS_CNTL, ~(3 << 2), 2 << 2); +} diff --git a/src/southbridge/intel/common/early_spi.h b/src/southbridge/intel/common/early_spi.h new file mode 100644 index 0000000..618cc9d --- /dev/null +++ b/src/southbridge/intel/common/early_spi.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_EARLY_SPI_H +#define SOUTHBRIDGE_INTEL_COMMON_EARLY_SPI_H + +#define BIOS_CNTL 0xDC + +void enable_spi_prefetching_and_caching(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c284d6cffd22949d50b4c4f9846ceaef38d7cda Gerrit-Change-Number: 42660 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI F...
by Johnny Lin (Code Review) 27 Jun '20

27 Jun '20

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40308 ) Change subject: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data ...................................................................... Patch Set 45: (4 comments) https://review.coreboot.org/c/coreboot/+/40308/44//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40308/44//COMMIT_MSG@12 PS44, Line 12: Need to configure the correct values for FRU_DEVICE_ID and BMC_KCS_BASE. > "Mainboard needs to configure" Done https://review.coreboot.org/c/coreboot/+/40308/23/src/drivers/ocp/dmi/Kconf… File src/drivers/ocp/dmi/Kconfig: https://review.coreboot.org/c/coreboot/+/40308/23/src/drivers/ocp/dmi/Kconf… PS23, Line 14: config BMC_KCS_BASE > For ramstage maybe I can add a global variable for it and sets it during ipmi_kcs_init() from dev->p […] I add a CONFIG_BMC_KCS to https://review.coreboot.org/c/coreboot/+/40234/31/src/drivers/ipmi/Kconfig#… and all code should use CONFIG_BMC_KCS whenever it needs a hard-coded address to avoid duplicate definitions. https://review.coreboot.org/c/coreboot/+/40308/44/src/drivers/ocp/dmi/ocp_d… File src/drivers/ocp/dmi/ocp_dmi.h: https://review.coreboot.org/c/coreboot/+/40308/44/src/drivers/ocp/dmi/ocp_d… PS44, Line 6: #include <cpu/x86/msr.h> > Do we need to include this header file? This is needed because of extern msr_t xeon_sp_ppin[] below. I added ARCH_X86 dependency to https://review.coreboot.org/c/coreboot/+/40308/45/src/drivers/ocp/dmi/Kconf… Because from the FB OCP specification it defines the PPIN requirement which should be ARCH_X86 dependent. https://review.coreboot.org/c/coreboot/+/40308/44/src/drivers/ocp/dmi/ocp_d… PS44, Line 15: extern msr_t xeon_sp_ppin[]; > All the PPIN related code are x86 specific. […] The PPIN in OCP spec is x86 dependent, so I still need put it here just to read and store them to a global array for lafter access from mainboard (SET PPIN to BMC). Unless it's better to move the read PPIN functions (maybe including the msr_t global array) to xeon_sp and call it here. -- To view, visit https://review.coreboot.org/c/coreboot/+/40308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c958dfad83216cd12545760a19d205efc2515b Gerrit-Change-Number: 40308 Gerrit-PatchSet: 45 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 27 Jun 2020 04:06:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI F...
by Johnny Lin (Code Review) 27 Jun '20

27 Jun '20

Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Patrick Rudolph, Jonathan Zhang, Maxim Polyakov, David Hendricks, Jingle Hsu, Morgan Jang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40308 to look at the new patch set (#45). Change subject: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data ...................................................................... drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data It implements the SMBIOS IPMI FRU mapping table defined in https://www.opencompute.org/documents/facebook-xeon-motherboard-v31 22.3 SMBIOS FRU mapping table. Mainboard needs to configure the correct values for FRU_DEVICE_ID and BMC_KCS_BASE. For type 11 string 1 to 6 are common and implemented in this driver, the rest are project dependent and can be added in the mainboard code. Tested on OCP Tioga Pass. Change-Id: I08c958dfad83216cd12545760a19d205efc2515b Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- A src/drivers/ocp/dmi/Kconfig A src/drivers/ocp/dmi/Makefile.inc A src/drivers/ocp/dmi/ocp_dmi.h A src/drivers/ocp/dmi/smbios.c 4 files changed, 324 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/40308/45 -- To view, visit https://review.coreboot.org/c/coreboot/+/40308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c958dfad83216cd12545760a19d205efc2515b Gerrit-Change-Number: 40308 Gerrit-PatchSet: 45 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Revert "Mushu: Enable PCIe 1d.4 to enable dgpu"
by Shelley Chen (Code Review) 26 Jun '20

26 Jun '20

Hello build bot (Jenkins), Patrick Georgi, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42583 to review the following change. Change subject: Revert "Mushu: Enable PCIe 1d.4 to enable dgpu" ...................................................................... Revert "Mushu: Enable PCIe 1d.4 to enable dgpu" This reverts commit 1408798637125f1707ded7215e22461c623a79a8. Reason for revert: Causing backlight issues in device. Will reland after more debugging to figure out the root cause. BUG=b:159370566 BRANCH=None TEST=boot up device and make sure when kernel is booted, backlight comes up. Change-Id: I643854c6c805d262539bbb482808e8c322059a49 --- M src/mainboard/google/hatch/variants/mushu/overridetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/42583/1 diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 100f7d5..db86d68 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -185,7 +185,6 @@ device i2c 1a on end end end #I2C #4 - device pci 1d.4 on end # PCI Express port 13 device pci 1e.3 on chip drivers/spi/acpi register "name" = ""CRFP"" -- To view, visit https://review.coreboot.org/c/coreboot/+/42583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I643854c6c805d262539bbb482808e8c322059a49 Gerrit-Change-Number: 42583 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: Refactor GPIO SCI/SMI interrupts
by Raul Rangel (Code Review) 26 Jun '20

26 Jun '20

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42687 ) Change subject: soc/amd/common: Refactor GPIO SCI/SMI interrupts ...................................................................... Patch Set 8: Code-Review+2 (3 comments) https://review.coreboot.org/c/coreboot/+/42687/5/src/soc/amd/common/block/g… File src/soc/amd/common/block/gpio_banks/gpio.c: https://review.coreboot.org/c/coreboot/+/42687/5/src/soc/amd/common/block/g… PS5, Line 52: sci_trigger_regs > Left as a followup exercise due the requested change of name 'level' to 'trigger' which calls for a […] Ack https://review.coreboot.org/c/coreboot/+/42687/5/src/soc/amd/common/block/g… PS5, Line 55: level > And have a field named trigger not being written to register named trigger? I find that equally conf […] Ack https://review.coreboot.org/c/coreboot/+/42687/5/src/soc/amd/common/block/g… PS5, Line 94: SMI_SCI_LEVEL > Not my choice. I have assumed these match the datasheets. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/42687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2c7cd70ab38d0d8e745b0a611b780d2b0b8dc5b Gerrit-Change-Number: 42687 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 26 Jun 2020 21:24:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in em100[master]: spi.c: Some fixes to the write_dfifo routine
by Stefan Reinauer (Code Review) 26 Jun '20

26 Jun '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/42571 ) Change subject: spi.c: Some fixes to the write_dfifo routine ...................................................................... spi.c: Some fixes to the write_dfifo routine Change-Id: I25867012e644b825f0a352dacb20e9df3a0c0720 --- M spi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/71/42571/1 diff --git a/spi.c b/spi.c index 1ac7004..c088a11 100644 --- a/spi.c +++ b/spi.c @@ -287,13 +287,13 @@ } printf ("Transfer %s\n",bytes_sent == length ? "Succeeded" : "Failed"); - if (bytes_sent == length) + if (bytes_sent != length) printf("Warning: Sent %zd bytes, expected %zd\n", bytes_sent, length); int len = get_response(em100->dev, data, 512); - if (len == 1 && data[0] == length) { + if (len == 2 && (((size_t)data[0] << 8) | data[1]) == length) { return 1; } return 0; -- To view, visit https://review.coreboot.org/c/em100/+/42571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I25867012e644b825f0a352dacb20e9df3a0c0720 Gerrit-Change-Number: 42571 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/rockchip: Use (Q) instead of @
by Stefan Reinauer (Code Review) 26 Jun '20

26 Jun '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42818 ) Change subject: soc/rockchip: Use (Q) instead of @ ...................................................................... soc/rockchip: Use (Q) instead of @ This way make V=1 will tell you what it's actually doing. Change-Id: I096bc2419e47a0b2a2454a792059464b27158cd9 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M src/soc/rockchip/rk3288/Makefile.inc M src/soc/rockchip/rk3399/Makefile.inc 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/42818/1 diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 527c04d..075fa36 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -62,7 +62,7 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" - @mkdir -p $(dir $@) - @$(IDBTOOL) --from=$< --to=$@ --enable-align --chip=RK32 + $(Q)mkdir -p $(dir $@) + $(Q)$(IDBTOOL) --from=$< --to=$@ --enable-align --chip=RK32 endif diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 763e11a..8521bf3 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -69,7 +69,7 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" - @mkdir -p $(dir $@) - @$(IDBTOOL) --from=$< --to=$@ --enable-align --chip=RK33 + $(Q)mkdir -p $(dir $@) + $(Q)$(IDBTOOL) --from=$< --to=$@ --enable-align --chip=RK33 endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I096bc2419e47a0b2a2454a792059464b27158cd9 Gerrit-Change-Number: 42818 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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coreboot-gerrit June 2020