Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41758 )
Change subject: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT
......................................................................
Patch Set 16:
(3 comments)
https://review.coreboot.org/c/coreboot/+/41758/15/src/mainboard/intel/jaspe…
File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/41758/15/src/mainboard/intel/jaspe…
PS15, Line 374: CAM1
> This is not the correct name for the power resource, it was "PRIC". […]
Done
https://review.coreboot.org/c/coreboot/+/41758/15/src/mainboard/intel/jaspe…
PS15, Line 387: register "chip_name" = ""Camera and Imaging Subsystem"
> Nit: this line probably isn't needed. […]
Done
https://review.coreboot.org/c/coreboot/+/41758/15/src/mainboard/intel/jaspe…
PS15, Line 397: pci 05.0 on end # RP4
> This is not producing any output, exploring on adding a minimal IPU PCI driver.
Done
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Hello Varshit B Pandya, build bot (Jenkins), Daniel Kang, Wonkyu Kim, Rizwan Qureshi, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#16).
Change subject: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT
......................................................................
mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT
This change updates devicetree to enable camera SSDT generation and removes
changes related to camera DSDT.
Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
---
M src/mainboard/intel/jasperlake_rvp/Kconfig
M src/mainboard/intel/jasperlake_rvp/dsdt.asl
D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl
D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl
D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl
D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
D src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl
M src/soc/intel/jasperlake/chip.c
9 files changed, 112 insertions(+), 334 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/41758/16
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Hello build bot (Jenkins),
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Change subject: soc/amd/common: Avoid aliasing on ACPIMMIO writes
......................................................................
soc/amd/common: Avoid aliasing on ACPIMMIO writes
With runtime configuration of base addresses, these
pointers are subject to aliasing on write8(). The impact
on code size is very small with iomux and biosram regions,
there is some unnecessary reloading of base address from
memory to register.
Declaring ACPIMMIO banks as arrays appears to sometimes
create more dense x86 assembly.
Change-Id: I7369b8b07a23e9b52c2961c527dc8d29ad4b505b
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/soc/amd/common/block/acpimmio/biosram.c
M src/soc/amd/common/block/acpimmio/mmio_util.c
M src/soc/amd/common/block/gpio_banks/gpio.c
M src/soc/amd/common/block/include/amdblocks/acpimmio.h
4 files changed, 40 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/42692/6
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Hello build bot (Jenkins), Raul Rangel,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/common: Refactor single GPIO programming
......................................................................
soc/amd/common: Refactor single GPIO programming
Make it clearer all the GPIO bank register programming
parameters originate from the same soc_amd_gpio entry.
Change-Id: I7aa6bd6996fd14dde4b1abcccbd2ae6ef933c87b
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/soc/amd/common/block/gpio_banks/gpio.c
1 file changed, 39 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/42691/6
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Hello build bot (Jenkins), Raul Rangel,
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Change subject: soc/amd/common: Complete ACPIMMIO GPIO bank separation
......................................................................
soc/amd/common: Complete ACPIMMIO GPIO bank separation
Move GPIO bank and IOMUX accessors away from global scope.
Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/soc/amd/common/block/acpimmio/mmio_util.c
M src/soc/amd/common/block/gpio_banks/gpio.c
M src/soc/amd/common/block/include/amdblocks/acpimmio.h
3 files changed, 45 insertions(+), 153 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/42690/6
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Change subject: [WIP,RFC] soc/amd/common: Move sb_reset_i2c_slaves()
......................................................................
[WIP,RFC] soc/amd/common: Move sb_reset_i2c_slaves()
Code needs full control over GPIO and IOMUX banks, maybe
better to implement inside GPIO scope.
Could it even move to drivers/i2c/designware ?
Change-Id: I4e761236fc0602babb9a96956b143ecd0d2c61de
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/soc/amd/common/block/gpio_banks/gpio.c
M src/soc/amd/picasso/i2c.c
M src/soc/amd/stoneyridge/i2c.c
3 files changed, 80 insertions(+), 143 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/42689/7
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42733 )
Change subject: [WIP] sb/amd/pi/hudson: Fixes for common GPIO API
......................................................................
Patch Set 3:
This is WIP because <gpio.h> forces the existence of <soc/gpio.h>. Not sure what the best approach here would be.
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Hello build bot (Jenkins), Raul Rangel, Martin Roth, Aaron Durbin,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/common: Refactor GPIO_MASTER_SWITCH interrupt enable
......................................................................
soc/amd/common: Refactor GPIO_MASTER_SWITCH interrupt enable
There is no GPIO_63 but the register position is used for
interrupt controls.
Change-Id: I754a2f6bbee12d637f8c99a9d330ab0ac8187247
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/soc/amd/common/block/gpio_banks/gpio.c
1 file changed, 15 insertions(+), 4 deletions(-)
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42708 )
Change subject: AGESA fam14: Use AMD_ACPIMMIO_GPIO_BASE_100
......................................................................
Patch Set 6:
(2 comments)
> Patch Set 3: Code-Review+1
>
> Could you please add a comment in src/soc/amd/common/block/include/amdblocks/acpimmio_map.h describing this only applies to certain families? That macro is not correct for all chipsets.
https://review.coreboot.org/c/coreboot/+/42708/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/42708/2//COMMIT_MSG@9
PS2, Line 9: direclty
> directly
Done
https://review.coreboot.org/c/coreboot/+/42708/4/src/soc/amd/common/block/i…
File src/soc/amd/common/block/include/amdblocks/acpimmio_map.h:
https://review.coreboot.org/c/coreboot/+/42708/4/src/soc/amd/common/block/i…
PS4, Line 36: /* Family 14h or before */
> works for me.
Removed the comment here, added more details to CB:37324.
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