Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42688 )
Change subject: soc/amd/common: Use gpio_setbits32()
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42688/6/src/soc/amd/common/block/g…
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42688/6/src/soc/amd/common/block/g…
PS6, Line 221: __gpio_setbits32
> I am actually working on changing this to `gpio_write32()`. […]
Whatever works for you. That mem_read_write32() was just too obscure to my eyes.
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Gerrit-Change-Number: 42688
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42687 )
Change subject: soc/amd/common: Refactor GPIO SCI/SMI interrupts
......................................................................
Patch Set 8:
(4 comments)
https://review.coreboot.org/c/coreboot/+/42687/4/src/soc/amd/common/block/g…
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42687/4/src/soc/amd/common/block/g…
PS4, Line 73: regs->polarity &= ~mask;
> It'd be helpful to add comments to handling of LEVEL vs EDGE stanzas here.
Done
https://review.coreboot.org/c/coreboot/+/42687/5/src/soc/amd/common/block/g…
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42687/5/src/soc/amd/common/block/g…
PS5, Line 52: sci_trigger_regs
> Since you are deleting the SCI_TRIGGER_X macros, you add a comment saying 0 -> Low, 1 -> High for th […]
Left as a followup exercise due the requested change of name 'level' to 'trigger' which calls for a rewrite on such added comment too.
https://review.coreboot.org/c/coreboot/+/42687/5/src/soc/amd/common/block/g…
PS5, Line 55: level
> Can you name this trigger? Level makes me think Level high or Level low. […]
And have a field named trigger not being written to register named trigger? I find that equally confusing.
https://review.coreboot.org/c/coreboot/+/42687/5/src/soc/amd/common/block/g…
PS5, Line 94: SMI_SCI_LEVEL
> I hate the name of these registers.
Not my choice. I have assumed these match the datasheets.
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42834 )
Change subject: mb/mandolin/devicetree: clarify that Ethernet devices are internal MACs
......................................................................
mb/mandolin/devicetree: clarify that Ethernet devices are internal MACs
Change-Id: Ib7d696f4cc8f5fdcdf45e271b36664d085eb16d5
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/mainboard/amd/mandolin/devicetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/42834/1
diff --git a/src/mainboard/amd/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/devicetree.cb
index 709778d..495961f 100644
--- a/src/mainboard/amd/mandolin/devicetree.cb
+++ b/src/mainboard/amd/mandolin/devicetree.cb
@@ -59,8 +59,8 @@
end
device pci 8.2 on # Bridge to Bus B
device pci 0.0 on end # AHCI
- device pci 0.1 off end # Ethernet
- device pci 0.2 off end # Ethernet
+ device pci 0.1 off end # integrated Ethernet MAC
+ device pci 0.2 off end # integrated Ethernet MAC
end
device pci 14.0 on # SM
chip drivers/generic/generic # dimm 0-0-0
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42782 )
Change subject: mb/amd/mandolin/devicetree: disable unused internal ethernet controllers
......................................................................
mb/amd/mandolin/devicetree: disable unused internal ethernet controllers
Change-Id: Id4c7ec02f37b35bbc36d40bb937b962cc6413d17
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/mainboard/amd/mandolin/devicetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/42782/1
diff --git a/src/mainboard/amd/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/devicetree.cb
index 179582b..d94084c 100644
--- a/src/mainboard/amd/mandolin/devicetree.cb
+++ b/src/mainboard/amd/mandolin/devicetree.cb
@@ -59,8 +59,8 @@
end
device pci 8.2 on # Bridge to Bus B
device pci 0.0 on end # AHCI
- device pci 0.1 on end # Ethernet
- device pci 0.2 on end # Ethernet
+ device pci 0.1 off end # Ethernet
+ device pci 0.2 off end # Ethernet
end
device pci 14.0 on # SM
chip drivers/generic/generic # dimm 0-0-0
--
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42688 )
Change subject: soc/amd/common: Use gpio_setbits32()
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42688/6/src/soc/amd/common/block/g…
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42688/6/src/soc/amd/common/block/g…
PS6, Line 221: __gpio_setbits32
I am actually working on changing this to `gpio_write32()`. This will allow us to not add multiple entries for the same pad in the mainboard GPIO table. I am fine if you want to get this in. I can work on top of this.
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42687 )
Change subject: soc/amd/common: Refactor GPIO SCI/SMI interrupts
......................................................................
Patch Set 7:
I see there are some opens from Raul on patchset#5.
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