coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: AGESA fam14: Use AMD_ACPIMMIO_GPIO_BASE_100
by Kyösti Mälkki (Code Review) 26 Jun '20

26 Jun '20

Hello build bot (Jenkins), Raul Rangel, Paul Menzel, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42708 to look at the new patch set (#6). Change subject: AGESA fam14: Use AMD_ACPIMMIO_GPIO_BASE_100 ...................................................................... AGESA fam14: Use AMD_ACPIMMIO_GPIO_BASE_100 Use the pre-defined constant address directly. Change-Id: I29fbc82fffc69b864adb4ddbda1425db98e2e48a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/inagua/BiosCallOuts.c M src/mainboard/amd/persimmon/BiosCallOuts.c M src/mainboard/amd/south_station/BiosCallOuts.c M src/mainboard/amd/union_station/BiosCallOuts.c M src/mainboard/asrock/e350m1/BiosCallOuts.c M src/mainboard/elmex/pcm205400/BiosCallOuts.c M src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c 7 files changed, 12 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/42708/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/42708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29fbc82fffc69b864adb4ddbda1425db98e2e48a Gerrit-Change-Number: 42708 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: AGESA fam14: Use AMD_ACPIMMIO_GPIO_BASE_100
by Kyösti Mälkki (Code Review) 26 Jun '20

26 Jun '20

Hello build bot (Jenkins), Raul Rangel, Paul Menzel, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42708 to look at the new patch set (#5). Change subject: AGESA fam14: Use AMD_ACPIMMIO_GPIO_BASE_100 ...................................................................... AGESA fam14: Use AMD_ACPIMMIO_GPIO_BASE_100 Use the pre-defined constant address direclty. Change-Id: I29fbc82fffc69b864adb4ddbda1425db98e2e48a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/inagua/BiosCallOuts.c M src/mainboard/amd/persimmon/BiosCallOuts.c M src/mainboard/amd/south_station/BiosCallOuts.c M src/mainboard/amd/union_station/BiosCallOuts.c M src/mainboard/asrock/e350m1/BiosCallOuts.c M src/mainboard/elmex/pcm205400/BiosCallOuts.c M src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c 7 files changed, 12 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/42708/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/42708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29fbc82fffc69b864adb4ddbda1425db98e2e48a Gerrit-Change-Number: 42708 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/prodrive/hermes: Enable EIST in DeviceTree
by Christian Walter (Code Review) 26 Jun '20

26 Jun '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42777 ) Change subject: mainboard/prodrive/hermes: Enable EIST in DeviceTree ...................................................................... mainboard/prodrive/hermes: Enable EIST in DeviceTree Enable EIST option in the devicetree in order to make Windows aware of using Intel CPU Turbo Technology. Change-Id: Ied3d7e934fcab2d5d491573245d68d392df5ba34 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42777/1 diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 3388239..93bae80 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -131,6 +131,9 @@ # Disable S0ix register "s0ix_enable" = "0" + # Enable Turbo + register "eist_enable" = "1" + register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/42777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied3d7e934fcab2d5d491573245d68d392df5ba34 Gerrit-Change-Number: 42777 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
by Sridhar Siricilla (Code Review) 26 Jun '20

26 Jun '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42441 ) Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ...................................................................... mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms Currently, coreboot doesn't set UPD FSPS PchPmPwrCycDur (Reset Power Cycle Duration). So, FSP set default value(4sec) to PchPmPwrCycDur. This adds around ~5 seconds of delay during power cycle or global reset. So, this patch set PchPmPwrCycDur to 1 second to minimize the delay. System behaviour for Power Cylce or Global Reset: With default value: S0->S3->S5 -> [~5 seconds delay]-> S5->S3->S0 With the change: S0->S3->S5 -> [~2 seconds delay]-> S5->S3->S0 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42441/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 2d3156a..04221af 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -143,6 +143,7 @@ register "PchPmSlpS4MinAssert" = "1" # 1s register "PchPmSlpSusMinAssert" = "1" # 500ms register "PchPmSlpAMinAssert" = "3" # 2s + register "PchPmPwrCycDur" = "1" # 1s # Enable Audio DSP oscillator qualification for S0ix register "cppmvric2_adsposcdis" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/42441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd Gerrit-Change-Number: 42441 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: add psp_verstage
by build bot (Jenkins) (Code Review) 26 Jun '20

26 Jun '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41816 ) Change subject: soc/amd/picasso: add psp_verstage ...................................................................... Patch Set 10: (10 comments) https://review.coreboot.org/c/coreboot/+/41816/10/src/soc/amd/picasso/psp_v… File src/soc/amd/picasso/psp_verstage/svc.h: https://review.coreboot.org/c/coreboot/+/41816/10/src/soc/amd/picasso/psp_v… PS10, Line 6: #define SVC_CALL4(SVC_ID, R0, R1, R2, R3, Ret) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/c/coreboot/+/41816/10/src/soc/amd/picasso/psp_v… PS10, Line 6: #define SVC_CALL4(SVC_ID, R0, R1, R2, R3, Ret) \ macros should not use a trailing semicolon https://review.coreboot.org/c/coreboot/+/41816/10/src/soc/amd/picasso/psp_v… PS10, Line 19: #define SVC_CALL3(SVC_ID, R0, R1, R2, Ret) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/c/coreboot/+/41816/10/src/soc/amd/picasso/psp_v… PS10, Line 19: #define SVC_CALL3(SVC_ID, R0, R1, R2, Ret) \ macros should not use a trailing semicolon https://review.coreboot.org/c/coreboot/+/41816/10/src/soc/amd/picasso/psp_v… PS10, Line 30: #define SVC_CALL2(SVC_ID, R0, R1, Ret) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/c/coreboot/+/41816/10/src/soc/amd/picasso/psp_v… PS10, Line 30: #define SVC_CALL2(SVC_ID, R0, R1, Ret) \ macros should not use a trailing semicolon https://review.coreboot.org/c/coreboot/+/41816/10/src/soc/amd/picasso/psp_v… PS10, Line 40: #define SVC_CALL1(SVC_ID, R0, Ret) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/c/coreboot/+/41816/10/src/soc/amd/picasso/psp_v… PS10, Line 40: #define SVC_CALL1(SVC_ID, R0, Ret) \ macros should not use a trailing semicolon https://review.coreboot.org/c/coreboot/+/41816/10/src/soc/amd/picasso/psp_v… PS10, Line 49: #define SVC_CALL0(SVC_ID, Ret) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/c/coreboot/+/41816/10/src/soc/amd/picasso/psp_v… PS10, Line 49: #define SVC_CALL0(SVC_ID, Ret) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/41816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 Gerrit-Change-Number: 41816 Gerrit-PatchSet: 10 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 26 Jun 2020 00:07:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: add psp_verstage
by Martin Roth (Code Review) 26 Jun '20

26 Jun '20

Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Patrick Georgi, Julius Werner, Eric Peers, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41816 to look at the new patch set (#10). Change subject: soc/amd/picasso: add psp_verstage ...................................................................... soc/amd/picasso: add psp_verstage This is the main code for building coreboot's verstage as a userspace application to run on the PSP. It does a minimal setup of hardware, then runs verstage_main. It uses hardware hashing to increase the speed and will directly reboot into recovery mode if there are any failures. BUG=b:158124527 TEST=Build & boot trembyle Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/memlayout.ld A src/soc/amd/picasso/memlayout_psp_verstage.ld A src/soc/amd/picasso/memlayout_x86.ld A src/soc/amd/picasso/psp_verstage/Makefile.inc A src/soc/amd/picasso/psp_verstage/delay.c A src/soc/amd/picasso/psp_verstage/fch.c A src/soc/amd/picasso/psp_verstage/include/arch/io.h A src/soc/amd/picasso/psp_verstage/pmutil.c A src/soc/amd/picasso/psp_verstage/post.c A src/soc/amd/picasso/psp_verstage/printk.c A src/soc/amd/picasso/psp_verstage/psp.c A src/soc/amd/picasso/psp_verstage/psp_verstage.c A src/soc/amd/picasso/psp_verstage/psp_verstage.h A src/soc/amd/picasso/psp_verstage/reset.c A src/soc/amd/picasso/psp_verstage/svc.c A src/soc/amd/picasso/psp_verstage/svc.h A src/soc/amd/picasso/psp_verstage/timer.c A src/soc/amd/picasso/psp_verstage/timestamp.c A src/soc/amd/picasso/psp_verstage/vboot_crypto.c 22 files changed, 1,125 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/41816/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/41816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 Gerrit-Change-Number: 41816 Gerrit-PatchSet: 10 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: add psp_verstage
by Martin Roth (Code Review) 25 Jun '20

25 Jun '20

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41816 ) Change subject: soc/amd/picasso: add psp_verstage ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/41816/9/src/soc/amd/picasso/psp_ve… File src/soc/amd/picasso/psp_verstage/psp_verstage.c: https://review.coreboot.org/c/coreboot/+/41816/9/src/soc/amd/picasso/psp_ve… PS9, Line 210: stage_entry > Can you add that as a comment Done -- To view, visit https://review.coreboot.org/c/coreboot/+/41816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 Gerrit-Change-Number: 41816 Gerrit-PatchSet: 9 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 25 Jun 2020 23:11:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: add psp_verstage
by Martin Roth (Code Review) 25 Jun '20

25 Jun '20

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41816 ) Change subject: soc/amd/picasso: add psp_verstage ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/41816/9/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h: https://review.coreboot.org/c/coreboot/+/41816/9/src/soc/amd/picasso/chip.h… PS9, Line 15: #include <arch/x86/include/arch/smp/mpspec.h> /* point from top level */ > hate the world.... Leave it like this for now. Some bits of code are like that. :) -- To view, visit https://review.coreboot.org/c/coreboot/+/41816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 Gerrit-Change-Number: 41816 Gerrit-PatchSet: 9 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 25 Jun 2020 23:07:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: add psp_verstage
by Raul Rangel (Code Review) 25 Jun '20

25 Jun '20

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41816 ) Change subject: soc/amd/picasso: add psp_verstage ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/41816/9/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h: https://review.coreboot.org/c/coreboot/+/41816/9/src/soc/amd/picasso/chip.h… PS9, Line 15: #include <arch/x86/include/arch/smp/mpspec.h> /* point from top level */ > That doesn't work either - static.c is compiled into verstage by default. […] hate the world.... Leave it like this for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/41816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 Gerrit-Change-Number: 41816 Gerrit-PatchSet: 9 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 25 Jun 2020 23:05:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: add psp_verstage
by Martin Roth (Code Review) 25 Jun '20

25 Jun '20

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41816 ) Change subject: soc/amd/picasso: add psp_verstage ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/41816/9/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h: https://review.coreboot.org/c/coreboot/+/41816/9/src/soc/amd/picasso/chip.h… PS9, Line 15: #include <arch/x86/include/arch/smp/mpspec.h> /* point from top level */ > Then guard it with ENV_X86. It's only used by static. […] That doesn't work either - static.c is compiled into verstage by default. If I remove static.c from verstage, then device_const.c doesn't compile. Some options that should work: 1) create the arch/smp/mpspec.h in the psp_verstage/include directory with just the definitions we need? 2) update the code in chip.h to something like: #if ENV_X86 #include <arch/smp/mpspec.h> #else #define MP_IRQ_TRIGGER_LEVEL #define MP_IRQ_POLARITY_HIGH #endif Thoughts? -- To view, visit https://review.coreboot.org/c/coreboot/+/41816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 Gerrit-Change-Number: 41816 Gerrit-PatchSet: 9 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 25 Jun 2020 22:51:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2020