coreboot-gerrit June 2020

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Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP WW22 release
by Jonathan Zhang (Code Review) 28 Jun '20

28 Jun '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41903 ) Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP WW22 release ...................................................................... vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP WW22 release Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I70762b377a057d0fca7806f485cce8d479fb5baa --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 3 files changed, 52 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/41903/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index c4c23df..a5175e8 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -481,57 +481,76 @@ **/ UINT8 KtiInEnableMktme; -/** Offset 0x00CF -**/ - UINT8 UnusedUpdSpace4; - -/** Offset 0x00D0 - Address of IIoBifurcationTable. - The address of the table of IIoBifurcation. +/** Offset 0x00CF - IIO ConfigIOU0 + ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO $EN_DIS **/ - UINT32 IIoBifurcationTablePtr; + UINT8 IioConfigIOU0[8]; -/** Offset 0x00D4 - Number of IIoBifurcationTable Entry - Number of IIoBifurcationTable Entry. If this is not zero, the IIoBifurcationTablePtr - must not be NULL. +/** Offset 0x00D7 - IIO ConfigIOU1 + ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ - UINT8 NumOfIIoBifurcationTable; + UINT8 IioConfigIOU1[8]; -/** Offset 0x00D5 - PchAdrEn +/** Offset 0x00DF - IIO ConfigIOU2 + ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO +**/ + UINT8 IioConfigIOU2[8]; + +/** Offset 0x00E7 - IIO ConfigIOU3 + ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO +**/ + UINT8 IioConfigIOU3[8]; + +/** Offset 0x00EF - IIO ConfigIOU4 + ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO +**/ + UINT8 IioConfigIOU4[8]; + +/** Offset 0x00F7 - PchAdrEn Enable or Disable PchAdr **/ UINT8 PchAdrEn; -/** Offset 0x00D6 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00F8 - } TYPE:{Combo + Root port swapping based on device connection status : TRUE or FALSE + TRUE : 0x01, FALSE : 0x00 **/ UINT8 PchPcieRootPortFunctionSwap; -/** Offset 0x00D7 - PCH PCIE PLL Ssc +/** Offset 0x00F9 - PCH PCIE PLL Ssc Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF **/ UINT8 PchPciePllSsc; -/** Offset 0x00D8 - Usage type for PCH PCIE Root Port Index +/** Offset 0x00FA - Usage type for PCH PCIE Root Port Index Index assigned to every PCH PCIE Root Port **/ UINT8 PchPciePortIndex[20]; -/** Offset 0x00EC - Usage type for PCH PCIE Root Port Enable or Disable - 0-19: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use - (free running), 0xFF: not used +/** Offset 0x010E - Usage type for PCH PCIE Root Port Enable or Disable + 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, + the value is 0x00 **/ UINT8 PchPcieForceEnable[20]; -/** Offset 0x0100 - Usage type for PCH PCIE Root Port Link Speed - 0-19: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use - (free running), 0xFF: not used +/** Offset 0x0122 - Usage type for PCH PCIE Root Port Link Speed + 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie + Gen2 Speed, 0x03 : Pcie Gen3 Speed **/ UINT8 PchPciePortLinkSpeed[20]; -/** Offset 0x0114 +/** Offset 0x0136 +**/ + UINT8 UnusedUpdSpace4[2]; + +/** Offset 0x0138 **/ UINT8 ReservedMemoryInitUpd[16]; } FSP_M_CONFIG; @@ -552,11 +571,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0124 +/** Offset 0x0148 **/ - UINT8 UnusedUpdSpace5[2]; + UINT8 UnusedUpdSpace5[6]; -/** Offset 0x0126 +/** Offset 0x014E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 1ce5d30..7ac630f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -273,7 +273,6 @@ uint8_t DmiVc1; uint8_t DmiVcm; uint32_t CpuPCPSInfo; - uint8_t LtsxEnable; uint8_t MctpEn; uint8_t cpuSubType; uint8_t SystemRasType; diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 6b0823c..e9c7dbf 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -99,7 +99,12 @@ UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; - UINT8 reserved3[24409]; + UINT8 reserved3[24417]; + + UINT32 MmiohBase; // MMIOH base in 64MB granularity + + UINT8 reserved4[10]; + } SYSTEM_MEMORY_MAP_HOB; #pragma pack() -- To view, visit https://review.coreboot.org/c/coreboot/+/41903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70762b377a057d0fca7806f485cce8d479fb5baa Gerrit-Change-Number: 41903 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: libpayload/cbgfx: Fix overflow in transform_vector()
by Yu-Ping Wu (Code Review) 28 Jun '20

28 Jun '20

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42770 ) Change subject: libpayload/cbgfx: Fix overflow in transform_vector() ...................................................................... libpayload/cbgfx: Fix overflow in transform_vector() Fix potential overflow when multiplying integers in transform_vector(). In addition, check the lower bound in within_box(). BRANCH=none BUG=b:146399181, b:159772149 TEST=emerge-puff libpayload TEST=Previous screen is cleared properly for menu UI Change-Id: I57845f54e18e5bdbd0d774209ee9632cb860b0c2 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M payloads/libpayload/drivers/video/graphics.c 1 file changed, 10 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/42770/1 diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index 81d2bb9..7c1e67f 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -113,8 +113,8 @@ { if (!is_valid_scale(a)) return CBGFX_ERROR_INVALID_PARAMETER; - out->x = a->x.n * in->x / a->x.d + offset->x; - out->y = a->y.n * in->y / a->y.d + offset->y; + out->x = (int64_t)a->x.n * in->x / a->x.d + offset->x; + out->y = (int64_t)a->y.n * in->y / a->y.d + offset->y; return CBGFX_SUCCESS; } @@ -124,11 +124,15 @@ */ static int within_box(const struct vector *v, const struct rect *bound) { - if (v->x < bound->offset.x + bound->size.width && - v->y < bound->offset.y + bound->size.height) + if (v->x > bound->offset.x && + v->y > bound->offset.y && + v->x < bound->offset.x + bound->size.width && + v->y < bound->offset.y + bound->size.height) return 1; - else if (v->x <= bound->offset.x + bound->size.width && - v->y <= bound->offset.y + bound->size.height) + else if (v->x >= bound->offset.x && + v->y >= bound->offset.y && + v->x <= bound->offset.x + bound->size.width && + v->y <= bound->offset.y + bound->size.height) return 0; else return -1; -- To view, visit https://review.coreboot.org/c/coreboot/+/42770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57845f54e18e5bdbd0d774209ee9632cb860b0c2 Gerrit-Change-Number: 42770 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: [WIP] sb,soc/amd: Allow dynamic ACPIMMIO base address
by Kyösti Mälkki (Code Review) 28 Jun '20

28 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42073 ) Change subject: [WIP] sb,soc/amd: Allow dynamic ACPIMMIO base address ...................................................................... [WIP] sb,soc/amd: Allow dynamic ACPIMMIO base address Change-Id: I8d50de60bb1ea1b3a521ab535a5637c4de8c3559 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h 2 files changed, 86 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/42073/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index b3d3332..9be9bcb 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -5,28 +5,56 @@ #include <amdblocks/acpimmio_map.h> #include <amdblocks/acpimmio.h> -uint8_t *const acpimmio_sm_pci = ACPIMMIO_BASE(SM_PCI); -uint8_t *const acpimmio_gpio_100 = ACPIMMIO_BASE(GPIO_100); -uint8_t *const acpimmio_smi = ACPIMMIO_BASE(SMI); -uint8_t *const acpimmio_pmio = ACPIMMIO_BASE(PMIO); -uint8_t *const acpimmio_pmio2 = ACPIMMIO_BASE(PMIO2); -uint8_t *const acpimmio_biosram = ACPIMMIO_BASE(BIOSRAM); -uint8_t *const acpimmio_cmosram = ACPIMMIO_BASE(CMOSRAM); -uint8_t *const acpimmio_cmos = ACPIMMIO_BASE(CMOS); -uint8_t *const acpimmio_acpi = ACPIMMIO_BASE(ACPI); -uint8_t *const acpimmio_asf = ACPIMMIO_BASE(ASF); -uint8_t *const acpimmio_smbus = ACPIMMIO_BASE(SMBUS); -uint8_t *const acpimmio_wdt = ACPIMMIO_BASE(WDT); -uint8_t *const acpimmio_hpet = ACPIMMIO_BASE(HPET); -uint8_t *const acpimmio_iomux = ACPIMMIO_BASE(IOMUX); -uint8_t *const acpimmio_misc = ACPIMMIO_BASE(MISC); -uint8_t *const acpimmio_dpvga = ACPIMMIO_BASE(DPVGA); -uint8_t *const acpimmio_gpio0 = ACPIMMIO_BASE(GPIO0); -uint8_t *const acpimmio_gpio1 = ACPIMMIO_BASE(GPIO1); -uint8_t *const acpimmio_gpio2 = ACPIMMIO_BASE(GPIO2); -uint8_t *const acpimmio_xhci_pm = ACPIMMIO_BASE(XHCIPM); -uint8_t *const acpimmio_acdc_tmr = ACPIMMIO_BASE(ACDCTMR); -uint8_t *const acpimmio_aoac = ACPIMMIO_BASE(AOAC); +DECLARE_ACPIMMIO(acpimmio_sm_pci, SM_PCI); +DECLARE_ACPIMMIO(acpimmio_gpio_100, GPIO_100); +DECLARE_ACPIMMIO(acpimmio_smi, SMI); +DECLARE_ACPIMMIO(acpimmio_pmio, PMIO); +DECLARE_ACPIMMIO(acpimmio_pmio2, PMIO2); +DECLARE_ACPIMMIO(acpimmio_biosram, BIOSRAM); +DECLARE_ACPIMMIO(acpimmio_cmosram, CMOSRAM); +DECLARE_ACPIMMIO(acpimmio_cmos, CMOS); +DECLARE_ACPIMMIO(acpimmio_acpi, ACPI); +DECLARE_ACPIMMIO(acpimmio_asf, ASF); +DECLARE_ACPIMMIO(acpimmio_smbus, SMBUS); +DECLARE_ACPIMMIO(acpimmio_wdt, WDT); +DECLARE_ACPIMMIO(acpimmio_hpet, HPET); +DECLARE_ACPIMMIO(acpimmio_iomux, IOMUX); +DECLARE_ACPIMMIO(acpimmio_misc, MISC); +DECLARE_ACPIMMIO(acpimmio_dpvga, DPVGA); +DECLARE_ACPIMMIO(acpimmio_gpio0, GPIO0); +DECLARE_ACPIMMIO(acpimmio_gpio1, GPIO1); +DECLARE_ACPIMMIO(acpimmio_gpio2, GPIO2); +DECLARE_ACPIMMIO(acpimmio_xhci_pm, XHCIPM); +DECLARE_ACPIMMIO(acpimmio_acdc_tmr, ACDCTMR); +DECLARE_ACPIMMIO(acpimmio_aoac, AOAC); + +#if !CONSTANT_ACPIMMIO_BASE_ADDRESS +static void __unused update_acpimmio_base(uintptr_t base) +{ + acpimmio_sm_pci = ACPIMMIO_BASE(base, SM_PCI); + acpimmio_gpio_100 = ACPIMMIO_BASE(base, GPIO_100); + acpimmio_smi = ACPIMMIO_BASE(base, SMI); + acpimmio_pmio = ACPIMMIO_BASE(base, PMIO); + acpimmio_pmio2 = ACPIMMIO_BASE(base, PMIO2); + acpimmio_biosram = ACPIMMIO_BASE(base, BIOSRAM); + acpimmio_cmosram = ACPIMMIO_BASE(base, CMOSRAM); + acpimmio_cmos = ACPIMMIO_BASE(base, CMOS); + acpimmio_acpi = ACPIMMIO_BASE(base, ACPI); + acpimmio_asf = ACPIMMIO_BASE(base, ASF); + acpimmio_smbus = ACPIMMIO_BASE(base, SMBUS); + acpimmio_wdt = ACPIMMIO_BASE(base, WDT); + acpimmio_hpet = ACPIMMIO_BASE(base, HPET); + acpimmio_iomux = ACPIMMIO_BASE(base, IOMUX); + acpimmio_misc = ACPIMMIO_BASE(base, MISC); + acpimmio_dpvga = ACPIMMIO_BASE(base, DPVGA); + acpimmio_gpio0 = ACPIMMIO_BASE(base, GPIO0); + acpimmio_gpio1 = ACPIMMIO_BASE(base, GPIO1); + acpimmio_gpio2 = ACPIMMIO_BASE(base, GPIO2); + acpimmio_xhci_pm = ACPIMMIO_BASE(base, XHCIPM); + acpimmio_acdc_tmr = ACPIMMIO_BASE(base, ACDCTMR); + acpimmio_aoac = ACPIMMIO_BASE(base, AOAC); +} +#endif void enable_acpimmio_decode_pm24(void) { diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 3d3c359..9cd6281 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -35,8 +35,19 @@ * across family/model products. */ +#define CONSTANT_ACPIMMIO_BASE_ADDRESS 0 + #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 +#if CONSTANT_ACPIMMIO_BASE_ADDRESS +#define MAYBE_CONST const +#define DECLARE_ACPIMMIO(ptr, bank) \ + uint8_t *const ptr = (void *)(AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK) +#else +#define MAYBE_CONST +#define DECLARE_ACPIMMIO(ptr, bank) uint8_t *ptr +#endif + #ifdef __ACPI__ /* Damn, ASL fails on additions. */ @@ -68,35 +79,36 @@ #define ACPIMMIO_ACDCTMR_BANK 0x1d00 #define ACPIMMIO_AOAC_BANK 0x1e00 -#define ACPIMMIO_BASE(x) \ - (void *)(AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## x ## _BANK) +#define ACPIMMIO_BASE(base, x) (void *)(base + ACPIMMIO_ ## x ## _BANK) /* FIXME: Passing host base for SMBUS is not long-term solution. */ #define ACPIMMIO_ASF_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ASF_BANK) #define ACPIMMIO_SMBUS_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_SMBUS_BANK) -extern uint8_t *const acpimmio_gpio_100; -extern uint8_t *const acpimmio_sm_pci; -extern uint8_t *const acpimmio_smi; -extern uint8_t *const acpimmio_pmio; -extern uint8_t *const acpimmio_pmio2; -extern uint8_t *const acpimmio_biosram; -extern uint8_t *const acpimmio_cmosram; -extern uint8_t *const acpimmio_cmos; -extern uint8_t *const acpimmio_acpi; -extern uint8_t *const acpimmio_asf; -extern uint8_t *const acpimmio_smbus; -extern uint8_t *const acpimmio_wdt; -extern uint8_t *const acpimmio_hpet; -extern uint8_t *const acpimmio_iomux; -extern uint8_t *const acpimmio_misc; -extern uint8_t *const acpimmio_dpvga; -extern uint8_t *const acpimmio_gpio0; -extern uint8_t *const acpimmio_gpio1; -extern uint8_t *const acpimmio_gpio2; -extern uint8_t *const acpimmio_xhci_pm; -extern uint8_t *const acpimmio_acdc_tmr; -extern uint8_t *const acpimmio_aoac; +extern uint8_t *MAYBE_CONST acpimmio_gpio_100; +extern uint8_t *MAYBE_CONST acpimmio_sm_pci; +extern uint8_t *MAYBE_CONST acpimmio_smi; +extern uint8_t *MAYBE_CONST acpimmio_pmio; +extern uint8_t *MAYBE_CONST acpimmio_pmio2; +extern uint8_t *MAYBE_CONST acpimmio_biosram; +extern uint8_t *MAYBE_CONST acpimmio_cmosram; +extern uint8_t *MAYBE_CONST acpimmio_cmos; +extern uint8_t *MAYBE_CONST acpimmio_acpi; +extern uint8_t *MAYBE_CONST acpimmio_asf; +extern uint8_t *MAYBE_CONST acpimmio_smbus; +extern uint8_t *MAYBE_CONST acpimmio_wdt; +extern uint8_t *MAYBE_CONST acpimmio_hpet; +extern uint8_t *MAYBE_CONST acpimmio_iomux; +extern uint8_t *MAYBE_CONST acpimmio_misc; +extern uint8_t *MAYBE_CONST acpimmio_dpvga; +extern uint8_t *MAYBE_CONST acpimmio_gpio0; +extern uint8_t *MAYBE_CONST acpimmio_gpio1; +extern uint8_t *MAYBE_CONST acpimmio_gpio2; +extern uint8_t *MAYBE_CONST acpimmio_xhci_pm; +extern uint8_t *MAYBE_CONST acpimmio_acdc_tmr; +extern uint8_t *MAYBE_CONST acpimmio_aoac; + +#undef MAYBE_CONST #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d50de60bb1ea1b3a521ab535a5637c4de8c3559 Gerrit-Change-Number: 42073 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

6 21

Change in coreboot[master]: [WIP] soc/amd/common: Access ACPI MMIO via proper symbols
by Kyösti Mälkki (Code Review) 28 Jun '20

28 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37324 ) Change subject: [WIP] soc/amd/common: Access ACPI MMIO via proper symbols ...................................................................... [WIP] soc/amd/common: Access ACPI MMIO via proper symbols Using proper symbols for base addresses, it is possible to only define the symbols for base addesses implemented in the platform. TBD: Check for bad aliasing effects when immediate value changes to memory reference. Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h 3 files changed, 125 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/37324/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 04d5e4a..51e661d 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -18,6 +18,28 @@ #include <amdblocks/acpimmio_map.h> #include <amdblocks/acpimmio.h> +uint8_t *const acpimmio_sm_pci = (void *)ACPIMMIO_SM_PCI_BASE; +uint8_t *const acpimmio_smi = (void *)ACPIMMIO_SMI_BASE; +uint8_t *const acpimmio_pmio = (void *)ACPIMMIO_PMIO_BASE; +uint8_t *const acpimmio_pmio2 = (void *)ACPIMMIO_PMIO2_BASE; +uint8_t *const acpimmio_biosram = (void *)ACPIMMIO_BIOSRAM_BASE; +uint8_t *const acpimmio_cmosram = (void *)ACPIMMIO_CMOSRAM_BASE; +uint8_t *const acpimmio_cmos = (void *)ACPIMMIO_CMOS_BASE; +uint8_t *const acpimmio_acpi = (void *)ACPIMMIO_ACPI_BASE; +uint8_t *const acpimmio_asf = (void *)ACPIMMIO_ASF_BASE; +uint8_t *const acpimmio_smbus = (void *)ACPIMMIO_SMBUS_BASE; +uint8_t *const acpimmio_wdt = (void *)ACPIMMIO_WDT_BASE; +uint8_t *const acpimmio_hpet = (void *)ACPIMMIO_HPET_BASE; +uint8_t *const acpimmio_iomux = (void *)ACPIMMIO_IOMUX_BASE; +uint8_t *const acpimmio_misc = (void *)ACPIMMIO_MISC_BASE; +uint8_t *const acpimmio_dpvga = (void *)ACPIMMIO_DPVGA_BASE; +uint8_t *const acpimmio_gpio0 = (void *)ACPIMMIO_GPIO0_BASE; +uint8_t *const acpimmio_gpio1 = (void *)ACPIMMIO_GPIO1_BASE; +uint8_t *const acpimmio_gpio2 = (void *)ACPIMMIO_GPIO2_BASE; +uint8_t *const acpimmio_xhci_pm = (void *)ACPIMMIO_XHCIPM_BASE; +uint8_t *const acpimmio_acdc_tmr = (void *)ACPIMMIO_ACDCTMR_BASE; +uint8_t *const acpimmio_aoac = (void *)ACPIMMIO_AOAC_BASE; + void enable_acpimmio_decode(void) { uint32_t dw; diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 57d24db..9df47d1 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -121,272 +121,272 @@ static inline uint8_t sm_pci_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg)); + return read8(acpimmio_sm_pci + reg); } static inline uint16_t sm_pci_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_SM_PCI_BASE + reg)); + return read16(acpimmio_sm_pci + reg); } static inline uint32_t sm_pci_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_SM_PCI_BASE + reg)); + return read32(acpimmio_sm_pci + reg); } static inline void sm_pci_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); + write8(acpimmio_sm_pci + reg, value); } static inline void sm_pci_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); + write16(acpimmio_sm_pci + reg, value); } static inline void sm_pci_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); + write32(acpimmio_sm_pci + reg, value); } static inline uint8_t smi_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_SMI_BASE + reg)); + return read8(acpimmio_smi + reg); } static inline uint16_t smi_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_SMI_BASE + reg)); + return read16(acpimmio_smi + reg); } static inline uint32_t smi_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_SMI_BASE + reg)); + return read32(acpimmio_smi + reg); } static inline void smi_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_SMI_BASE + reg), value); + write8(acpimmio_smi + reg, value); } static inline void smi_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_SMI_BASE + reg), value); + write16(acpimmio_smi + reg, value); } static inline void smi_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_SMI_BASE + reg), value); + write32(acpimmio_smi + reg, value); } static inline uint8_t pm_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); + return read8(acpimmio_pmio + reg); } static inline uint16_t pm_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); + return read16(acpimmio_pmio + reg); } static inline uint32_t pm_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); + return read32(acpimmio_pmio + reg); } static inline void pm_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); + write8(acpimmio_pmio + reg, value); } static inline void pm_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); + write16(acpimmio_pmio + reg, value); } static inline void pm_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); + write32(acpimmio_pmio + reg, value); } static inline uint8_t biosram_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); + return read8(acpimmio_biosram + reg); } static inline void biosram_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); + write8(acpimmio_biosram + reg, value); } static inline uint8_t acpi_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); + return read8(acpimmio_acpi + reg); } static inline uint16_t acpi_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); + return read16(acpimmio_acpi + reg); } static inline uint32_t acpi_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); + return read32(acpimmio_acpi + reg); } static inline void acpi_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); + write8(acpimmio_acpi + reg, value); } static inline void acpi_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); + write16(acpimmio_acpi + reg, value); } static inline void acpi_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); + write32(acpimmio_acpi + reg, value); } static inline uint8_t asf_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_ASF_BASE + reg)); + return read8(acpimmio_asf + reg); } static inline uint16_t asf_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_ASF_BASE + reg)); + return read16(acpimmio_asf + reg); } static inline void asf_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_ASF_BASE + reg), value); + write8(acpimmio_asf + reg, value); } static inline void asf_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_ASF_BASE + reg), value); + write16(acpimmio_asf + reg, value); } static inline uint8_t smbus_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); + return read8(acpimmio_smbus + reg); } static inline uint16_t smbus_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); + return read16(acpimmio_smbus + reg); } static inline void smbus_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); + write8(acpimmio_smbus + reg, value); } static inline void smbus_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); + write16(acpimmio_smbus + reg, value); } static inline uint8_t iomux_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); + return read8(acpimmio_iomux + reg); } static inline uint16_t iomux_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); + return read16(acpimmio_iomux + reg); } static inline uint32_t iomux_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); + return read32(acpimmio_iomux + reg); } static inline void iomux_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); + write8(acpimmio_iomux + reg, value); } static inline void iomux_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); + write16(acpimmio_iomux + reg, value); } static inline void iomux_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); + write32(acpimmio_iomux + reg, value); } static inline uint8_t misc_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_MISC_BASE + reg)); + return read8(acpimmio_misc + reg); } static inline uint16_t misc_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_MISC_BASE + reg)); + return read16(acpimmio_misc + reg); } static inline uint32_t misc_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_MISC_BASE + reg)); + return read32(acpimmio_misc + reg); } static inline void misc_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_MISC_BASE + reg), value); + write8(acpimmio_misc + reg, value); } static inline void misc_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_MISC_BASE + reg), value); + write16(acpimmio_misc + reg, value); } static inline void misc_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_MISC_BASE + reg), value); + write32(acpimmio_misc + reg, value); } static inline uint8_t xhci_pm_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); + return read8(acpimmio_xhci_pm + reg); } static inline uint16_t xhci_pm_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); + return read16(acpimmio_xhci_pm + reg); } static inline uint32_t xhci_pm_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); + return read32(acpimmio_xhci_pm + reg); } static inline void xhci_pm_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); + write8(acpimmio_xhci_pm + reg, value); } static inline void xhci_pm_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); + write16(acpimmio_xhci_pm + reg, value); } static inline void xhci_pm_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); + write32(acpimmio_xhci_pm + reg, value); } static inline uint8_t aoac_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); + return read8(acpimmio_aoac + reg); } static inline void aoac_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); + write8(acpimmio_aoac + reg, value); } #endif /* __AMDBLOCKS_ACPIMMIO_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 755af52..4f64ee6 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -42,26 +42,56 @@ */ #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 -#define ACPIMMIO_SM_PCI_BASE 0xfed80000 -#define ACPIMMIO_SMI_BASE 0xfed80200 -#define ACPIMMIO_PMIO_BASE 0xfed80300 -#define ACPIMMIO_PMIO2_BASE 0xfed80400 -#define ACPIMMIO_BIOSRAM_BASE 0xfed80500 -#define ACPIMMIO_CMOSRAM_BASE 0xfed80600 -#define ACPIMMIO_CMOS_BASE 0xfed80700 -#define ACPIMMIO_ACPI_BASE 0xfed80800 -#define ACPIMMIO_ASF_BASE 0xfed80900 -#define ACPIMMIO_SMBUS_BASE 0xfed80a00 -#define ACPIMMIO_WDT_BASE 0xfed80b00 -#define ACPIMMIO_HPET_BASE 0xfed80c00 -#define ACPIMMIO_IOMUX_BASE 0xfed80d00 + +#ifndef __ACPI__ +#define ACPIMMIO_SM_PCI_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0000) +#define ACPIMMIO_SMI_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0200) +#define ACPIMMIO_PMIO_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0300) +#define ACPIMMIO_PMIO2_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0400) +#define ACPIMMIO_BIOSRAM_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0500) +#define ACPIMMIO_CMOSRAM_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0600) +#define ACPIMMIO_CMOS_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0700) +#define ACPIMMIO_ACPI_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0800) +#define ACPIMMIO_ASF_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0900) +#define ACPIMMIO_SMBUS_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0a00) +#define ACPIMMIO_WDT_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0b00) +#define ACPIMMIO_HPET_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0c00) +#define ACPIMMIO_IOMUX_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0d00) +#define ACPIMMIO_MISC_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0e00) +#define ACPIMMIO_DPVGA_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x1400) +#define ACPIMMIO_GPIO0_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x1500) +#define ACPIMMIO_GPIO1_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x1600) +#define ACPIMMIO_GPIO2_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x1700) +#define ACPIMMIO_XHCIPM_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x1c00) +#define ACPIMMIO_ACDCTMR_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x1d00) +#define ACPIMMIO_AOAC_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x1e00) + +extern uint8_t *const acpimmio_sm_pci; +extern uint8_t *const acpimmio_smi; +extern uint8_t *const acpimmio_pmio; +extern uint8_t *const acpimmio_pmio2; +extern uint8_t *const acpimmio_biosram; +extern uint8_t *const acpimmio_cmosram; +extern uint8_t *const acpimmio_cmos; +extern uint8_t *const acpimmio_acpi; +extern uint8_t *const acpimmio_asf; +extern uint8_t *const acpimmio_smbus; +extern uint8_t *const acpimmio_wdt; +extern uint8_t *const acpimmio_hpet; +extern uint8_t *const acpimmio_iomux; +extern uint8_t *const acpimmio_misc; +extern uint8_t *const acpimmio_dpvga; +extern uint8_t *const acpimmio_gpio0; +extern uint8_t *const acpimmio_gpio1; +extern uint8_t *const acpimmio_gpio2; +extern uint8_t *const acpimmio_xhci_pm; +extern uint8_t *const acpimmio_acdc_tmr; +extern uint8_t *const acpimmio_aoac; +#else + +/* Damn, ASL fails on additions. */ #define ACPIMMIO_MISC_BASE 0xfed80e00 -#define ACPIMMIO_DPVGA_BASE 0xfed81400 #define ACPIMMIO_GPIO0_BASE 0xfed81500 -#define ACPIMMIO_GPIO1_BASE 0xfed81600 -#define ACPIMMIO_GPIO2_BASE 0xfed81700 -#define ACPIMMIO_XHCIPM_BASE 0xfed81c00 -#define ACPIMMIO_ACDCTMR_BASE 0xfed81d00 -#define ACPIMMIO_AOAC_BASE 0xfed81e00 +#endif #endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09 Gerrit-Change-Number: 37324 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

8 37

Change in coreboot[master]: AGESA fam14: Use AMD_ACPIMMIO_GPIO_BASE_100
by Patrick Georgi (Code Review) 28 Jun '20

28 Jun '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42708 ) Change subject: AGESA fam14: Use AMD_ACPIMMIO_GPIO_BASE_100 ...................................................................... AGESA fam14: Use AMD_ACPIMMIO_GPIO_BASE_100 Use the pre-defined constant address directly. Change-Id: I29fbc82fffc69b864adb4ddbda1425db98e2e48a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42708 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/amd/inagua/BiosCallOuts.c M src/mainboard/amd/persimmon/BiosCallOuts.c M src/mainboard/amd/south_station/BiosCallOuts.c M src/mainboard/amd/union_station/BiosCallOuts.c M src/mainboard/asrock/e350m1/BiosCallOuts.c M src/mainboard/elmex/pcm205400/BiosCallOuts.c M src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c 7 files changed, 12 insertions(+), 48 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 07b9ebd..16058b6 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -30,7 +30,6 @@ AGESA_STATUS Status; UINTN FcnData; MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; UINT32 GpioMmioAddr; UINT8 Data8; UINT8 TempData8; @@ -39,8 +38,7 @@ MemData = ConfigPtr; Status = AGESA_SUCCESS; - AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + GpioMmioAddr = ACPIMMIO_GPIO_BASE_100; Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); Data8 &= ~BIT5; @@ -107,13 +105,11 @@ PCIe_SLOT_RESET_INFO *ResetInfo; UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; UINT8 Data8; FcnData = Data; ResetInfo = ConfigPtr; - AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + GpioMmioAddr = ACPIMMIO_GPIO_BASE_100; Status = AGESA_UNSUPPORTED; switch (ResetInfo->ResetId) { case 4: diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 4a6653e..1734bc9 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -40,20 +40,12 @@ PCIe_SLOT_RESET_INFO *ResetInfo; UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; UINT8 Data8; - UINT16 Data16; FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) - Data8 = pm_io_read8(0x27); - Data16 = Data8 << 8; - Data8 = pm_io_read8(0x26); - Data16 |= Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; Status = AGESA_UNSUPPORTED; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + GpioMmioAddr = ACPIMMIO_GPIO_BASE_100; switch (ResetInfo->ResetId) { case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 3e619be..a4438f5 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -30,7 +30,6 @@ AGESA_STATUS Status; UINTN FcnData; MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; UINT32 GpioMmioAddr; UINT8 Data8; UINT8 TempData8; @@ -39,8 +38,7 @@ MemData = ConfigPtr; Status = AGESA_SUCCESS; - AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + GpioMmioAddr = ACPIMMIO_GPIO_BASE_100; Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); Data8 &= ~BIT5; @@ -106,13 +104,12 @@ UINTN FcnData; PCIe_SLOT_RESET_INFO *ResetInfo; UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; UINT8 Data8; + GpioMmioAddr = ACPIMMIO_GPIO_BASE_100; + FcnData = Data; ResetInfo = ConfigPtr; - AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; Status = AGESA_UNSUPPORTED; switch (ResetInfo->ResetId) { case 4: diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index a5634ec..deb6176 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -30,7 +30,6 @@ AGESA_STATUS Status; UINTN FcnData; MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; UINT32 GpioMmioAddr; UINT8 Data8; UINT8 TempData8; @@ -39,8 +38,7 @@ MemData = ConfigPtr; Status = AGESA_SUCCESS; - AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + GpioMmioAddr = ACPIMMIO_GPIO_BASE_100; Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); Data8 &= ~BIT5; @@ -106,13 +104,12 @@ UINTN FcnData; PCIe_SLOT_RESET_INFO *ResetInfo; UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; UINT8 Data8; + GpioMmioAddr = ACPIMMIO_GPIO_BASE_100; + FcnData = Data; ResetInfo = ConfigPtr; - AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; Status = AGESA_UNSUPPORTED; switch (ResetInfo->ResetId) { case 4: diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index b4f6d64..a3d5337 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -28,7 +28,6 @@ AGESA_STATUS Status; UINTN FcnData; MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; UINT32 GpioMmioAddr; UINT8 Data8; UINT8 TempData8; @@ -37,8 +36,7 @@ MemData = ConfigPtr; Status = AGESA_SUCCESS; - AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + GpioMmioAddr = ACPIMMIO_GPIO_BASE_100; Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); Data8 &= ~BIT5; diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c index 2242c0e..1734bc9 100644 --- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c +++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c @@ -40,20 +40,12 @@ PCIe_SLOT_RESET_INFO *ResetInfo; UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; UINT8 Data8; - UINT16 Data16; FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) - Data8 = pm_io_read8(0x27); - Data16=Data8<<8; - Data8 = pm_io_read8(0x26); - Data16|=Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; Status = AGESA_UNSUPPORTED; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + GpioMmioAddr = ACPIMMIO_GPIO_BASE_100; switch (ResetInfo->ResetId) { case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 6e0f1ad..2129509 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -43,20 +43,12 @@ PCIe_SLOT_RESET_INFO *ResetInfo; uint32_t GpioMmioAddr; - uint32_t AcpiMmioAddr; uint8_t Data8; - uint16_t Data16; FcnData = Data; ResetInfo = ConfigPtr; - /* Get SB800 MMIO Base (AcpiMmioAddr) */ - Data8 = pm_io_read8(0x27); - Data16 = Data8 << 8; - Data8 = pm_io_read8(0x26); - Data16 |= Data8; - AcpiMmioAddr = (uint32_t)Data16 << 16; Status = AGESA_UNSUPPORTED; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + GpioMmioAddr = ACPIMMIO_GPIO_BASE_100; switch (ResetInfo->ResetId) { case 46: /* GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29fbc82fffc69b864adb4ddbda1425db98e2e48a Gerrit-Change-Number: 42708 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/zork: update DRAM SPD table for berknip
by Kevin Chiu (Code Review) 28 Jun '20

28 Jun '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42814 ) Change subject: mb/google/zork: update DRAM SPD table for berknip ...................................................................... mb/google/zork: update DRAM SPD table for berknip samsung-K4A8G165WC-BCWE_x1 # 0b0101 micron-MT40A1G16KD-062E-E_x2 # 0b0110 hynix-H5ANAG6NCMR-XNC_x2 # 0b0111 samsung-K4AAG165WA-BCWE_x2 # 0b1000 BUG=b:159418772 BRANCH=master TEST=emerge-zork coreboot Change-Id: I24b632c75d4a0660dc6beb88f135b546860d7079 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/berknip/spd/Makefile.inc 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/42814/1 diff --git a/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc index 7731c07..f53e662 100644 --- a/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc @@ -14,10 +14,10 @@ APCB_SOURCES += micron-MT40A512M16TB-062E-J_x2 # 0b0010 APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0011 APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x2 # 0b0100 -APCB_SOURCES += empty # 0b0101 -APCB_SOURCES += empty # 0b0110 -APCB_SOURCES += empty # 0b0111 -APCB_SOURCES += empty # 0b1000 +APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0101 +APCB_SOURCES += micron-MT40A1G16KD-062E-E_x2 # 0b0110 +APCB_SOURCES += hynix-H5ANAG6NCMR-XNC_x2 # 0b0111 +APCB_SOURCES += samsung-K4AAG165WA-BCWE_x2 # 0b1000 APCB_SOURCES += empty # 0b1001 APCB_SOURCES += empty # 0b1010 APCB_SOURCES += empty # 0b1011 -- To view, visit https://review.coreboot.org/c/coreboot/+/42814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24b632c75d4a0660dc6beb88f135b546860d7079 Gerrit-Change-Number: 42814 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: drivers/vpd: Add a config option that would override coreboot version...
by Johnny Lin (Code Review) 28 Jun '20

28 Jun '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42029 ) Change subject: drivers/vpd: Add a config option that would override coreboot version with VPD variable ...................................................................... drivers/vpd: Add a config option that would override coreboot version with VPD variable If VPD_COREBOOT_VERSION is selected, it would read VPD_RO variable to override SMBIOS type 0 version, if the VPD variable is not found it would fallback to use VERSION_VPD_DEFAULT_IF_MISSING, if it's still not set it would use COREBOOT_VERSION. VPD_COREBOOT_VERSION default is n. Tested on OCP Delta Lake, dmidecode -t 0 can see version being updated from VPD. Change-Id: Iee62ed900095001ffac225fc629b3f2f52045e30 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/drivers/vpd/Kconfig M src/drivers/vpd/Makefile.inc A src/drivers/vpd/smbios.c 3 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/42029/1 diff --git a/src/drivers/vpd/Kconfig b/src/drivers/vpd/Kconfig index eda9130..566bec5 100644 --- a/src/drivers/vpd/Kconfig +++ b/src/drivers/vpd/Kconfig @@ -5,3 +5,27 @@ default n help Enable support for flash based vital product data. + +config VPD_COREBOOT_VERSION + bool "Read CONFIG_VERSION_VPD from VPD_RO for SMBIOS type 0 version" + default n + depends on VPD + help + After selecting this option, it would read CONFIG_VERSION_VPD from + VPD_RO and override SMBIOS type 0 version. + +config VERSION_VPD + string + default "version" + depends on VPD_COREBOOT_VERSION + help + The VPD variable name resides in VPD_RO for coreboot version, default + is "version". The value of the variable is limited to 20 characters for now. + +config VERSION_VPD_DEFAULT_IF_MISSING + string + default "" + depends on VPD_COREBOOT_VERSION + help + The fallback version value if VERSION_VPD cannot be read from VPD_RO, + if it's not set COREBOOT_VERSION would be used. diff --git a/src/drivers/vpd/Makefile.inc b/src/drivers/vpd/Makefile.inc index cc276e4..2237340 100644 --- a/src/drivers/vpd/Makefile.inc +++ b/src/drivers/vpd/Makefile.inc @@ -1,2 +1,3 @@ romstage-$(CONFIG_VPD) += vpd_decode.c vpd_premem.c vpd.c ramstage-$(CONFIG_VPD) += vpd_decode.c vpd_cbmem.c vpd.c +ramstage-$(CONFIG_VPD_COREBOOT_VERSION) += smbios.c diff --git a/src/drivers/vpd/smbios.c b/src/drivers/vpd/smbios.c new file mode 100644 index 0000000..682a4ce --- /dev/null +++ b/src/drivers/vpd/smbios.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#include <console/console.h> +#include <string.h> +#include <smbios.h> +#include <version.h> + +#include "vpd.h" + +#define VER_LEN 20 +static char version[VER_LEN] = {0}; + +const char *smbios_mainboard_bios_version(void) +{ + if (vpd_gets(CONFIG_VERSION_VPD, version, VER_LEN, VPD_RO)) { + printk(BIOS_DEBUG, "Get version from VPD: %s\n", version); + return version; + } + printk(BIOS_ERR, "Get version from VPD failed\n"); + if (strlen(CONFIG_VERSION_VPD_DEFAULT_IF_MISSING)) + return CONFIG_VERSION_VPD_DEFAULT_IF_MISSING; + else + return coreboot_version; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee62ed900095001ffac225fc629b3f2f52045e30 Gerrit-Change-Number: 42029 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

6 52

Change in coreboot[master]: mb/google/zork: update telemetry settings for berknip
by Kevin Chiu (Code Review) 28 Jun '20

28 Jun '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42817 ) Change subject: mb/google/zork: update telemetry settings for berknip ...................................................................... mb/google/zork: update telemetry settings for berknip update telemetry to improve the performance. BUG=b:154879805 BRANCH=master TEST=emerge-zork coreboot verify by Stardust test Change-Id: Iae5486cf2ee26b3d8e6124edfff4fe2d1fbe211e Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/berknip/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/42817/1 diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 18d6151..f939ed4 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -15,9 +15,9 @@ register "stapm_time_constant" = "200" #second register "sustained_power_limit" = "25000" #mw - register "telemetry_vddcr_vdd_slope" = "78289" #mA + register "telemetry_vddcr_vdd_slope" = "62451" #mA register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "24519" #mA + register "telemetry_vddcr_soc_slope" = "27301" #mA register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/42817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae5486cf2ee26b3d8e6124edfff4fe2d1fbe211e Gerrit-Change-Number: 42817 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: add G2 TS support for berknip
by Kevin Chiu (Code Review) 28 Jun '20

28 Jun '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42813 ) Change subject: mb/google/zork: add G2 TS support for berknip ...................................................................... mb/google/zork: add G2 TS support for berknip Add G2 GTCH7503 HID TS support BUG=b:159510906 BRANCH=master TEST=emerge-zork coreboot boot with G2 TS, make sure G2 TS is functional Change-Id: Id9ed5fc768459edc4660ddd6fbffb0b1973ce6d1 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/berknip/overridetree.cb 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/42813/1 diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 18d6151..251f5d5 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -87,6 +87,17 @@ register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end device mmio 0xfedca000 on -- To view, visit https://review.coreboot.org/c/coreboot/+/42813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9ed5fc768459edc4660ddd6fbffb0b1973ce6d1 Gerrit-Change-Number: 42813 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/zork: update telemetry settings for morphius
by Kevin Chiu (Code Review) 28 Jun '20

28 Jun '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42815 ) Change subject: mb/google/zork: update telemetry settings for morphius ...................................................................... mb/google/zork: update telemetry settings for morphius update telemetry to improve the performance. BUG=b:154863613 BRANCH=master TEST=emerge-zork coreboot Change-Id: Ia08259e81f360259f23ea0f9c5c128c9d0961322 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/morphius/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/42815/1 diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index 12d032a..3faab0d 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -15,9 +15,9 @@ register "stapm_time_constant" = "200" #second register "sustained_power_limit" = "12000" #mw - register "telemetry_vddcr_vdd_slope" = "78289" #mA + register "telemetry_vddcr_vdd_slope" = "78709" #mA register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "24519" #mA + register "telemetry_vddcr_soc_slope" = "29035" #mA register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/42815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia08259e81f360259f23ea0f9c5c128c9d0961322 Gerrit-Change-Number: 42815 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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