coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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2826 discussions

Change in coreboot[master]: mb/purism/librem_whl: Add new board Librem Mini (WHL-U)
by Matt DeVillier (Code Review) 29 Jun '20

29 Jun '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40278 ) Change subject: mb/purism/librem_whl: Add new board Librem Mini (WHL-U) ...................................................................... Patch Set 3: (3 comments) https://review.coreboot.org/c/coreboot/+/40278/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40278/2//COMMIT_MSG@10 PS2, Line 10: > Could you please give more details to the board (URL maybe), and document, how it was tested? documentation added in CB:42882 https://review.coreboot.org/c/coreboot/+/40278/1/src/mainboard/purism/libre… File src/mainboard/purism/librem_whl/romstage.c: https://review.coreboot.org/c/coreboot/+/40278/1/src/mainboard/purism/libre… PS1, Line 28: .dqs_map[DDR_CH0] = {0, 1, 3, 2, 4, 5, 6, 7}, > That shouldn't be needed for regular DDR4 Done https://review.coreboot.org/c/coreboot/+/40278/1/src/mainboard/purism/libre… PS1, Line 40: values for Cannon Lake : { 80, 40, 40, 40, 30 } > I think we can drop this. Maybe replace with the names of the values? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/40278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6 Gerrit-Change-Number: 40278 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 29 Jun 2020 19:58:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/purism/librem_whl: Add new board Librem Mini (WHL-U)
by Matt DeVillier (Code Review) 29 Jun '20

29 Jun '20

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT
by Tim Wawrzynczak (Code Review) 29 Jun '20

29 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41758 ) Change subject: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT ...................................................................... Patch Set 17: (1 comment) https://review.coreboot.org/c/coreboot/+/41758/16/src/soc/intel/jasperlake/… File src/soc/intel/jasperlake/chip.c: https://review.coreboot.org/c/coreboot/+/41758/16/src/soc/intel/jasperlake/… PS16, Line 96: case SA_DEVFN_IPU: return "IPU0"; > You bet, I will add that to TGL & JSL. see CB:42878 -- To view, visit https://review.coreboot.org/c/coreboot/+/41758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Gerrit-Change-Number: 41758 Gerrit-PatchSet: 17 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 29 Jun 2020 18:45:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT
by Tim Wawrzynczak (Code Review) 29 Jun '20

29 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41758 ) Change subject: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT ...................................................................... Patch Set 16: (1 comment) https://review.coreboot.org/c/coreboot/+/41758/16/src/soc/intel/jasperlake/… File src/soc/intel/jasperlake/chip.c: https://review.coreboot.org/c/coreboot/+/41758/16/src/soc/intel/jasperlake/… PS16, Line 96: case SA_DEVFN_IPU: return "IPU0"; > @Tim, can this be moved to your patch and also add required entries for other SOCs. […] You bet, I will add that to TGL & JSL. -- To view, visit https://review.coreboot.org/c/coreboot/+/41758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Gerrit-Change-Number: 41758 Gerrit-PatchSet: 16 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 29 Jun 2020 18:08:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: comment

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Change in em100[master]: Remove dead assignment
by HAOUAS Elyes (Code Review) 29 Jun '20

29 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/42843 ) Change subject: Remove dead assignment ...................................................................... Remove dead assignment Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Change-Id: I44ca81ecee8ee9639b37a03e5a5b513cd07f4d10 --- M firmware.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/43/42843/1 diff --git a/firmware.c b/firmware.c index f86362c..4dc58c0 100644 --- a/firmware.c +++ b/firmware.c @@ -246,7 +246,7 @@ unsigned char page[256], vpage[256]; long fsize; unsigned char *fw; - int i, automatic = 0; + int i; int fpga_offset, fpga_len, mcu_offset, mcu_len; char fpga_version[MAX_VERSION_LENGTH + 1], mcu_version[MAX_VERSION_LENGTH + 1]; -- To view, visit https://review.coreboot.org/c/em100/+/42843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I44ca81ecee8ee9639b37a03e5a5b513cd07f4d10 Gerrit-Change-Number: 42843 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: Use gpio_setbits32()
by Furquan Shaikh (Code Review) 29 Jun '20

29 Jun '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42688 ) Change subject: soc/amd/common: Use gpio_setbits32() ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/42688/6/src/soc/amd/common/block/g… File src/soc/amd/common/block/gpio_banks/gpio.c: https://review.coreboot.org/c/coreboot/+/42688/6/src/soc/amd/common/block/g… PS6, Line 221: __gpio_setbits32 > Ack Series pushed here: https://review.coreboot.org/c/coreboot/+/42875 -- To view, visit https://review.coreboot.org/c/coreboot/+/42688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4413d113dff550900348a44f71b949b7547a9cfc Gerrit-Change-Number: 42688 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 29 Jun 2020 17:34:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Use gpio_setbits32()
by Raul Rangel (Code Review) 29 Jun '20

29 Jun '20

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42688 ) Change subject: soc/amd/common: Use gpio_setbits32() ...................................................................... Patch Set 6: (1 comment) Think we can merge this as is. https://review.coreboot.org/c/coreboot/+/42688/6/src/soc/amd/common/block/g… File src/soc/amd/common/block/gpio_banks/gpio.c: https://review.coreboot.org/c/coreboot/+/42688/6/src/soc/amd/common/block/g… PS6, Line 221: __gpio_setbits32 > Whatever works for you. That mem_read_write32() was just too obscure to my eyes. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/42688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4413d113dff550900348a44f71b949b7547a9cfc Gerrit-Change-Number: 42688 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 29 Jun 2020 17:23:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/mandolin: make mandolin a variant of itself
by Felix Held (Code Review) 29 Jun '20

29 Jun '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42785 ) Change subject: mb/amd/mandolin: make mandolin a variant of itself ...................................................................... mb/amd/mandolin: make mandolin a variant of itself A follow-up patch will add Cereme which is a Mandolin variant. TEST=Mandolin still boots into Linux live system. Change-Id: Ifee91306756f8a4152a6a0224e172dae7eac8f7a Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Makefile.inc R src/mainboard/amd/mandolin/variants/mandolin/board.fmd R src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb R src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c 5 files changed, 15 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/42785/1 diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 49a8ece..8c37ef5 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -7,13 +7,13 @@ select SOC_AMD_COMMON_BLOCK_USE_ESPI select SOC_AMD_PICASSO select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_8192 + select BOARD_ROMSIZE_KB_8192 if BOARD_AMD_MANDOLIN select AZALIA_PLUGIN_SUPPORT select HAVE_ACPI_RESUME config FMDFILE string - default "src/mainboard/amd/mandolin/mandolin.fmd" + default "src/mainboard/amd/mandolin/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" config AMD_LPC_DEBUG_CARD bool "Enable LPC-Serial debug card on the debug header" @@ -28,15 +28,23 @@ config CBFS_SIZE hex - default 0x7cf000 # Maximum size for the Mandolin FMAP + default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP config MAINBOARD_DIR string default amd/mandolin +config VARIANT_DIR + string + default "mandolin" if BOARD_AMD_MANDOLIN + config MAINBOARD_PART_NUMBER string - default "MANDOLIN" + default "MANDOLIN" if BOARD_AMD_MANDOLIN + +config DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" config MAX_CPUS int @@ -48,7 +56,7 @@ config AMD_FWM_POSITION_INDEX int - default 3 + default 3 if BOARD_AMD_MANDOLIN help TODO: might need to be adapted for better placement of files in cbfs @@ -96,6 +104,6 @@ config VGA_BIOS_DGPU_FILE string - default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" + default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" if BOARD_AMD_MANDOLIN endif # BOARD_AMD_MANDOLIN diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index 56dd5e2..7bc176a 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -4,7 +4,7 @@ bootblock-y += early_gpio.c ramstage-y += gpio.c -ramstage-y += port_descriptors.c +ramstage-y += variants/$(VARIANT_DIR)/port_descriptors.c # APCB_mandolin.bin APCB_SOURCES = mandolin diff --git a/src/mainboard/amd/mandolin/mandolin.fmd b/src/mainboard/amd/mandolin/variants/mandolin/board.fmd similarity index 100% rename from src/mainboard/amd/mandolin/mandolin.fmd rename to src/mainboard/amd/mandolin/variants/mandolin/board.fmd diff --git a/src/mainboard/amd/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb similarity index 100% rename from src/mainboard/amd/mandolin/devicetree.cb rename to src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb diff --git a/src/mainboard/amd/mandolin/port_descriptors.c b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c similarity index 100% rename from src/mainboard/amd/mandolin/port_descriptors.c rename to src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c -- To view, visit https://review.coreboot.org/c/coreboot/+/42785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifee91306756f8a4152a6a0224e172dae7eac8f7a Gerrit-Change-Number: 42785 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/soc_util: add comment on the silicon and soc types
by Felix Held (Code Review) 29 Jun '20

29 Jun '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42838 ) Change subject: soc/amd/picasso/soc_util: add comment on the silicon and soc types ...................................................................... soc/amd/picasso/soc_util: add comment on the silicon and soc types Change-Id: I71704ab292edf8bd343370e6b72c47a8f3aceffd Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/soc_util.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/42838/1 diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c index 8a1f8ef..887a71b 100644 --- a/src/soc/amd/picasso/soc_util.c +++ b/src/soc/amd/picasso/soc_util.c @@ -9,6 +9,14 @@ #include <soc/soc_util.h> #include <types.h> +/* + * The Zen/Zen+ based APUs can be RV (sometimes called RV1), PCO or RV2 silicon. RV2 has less + * PCIe, USB3 and Displayport connectivity than RV(1) or PCO. A Picasso SoC is always PCO + * silicon, a Dali SoC can either be RV2 or fused-down PCO silicon that has the same + * connectivity as the RV2 one and Pollock is always RV2 silicon. Picasso and Dali are in a FP5 + * package while Pollock is in the smaller FT5 package. + */ + #define SOCKET_TYPE_SHIFT 28 #define SOCKET_TYPSE_MASK (0xf << SOCKET_TYPE_SHIFT) -- To view, visit https://review.coreboot.org/c/coreboot/+/42838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71704ab292edf8bd343370e6b72c47a8f3aceffd Gerrit-Change-Number: 42838 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/{x230, x230s}: Disable SuperSpeed capabilities for wwan usb
by Bill XIE (Code Review) 29 Jun '20

29 Jun '20

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41505 ) Change subject: mb/lenovo/{x230, x230s}: Disable SuperSpeed capabilities for wwan usb ...................................................................... mb/lenovo/{x230, x230s}: Disable SuperSpeed capabilities for wwan usb Although on ThinkPads with Panther Point PCH the usb port inside wwan socket is usually wired to XHCI, it has actually no SuperSpeed lines, so maybe it is okay to disable SuperSpeed capabilities, and wire them to EHCI #2 by making use of XUSB2PRM and USB3PRM. This applies to both variants of x230 and t430s, and should to X1 Carbon Gen1, which I do not possess. Change-Id: Ia8d27be84e4dbfa0efed506b9fc010e7f4d6ba23 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/mainboard/lenovo/x230/devicetree.cb 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/41505/1 diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 3a8e5fe..b4247d1 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -58,8 +58,9 @@ register "gen2_dec" = "0x0c15e1" register "gen4_dec" = "0x0c06a1" - register "xhci_switchable_ports" = "0xf" - register "superspeed_capable_ports" = "0xf" + # Wire port 4 (wwan usb) to ehci for it lacks superspeed components + register "xhci_switchable_ports" = "0x7" + register "superspeed_capable_ports" = "0x7" register "xhci_overcurrent_mapping" = "0x4000201" # Enable zero-based linear PCIe root port functions -- To view, visit https://review.coreboot.org/c/coreboot/+/41505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8d27be84e4dbfa0efed506b9fc010e7f4d6ba23 Gerrit-Change-Number: 41505 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit June 2020