coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI F...
by Jonathan Zhang (Code Review) 30 Jun '20

30 Jun '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40308 ) Change subject: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data ...................................................................... Patch Set 51: Code-Review+1 LGTM -- To view, visit https://review.coreboot.org/c/coreboot/+/40308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c958dfad83216cd12545760a19d205efc2515b Gerrit-Change-Number: 40308 Gerrit-PatchSet: 51 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 30 Jun 2020 16:37:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/gpio: Drop unused macro GPIO_TRIGGER_INVALID
by Furquan Shaikh (Code Review) 30 Jun '20

30 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42868 ) Change subject: soc/amd/common/gpio: Drop unused macro GPIO_TRIGGER_INVALID ...................................................................... soc/amd/common/gpio: Drop unused macro GPIO_TRIGGER_INVALID This change drops unused macro GPIO_TRIGGER_VALID from gpio_banks.h. BUG=b:159944426 Change-Id: Ie115f37893d9ba190bab56cf8b037febd8b5f4b5 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/common/block/include/amdblocks/gpio_banks.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/42868/1 diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index 4a8a5ae..92aa8a2 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -113,8 +113,6 @@ GPIO_TRIGGER_EDGE_HIGH, }; -#define GPIO_TRIGGER_INVALID -1 - #define GPIO_SPECIAL_FLAG (1 << 31) #define GPIO_DEBOUNCE_FLAG (1 << 30) #define GPIO_WAKE_FLAG (1 << 29) -- To view, visit https://review.coreboot.org/c/coreboot/+/42868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie115f37893d9ba190bab56cf8b037febd8b5f4b5 Gerrit-Change-Number: 42868 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init
by Karthik Ramasubramanian (Code Review) 30 Jun '20

30 Jun '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42462 ) Change subject: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/42462/4/src/soc/intel/jasperlake/r… File src/soc/intel/jasperlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/42462/4/src/soc/intel/jasperlake/r… PS4, Line 84: SerialIoUartDebugMode > This is the new addition Karthik. […] Ok, makes sense. If that is the case, can you just assign the devicetree config here i.e. m_cfg->SerialIoUartDebugMode = config->SerialIoUartMode[CONFIG_UART_FOR_CONSOLE]; This will help to avoid the configuration from digressing. -- To view, visit https://review.coreboot.org/c/coreboot/+/42462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07 Gerrit-Change-Number: 42462 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 30 Jun 2020 16:13:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: Handle acpi_name and common code
by Tim Wawrzynczak (Code Review) 30 Jun '20

30 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41607 ) Change subject: drivers/intel/mipi_camera: Handle acpi_name and common code ...................................................................... Patch Set 28: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/41607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Gerrit-Change-Number: 41607 Gerrit-PatchSet: 28 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 30 Jun 2020 16:10:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in vboot[master]: Allow building for non-CrOS environments
by Patrick Georgi (Code Review) 30 Jun '20

30 Jun '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/vboot/+/42931 ) Change subject: Allow building for non-CrOS environments ...................................................................... Allow building for non-CrOS environments There's some code that is architecture specific, but looking at it, it's code for Chrome OS devices that just happens to be split along ISA lines. When compiling with NOCROS=1, these parts are left out, which allows building on unsupported ISA (such as POWER) and probably also helps support non-Linux hosts. The issue was reported at https://ticket.coreboot.org/issues/145 where a coreboot user wanted to build a vboot-enabled coreboot configuration (which builds futility for the signing part) on a POWER host system, which failed because we lack an implementation of the crossystem interfaces for POWER. BUG=none BRANCH=none TEST=Built upstream coreboot with a vboot-enabled target inside qemu-user-ppc64 and https://review.coreboot.org/c/coreboot/+/42853 applied. Doing so works with these patches applied while it failed without them. Change-Id: I4aaeb56d4521c426a520bc9a1bb49497bec86c35 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile 1 file changed, 18 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/vboot refs/changes/31/42931/1 diff --git a/Makefile b/Makefile index b35dc91..b06e841 100644 --- a/Makefile +++ b/Makefile @@ -451,9 +451,7 @@ cgpt/cgpt_repair.c \ cgpt/cgpt_show.c \ futility/dump_kernel_config_lib.c \ - host/arch/${ARCH}/lib/crossystem_arch.c \ host/lib/chromeos_config.c \ - host/lib/crossystem.c \ host/lib/crypto.c \ host/lib/file_keys.c \ host/lib/fmap.c \ @@ -471,6 +469,12 @@ host/lib21/host_misc.c \ host/lib21/host_signature.c +ifneq (${NOCROS},1) +UTILLIB_SRCS += \ + host/arch/${ARCH}/lib/crossystem_arch.c \ + host/lib/crossystem.c +endif + UTILLIB_OBJS = ${UTILLIB_SRCS:%.c=${BUILD}/%.o} ALL_OBJS += ${UTILLIB_OBJS} @@ -510,7 +514,6 @@ firmware/stub/vboot_api_stub_disk.c \ firmware/stub/vboot_api_stub_init.c \ futility/dump_kernel_config_lib.c \ - host/arch/${ARCH}/lib/crossystem_arch.c \ host/lib/chromeos_config.c \ host/lib/crossystem.c \ host/lib/crypto.c \ @@ -520,6 +523,10 @@ host/lib/subprocess.c \ ${TLCL_SRCS} +ifneq (${NOCROS},1) +HOSTLIB_SRCS += host/arch/${ARCH}/lib/crossystem_arch.c +endif + HOSTLIB_OBJS = ${HOSTLIB_SRCS:%.c=${BUILD}/%.o} ALL_OBJS += ${HOSTLIB_OBJS} @@ -631,7 +638,6 @@ futility/cmd_pcr.c \ futility/cmd_show.c \ futility/cmd_sign.c \ - futility/cmd_update.c \ futility/cmd_validate_rec_mrc.c \ futility/cmd_vbutil_firmware.c \ futility/cmd_vbutil_firmware.c \ @@ -645,12 +651,17 @@ futility/file_type_usbpd1.c \ futility/misc.c \ futility/ryu_root_header.c \ + futility/vb1_helper.c \ + futility/vb2_helper.c + +ifneq (${NOCROS},1) +FUTIL_SRCS += \ + futility/cmd_update.c \ futility/updater.c \ futility/updater_archive.c \ futility/updater_quirks.c \ - futility/updater_utils.c \ - futility/vb1_helper.c \ - futility/vb2_helper.c + futility/updater_utils.c +endif # List of commands built in futility. FUTIL_CMD_LIST = ${BUILD}/gen/futility_cmds.c -- To view, visit https://review.coreboot.org/c/vboot/+/42931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: master Gerrit-Change-Id: I4aaeb56d4521c426a520bc9a1bb49497bec86c35 Gerrit-Change-Number: 42931 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad Th...
by Johnny Li (Code Review) 30 Jun '20

30 Jun '20

Johnny Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42678 ) Change subject: mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad This change updates scl_lcnt,scl_hcnt,scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. ...................................................................... mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad This change updates scl_lcnt,scl_hcnt,scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:157999726 TEST= Verified that I2C5 frequency is between 389-396kHz. Change-Id: I20cb10455932822744b09aa347e271a0ec064eb6 --- M src/mainboard/google/volteer/variants/volteer/overridetree.cb 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/42678/1 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 9e5ef4b..076faf7 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -1,4 +1,32 @@ chip soc/intel/tigerlake + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" device domain 0 on device pci 15.0 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/42678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20cb10455932822744b09aa347e271a0ec064eb6 Gerrit-Change-Number: 42678 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init
by Maulik V Vaghela (Code Review) 30 Jun '20

30 Jun '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42462 ) Change subject: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/42462/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42462/4//COMMIT_MSG@17 PS4, Line 17: > Nit: Please remove the extra line. Also I believe Cq-Depend: should be marked as TBD. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/42462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07 Gerrit-Change-Number: 42462 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 30 Jun 2020 13:37:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init
by Maulik V Vaghela (Code Review) 30 Jun '20

30 Jun '20

Hello build bot (Jenkins), Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Aamir Bohra, Krishna P Bhat D, Ronak Kanabar, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42462 to look at the new patch set (#5). Change subject: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init ...................................................................... soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init Since coreboot is initializing uart for debug logs, fsp should not reinitialize it. Thus we need to set FSP UPD to skip Uart init in FSP and use settings done by coreboot BUG=None BRANCH=None TEST=FSP is able to push debug logs on UART with this setting Cq-Depend: TBD Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/jasperlake/romstage/fsp_params.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/42462/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/42462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07 Gerrit-Change-Number: 42462 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init
by Maulik V Vaghela (Code Review) 30 Jun '20

30 Jun '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42462 ) Change subject: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/42462/4/src/soc/intel/jasperlake/r… File src/soc/intel/jasperlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/42462/4/src/soc/intel/jasperlake/r… PS4, Line 84: SerialIoUartDebugMode > I believe FSP has been initializing the debug UART in its current form. […] This is the new addition Karthik. In current devicetree, we set UARTs as either Disable or SkipInit to avoid reinitialize in FSP. This is the new parameter which is being introduced in latest FSP version and if we don't set it, fsp may reinitialize UART to different BAR address and may create an issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/42462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07 Gerrit-Change-Number: 42462 Gerrit-PatchSet: 4 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 30 Jun 2020 13:37:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad
by Johnny Li (Code Review) 30 Jun '20

30 Jun '20

Johnny Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42909 ) Change subject: mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad ...................................................................... mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad This change updates scl_lcnt,scl_hcnt,scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:157999726 TEST= Verified that I2C5 frequency is between 389-396kHz. Change-Id: I3061a3a8188c020ee7ca31bcddccbd16f31761e4 --- M src/mainboard/google/volteer/variants/volteer/overridetree.cb 1 file changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/42909/1 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 9e5ef4b..6a4b875 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -88,5 +88,49 @@ end end end # PMC + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" end end -- To view, visit https://review.coreboot.org/c/coreboot/+/42909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3061a3a8188c020ee7ca31bcddccbd16f31761e4 Gerrit-Change-Number: 42909 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2020