coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/zork: Configure GPIO_40 as drive low in sleep path
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42935 to review the following change. Change subject: mb/google/zork: Configure GPIO_40 as drive low in sleep path ...................................................................... mb/google/zork: Configure GPIO_40 as drive low in sleep path This change configures GPIO_40 (NVME_AUX_RESET_L) as drive low in sleep path so that the PERST# to NVMe device keeps asserted until coreboot reconfigures it as high on S3 resume path. This is similar to the earlier change for PCIE_RST1_L but helps platforms that use NVME_AUX_RESET_L instead of PCIE_RST1_L. GPIO_40 lives in S5 domain, hence it retains state across S3 entry/exit. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Ie79e946eee8f393863630226ae2183e653030415 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Reviewed-by: Aaron Durbin <adurbin(a)google.com> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/42935/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c index 1dd2dd5..aacf14b 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c @@ -36,6 +36,8 @@ PAD_GPO(GPIO_5, LOW), /* PCIE_RST1_L */ PAD_GPO(GPIO_27, LOW), + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, LOW), /* EN_PWR_CAMERA */ PAD_GPO(GPIO_76, LOW), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/42935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie79e946eee8f393863630226ae2183e653030415 Gerrit-Change-Number: 42935 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Reconfigure PCIE_RST1_L as GPO driven low on sleep path
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42934 to review the following change. Change subject: mb/google/zork: Reconfigure PCIE_RST1_L as GPO driven low on sleep path ...................................................................... mb/google/zork: Reconfigure PCIE_RST1_L as GPO driven low on sleep path This change configures PCIE_RST1_L as GPO driven low on the sleep path. This is required to keep PERST# asserted to devices until coreboot deasserts it on S3 resume path. Without this change, on S3 resume, PCIE_RST1_L gets deasserted sooner than required resulting in violation of PCIe reset timings. With this change, the behavior of PCIE_RST1_L is as follows: 1. GPIO27 is configured as NF (PCIE_RST1_L) in coreboot bootblock/romstage and driven high. 2. On S3 entry, GPIO27 is configured as GPO driven low. * Boot out of G3: Timing should be met since GPIO_27 is pulled down by default until coreboot configures it. * S3 resume: Timing should be met since GPIO_27 is configured as GPO low and it retains state across S3 entry/exit. So, should be low until coreboot configures it. * Warm reset: Timing should be met since it is configured as NF. So, hardware guarantees the reset timing as seen in "warm reset.jpg" in #46. BUG=b:152582706 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Ia0ad1522edc438fd054d927ef4a2ab5c27329c00 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Reviewed-by: Aaron Durbin <adurbin(a)google.com> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/42934/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c index e43b0b4c..1dd2dd5 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c @@ -34,6 +34,8 @@ static const struct soc_amd_gpio gpio_sleep_table[] = { /* PEN_POWER_EN */ PAD_GPO(GPIO_5, LOW), + /* PCIE_RST1_L */ + PAD_GPO(GPIO_27, LOW), /* EN_PWR_CAMERA */ PAD_GPO(GPIO_76, LOW), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/42934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0ad1522edc438fd054d927ef4a2ab5c27329c00 Gerrit-Change-Number: 42934 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Turn off power to camera and pen in sleep path
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42933 to review the following change. Change subject: mb/google/zork: Turn off power to camera and pen in sleep path ...................................................................... mb/google/zork: Turn off power to camera and pen in sleep path This change turns off power to camera and pen devices when entering sleep since they do not act as wake sources in S3. Power to trackpad and WiFi is left enabled since they are wake sources for S3. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I21bcdd53370372c7d43c3b685abb2a9171e42d22 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Reviewed-by: Aaron Durbin <adurbin(a)google.com> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/42933/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c index 614e837..e43b0b4c 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c @@ -32,6 +32,10 @@ } static const struct soc_amd_gpio gpio_sleep_table[] = { + /* PEN_POWER_EN */ + PAD_GPO(GPIO_5, LOW), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, LOW), }; const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) -- To view, visit https://review.coreboot.org/c/coreboot/+/42933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21bcdd53370372c7d43c3b685abb2a9171e42d22 Gerrit-Change-Number: 42933 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Add support for GPIO configuration on sleep path
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42932 to review the following change. Change subject: mb/google/zork: Add support for GPIO configuration on sleep path ...................................................................... mb/google/zork: Add support for GPIO configuration on sleep path This change adds support to configure GPIOs on the sleep path. This is required to turn off power to devices that do not act as wake sources and to assert reset to devices. Currently, variant_sleep_gpio_table() returns an empty table by default. In the following changes, entries will be added to gpio_sleep_table. BUG=b:152582706 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I7286cbf165024bdd81f8748e525542dce8dd8702 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Tested-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)google.com> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/zork/smihandler.c M src/mainboard/google/zork/variants/baseboard/Makefile.inc M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h 4 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/42932/1 diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c index 7c88215..12a3b64 100644 --- a/src/mainboard/google/zork/smihandler.c +++ b/src/mainboard/google/zork/smihandler.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ + #include <acpi/acpi.h> +#include <baseboard/variants.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/smm.h> #include <gpio.h> @@ -15,10 +17,17 @@ } void mainboard_smi_sleep(u8 slp_typ) { + size_t num_gpios; + const struct soc_amd_gpio *gpios; + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); + + gpios = variant_sleep_gpio_table(&num_gpios, slp_typ); + program_gpios(gpios, num_gpios); } + int mainboard_smi_apmc(u8 apmc) { if (CONFIG(EC_GOOGLE_CHROMEEC)) diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc index 7e4ccae..0f025e0 100644 --- a/src/mainboard/google/zork/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc @@ -24,6 +24,8 @@ ramstage-y += helpers.c ramstage-y += tpm_tis.c +smm-y += gpio_baseboard_common.c + # Add OEM ID table ifeq ($(CONFIG_USE_OEM_BIN),y) cbfs-files-y += oem.bin diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c index a4e8648..614e837 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c @@ -30,3 +30,12 @@ *size = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +static const struct soc_amd_gpio gpio_sleep_table[] = { +}; + +const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) +{ + *size = ARRAY_SIZE(gpio_sleep_table); + return gpio_sleep_table; +} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 4f8f225..6c5b95b 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -25,6 +25,13 @@ * configuration provided by variant_base_gpio_table(). */ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size); + +/* + * This function provides GPIO table for the pads that need to be configured when entering + * sleep. + */ +const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ); + void variant_romstage_entry(void); /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/42932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7286cbf165024bdd81f8748e525542dce8dd8702 Gerrit-Change-Number: 42932 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Remove unused structs
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42695 ) Change subject: nb/intel/ironlake: Remove unused structs ...................................................................... nb/intel/ironlake: Remove unused structs These were copied from gm45, but are not used. Drop them. Change-Id: I85ca37516272a2c1af88a65df2682e92d7579050 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/ironlake.h 1 file changed, 0 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/42695/1 diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 93d55a9..53efced 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -3,38 +3,6 @@ #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ -#ifndef __ASSEMBLER__ - -typedef struct { - unsigned int CAS; - unsigned int tRAS; - unsigned int tRP; - unsigned int tRCD; - unsigned int tRFC; - unsigned int tWR; - unsigned int tRD; - unsigned int tRRD; - unsigned int tFAW; - unsigned int tWL; -} timings_t; - -/* The setup is one DIMM per channel, so there's no need to find a - common timing setup between multiple chips (but chip and controller - still need to be coordinated */ -typedef struct { - int txt_enabled; - int cores; - int max_ddr2_mhz; - int max_ddr3_mt; - int max_fsb_mhz; - int max_render_mhz; - - int spd_type; - timings_t selected_timings; -} sysinfo_t; - -#endif - #define DEFAULT_HECIBAR ((u8 *)0xfed17000) -- To view, visit https://review.coreboot.org/c/coreboot/+/42695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ca37516272a2c1af88a65df2682e92d7579050 Gerrit-Change-Number: 42695 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/pineview: Drop undefined function declaration
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42694 ) Change subject: nb/intel/pineview: Drop undefined function declaration ...................................................................... nb/intel/pineview: Drop undefined function declaration This function isn't defined anywhere for Pineview. Drop its declaration. Change-Id: I38a01d6ba5aaa91de08702c1eb8a2e8c70688192 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/pineview/pineview.h 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/42694/1 diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 55d098b..7c41b4c 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -239,7 +239,4 @@ void get_mb_spd_addrmap(u8 *spd_addr_map); void mb_pirq_setup(void); /* optional */ -struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp); - #endif /* NORTHBRIDGE_INTEL_PINEVIEW_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38a01d6ba5aaa91de08702c1eb8a2e8c70688192 Gerrit-Change-Number: 42694 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tgl: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry
by Jamie Ryu (Code Review) 01 Jul '20

01 Jul '20

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42790 ) Change subject: soc/intel/tgl: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry ...................................................................... soc/intel/tgl: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry This is a W/A to avoid a communication issue with CSE Lite over Heci interface. This will help to avoid boot failures with CSE Lite until the permanent fix is available. BUG=b:158643194 TEST=build and boot volteer with serial and non-serial image Change-Id: Ib136a2154b36c63c7147bbcfbf1ca7beac3a5685 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/42790/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 3077c7f..a0b1e10 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -361,4 +361,4 @@ } } -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, cse_fw_sync, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/42790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib136a2154b36c63c7147bbcfbf1ca7beac3a5685 Gerrit-Change-Number: 42790 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/nightfury: Override VBT selection for nightfury 2nd sku
by shkim (Code Review) 01 Jul '20

01 Jul '20

Hello SH Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42904 to review the following change. Change subject: mb/google/nightfury: Override VBT selection for nightfury 2nd sku ...................................................................... mb/google/nightfury: Override VBT selection for nightfury 2nd sku Override VBT for nightfury SKU_ID = 2 to support different panel. BUG=b:159051021 BRANCH=firmware-hatch-12672.B TEST=Built and verified using different VBT by SKU_ID Change-Id: I9450814aadc43cc7991457c3793f109b889186b9 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/variant.c 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/42904/1 diff --git a/src/mainboard/google/hatch/variants/nightfury/Makefile.inc b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc index 7799cd2..05f77ad 100644 --- a/src/mainboard/google/hatch/variants/nightfury/Makefile.inc +++ b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc @@ -10,3 +10,4 @@ ramstage-y += gpio.c ramstage-y += ramstage.c +ramstage-y += variant.c diff --git a/src/mainboard/google/hatch/variants/nightfury/variant.c b/src/mainboard/google/hatch/variants/nightfury/variant.c new file mode 100644 index 0000000..8fede2c --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/variant.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <ec/google/chromeec/ec.h> +#include <drivers/intel/gma/opregion.h> + +const char *mainboard_vbt_filename(void) +{ + uint32_t sku_id = google_chromeec_get_board_sku(); + + if (sku_id == 2) + return "vbt-nightfury-qled.bin"; + else + return "vbt.bin"; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9450814aadc43cc7991457c3793f109b889186b9 Gerrit-Change-Number: 42904 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util: Compile vboot with CrOS parts disabled
by Patrick Georgi (Code Review) 01 Jul '20

01 Jul '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42853 ) Change subject: util: Compile vboot with CrOS parts disabled ...................................................................... util: Compile vboot with CrOS parts disabled With CL:2270096 merged, vboot can be built with CrOS specific support disabled. Use this feature so our build becomes more portable. Fixes https://ticket.coreboot.org/issues/145 Change-Id: Ice1955623779792af4d0b87872827f6fbe687e31 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/cbfstool/Makefile.inc M util/futility/Makefile.inc 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/42853/1 diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index f38c825..f41724a 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -133,6 +133,7 @@ unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$(VBOOT_HOST_BUILD) \ CC="$(HOSTCC)" \ + NOCROS=1 \ $(if $(HOSTPKGCONFIG), PKG_CONFIG="$(HOSTPKGCONFIG)") \ V=$(V) \ hostlib diff --git a/util/futility/Makefile.inc b/util/futility/Makefile.inc index ee4ad05..d3f0441 100644 --- a/util/futility/Makefile.inc +++ b/util/futility/Makefile.inc @@ -7,6 +7,7 @@ unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$(VBOOT_HOST_BUILD) \ CC="$(HOSTCC)" \ + NOCROS=1 \ $(if $(HOSTPKGCONFIG), PKG_CONFIG="$(HOSTPKGCONFIG)") \ V=$(V) \ $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/42853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice1955623779792af4d0b87872827f6fbe687e31 Gerrit-Change-Number: 42853 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cpu: Don't set any TCC settings if offset is 0
by Tim Wawrzynczak (Code Review) 01 Jul '20

01 Jul '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42879 ) Change subject: soc/intel/common/cpu: Don't set any TCC settings if offset is 0 ...................................................................... soc/intel/common/cpu: Don't set any TCC settings if offset is 0 Many previous versions of this function would return early if tcc_offset is 0. This adds that logic back in. Change-Id: Ibc529520a4e74608cb5d20e5a6e8fc2c727c903c Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cpu/cpulib.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/42879/1 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 0ac8dda..e4ab664 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -260,15 +260,20 @@ const config_t *conf = config_of_soc(); msr_t msr; + if (!conf->tcc_offset) + return; + /* Set TCC activation offset */ msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & BIT(30)) && conf->tcc_offset) { + if ((msr.lo & BIT(30))) { msr = rdmsr(MSR_TEMPERATURE_TARGET); msr.lo &= ~(0xf << 24); msr.lo |= (conf->tcc_offset & 0xf) << 24; wrmsr(MSR_TEMPERATURE_TARGET, msr); } + msr = rdmsr(MSR_TEMPERATURE_TARGET); + /* Time Window Tau Bits [6:0] */ msr.lo &= ~0x7f; msr.lo |= 0xe6; /* setting 100ms thermal time window */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc529520a4e74608cb5d20e5a6e8fc2c727c903c Gerrit-Change-Number: 42879 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit June 2020