coreboot-gerrit June 2020

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Change in coreboot[master]: drivers/pc80/tpm: Remove LPC_TPM
by Kyösti Mälkki (Code Review) 04 Jul '20

04 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41872 ) Change subject: drivers/pc80/tpm: Remove LPC_TPM ...................................................................... drivers/pc80/tpm: Remove LPC_TPM Replace uses with MAINBOARD_HAS_LPC_TPM, if drivers/pc80/tpm is present in devicetree.cb it is necessary to always include the driver in the build. Change-Id: I9ab921ab70f7b527a52fbf5f775aa063d9a706ce Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M configs/builder/config.lenovo_t420 M configs/builder/config.lenovo_t420s M configs/builder/config.lenovo_t430s M configs/builder/config.lenovo_t520 M configs/builder/config.lenovo_t530 M configs/builder/config.lenovo_x220 M configs/builder/config.lenovo_x220i M configs/builder/config.lenovo_x230 M src/drivers/pc80/tpm/Kconfig M src/drivers/pc80/tpm/Makefile.inc M src/security/tpm/Kconfig 11 files changed, 10 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/41872/1 diff --git a/configs/builder/config.lenovo_t420 b/configs/builder/config.lenovo_t420 index e4e4b9b..5ac036d 100644 --- a/configs/builder/config.lenovo_t420 +++ b/configs/builder/config.lenovo_t420 @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_t420s b/configs/builder/config.lenovo_t420s index 7593b7a..f0b312b 100644 --- a/configs/builder/config.lenovo_t420s +++ b/configs/builder/config.lenovo_t420s @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_t430s b/configs/builder/config.lenovo_t430s index b21dbba..682b17e 100644 --- a/configs/builder/config.lenovo_t430s +++ b/configs/builder/config.lenovo_t430s @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_t520 b/configs/builder/config.lenovo_t520 index 1d7816e..4bbbb25 100644 --- a/configs/builder/config.lenovo_t520 +++ b/configs/builder/config.lenovo_t520 @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_t530 b/configs/builder/config.lenovo_t530 index 0106bbc..635e355 100644 --- a/configs/builder/config.lenovo_t530 +++ b/configs/builder/config.lenovo_t530 @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_x220 b/configs/builder/config.lenovo_x220 index da5a474..29d9639 100644 --- a/configs/builder/config.lenovo_x220 +++ b/configs/builder/config.lenovo_x220 @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_x220i b/configs/builder/config.lenovo_x220i index 5612f5b..24e381d 100644 --- a/configs/builder/config.lenovo_x220i +++ b/configs/builder/config.lenovo_x220i @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_x230 b/configs/builder/config.lenovo_x230 index d897f44..5040145 100644 --- a/configs/builder/config.lenovo_x230 +++ b/configs/builder/config.lenovo_x230 @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/src/drivers/pc80/tpm/Kconfig b/src/drivers/pc80/tpm/Kconfig index 853801b..4a40b29 100644 --- a/src/drivers/pc80/tpm/Kconfig +++ b/src/drivers/pc80/tpm/Kconfig @@ -1,13 +1,14 @@ -config LPC_TPM +config MAINBOARD_HAS_LPC_TPM bool default n help - LPC TPM driver is enabled! + Board has LPC TPM support + +if MAINBOARD_HAS_LPC_TPM config TPM_TIS_BASE_ADDRESS hex default 0xfed40000 - depends on LPC_TPM help This can be used to adjust the TPM memory base address. The default is specified by the TCG PC Client Specific TPM @@ -17,14 +18,8 @@ config TPM_PIRQ hex default 0x0 - depends on LPC_TPM help This can be used to specify a PIRQ to use instead of SERIRQ, which is needed for SPI TPM interrupt support on x86. -config MAINBOARD_HAS_LPC_TPM - bool - default n - select LPC_TPM - help - Board has LPC TPM support +endif diff --git a/src/drivers/pc80/tpm/Makefile.inc b/src/drivers/pc80/tpm/Makefile.inc index 0de1b76..a16f6af 100644 --- a/src/drivers/pc80/tpm/Makefile.inc +++ b/src/drivers/pc80/tpm/Makefile.inc @@ -1,4 +1,4 @@ -verstage-$(CONFIG_LPC_TPM) += tis.c -romstage-$(CONFIG_LPC_TPM) += tis.c -ramstage-$(CONFIG_LPC_TPM) += tis.c -postcar-$(CONFIG_LPC_TPM) += tis.c +verstage-$(CONFIG_MAINBOARD_HAS_LPC_TPM) += tis.c +romstage-$(CONFIG_MAINBOARD_HAS_LPC_TPM) += tis.c +ramstage-$(CONFIG_MAINBOARD_HAS_LPC_TPM) += tis.c +postcar-$(CONFIG_MAINBOARD_HAS_LPC_TPM) += tis.c diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index b6a7781..e1255d1 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -82,7 +82,7 @@ config TPM_RDRESP_NEED_DELAY bool "Enable Delay Workaround for TPM" default n - depends on LPC_TPM + depends on MAINBOARD_HAS_LPC_TPM help Certain TPMs seem to need some delay when reading response to work around a race-condition-related issue, possibly -- To view, visit https://review.coreboot.org/c/coreboot/+/41872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ab921ab70f7b527a52fbf5f775aa063d9a706ce Gerrit-Change-Number: 41872 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: doc/mb/ocp: Add documentation for Delta Lake
by Jonathan Zhang (Code Review) 04 Jul '20

04 Jul '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42947 ) Change subject: doc/mb/ocp: Add documentation for Delta Lake ...................................................................... doc/mb/ocp: Add documentation for Delta Lake Add OCP platform Delta Lake documentation. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e --- A Documentation/mainboard/ocp/deltalake.md 1 file changed, 98 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/42947/1 diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md new file mode 100644 index 0000000..3af893a --- /dev/null +++ b/Documentation/mainboard/ocp/deltalake.md @@ -0,0 +1,98 @@ +# OCP Delta Lake + +This page describes coreboot support status for the [OCP] (Open Compute Project) +Delta Lake server platform. + +## Introduction + +OCP Delta Lake server platform is a component of multi-host server system +Yosemite-V3. Both were announced by Facebook and Intel in [OCP virtual summit 2020]. + +Delta Lake server is a one socket CooperLake Sacalable Processor server. + +Yosemite-V3 has multiple configurations. Depending on configurations, it may +host up to 4 Delta Lake servers in one sled. + +Yosemite-V3 and Delta Lake are currently in DVT phase. Facebook, Intel and partners +jointly develop FSP/coreboot/Linuxboot solution on Delta Lake as a hack project. + +## Required blobs + +This board currently requires: +- FSP blob: The blob (Intel CooperLake Scalable Processor Firmware Support Package) + is not yet available to the public. It will be made public some time after the MP + of CooperLake Scalable Processor when the FSP is mature. +- Microcode: Not yet available to the public. +- ME binary: Not yet available to the public. + +## Payload +- Linuxboot: This is necessary only if you use Linuxboot as coreboot payload. + U-root as initramfs, is used in the joint development. It can be built + following [All about u-root]. + +## Flashing coreboot + +To do in-band FW image update, use [flashrom]: + flashrom -p internal:ich_spi_mode=hwseq -c "Opaque flash chip" --ifd \ + -i bios --noverify-all -w <path to coreboot image> + +From OpenBMC, to update FW image: + fw-util slotx --update bios <path to coreboot image> + +To power off/on the host: + power-util slotx off + power-util slotx on + +To connect to console through SOL (Serial Over Lan): + sol-util slotx + +## Working features +The solution is developed using Linuxboot payload. The Linuxboot +kernel versions tried is 5.2.9. The initramfs image is u-root. +- Most SMBIOS types +- BMC integration: + - BMC readiness check + - IPMI commands + - watchdog timer + - POST complete pin acknowledgement +- SEL record generation +- Early serial output +- port 80h direct to GPIO +- ACPI tables: APIC/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT +- Skipping memory training upon subsequent reboots +- BMC crash dump +- Error injection through ITP + +## Firmware configurations +[ChromeOS VPD] is used to store most of firmware configurations. RO_VPD +holds default values, while RW_VPD holds customized values. + +VPD variables supported are: +- firmware_version: This variable holds overall firmware version. coreboot + uses its value to populate smbios type 1 version field. + +## Known issues / feature gaps +- Even though CPX-SP FSP is based on FSP 2.2 framework, it does not + support FSP_USES_CB_STACK. An IPS ticket is filed with Intel. +- VT-d is not supported. An IPS ticket is filed with Intel. +- PCIe bifuration is not supported. An IPS ticket is filed with Intel. +- SMBIOS type 7 and type 17 are not populated. +- ME based power capping. + +## Technology + +```eval_rst ++------------------------+---------------------------------------------+ +| Processor (1 socket) | Intel CooperLake Scalable Processor | ++------------------------+---------------------------------------------+ +| BMC | Aspeed AST 2500 | ++------------------------+---------------------------------------------+ +| PCH | Intel Lewisburg C621 | ++------------------------+---------------------------------------------+ +``` + +[OCP]: https://www.opencompute.org +[OCP virtual summit 2020]: https://www.opencompute.org/summit/virtual-summit/schedule +[flashrom]: https://flashrom.org/Flashrom +[All about u-root]: https://github.com/linuxboot/book/tree/master/u-root +[ChromeOS VPD]: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md -- To view, visit https://review.coreboot.org/c/coreboot/+/42947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e Gerrit-Change-Number: 42947 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: MAINTAINERS: Add Maintainers for Prodrive Hermes Mainboard
by Christian Walter (Code Review) 04 Jul '20

04 Jul '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42479 ) Change subject: MAINTAINERS: Add Maintainers for Prodrive Hermes Mainboard ...................................................................... MAINTAINERS: Add Maintainers for Prodrive Hermes Mainboard Change-Id: Ifaed81016be9cd2845b3a2c55ee1a5ac4d317081 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M MAINTAINERS 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/42479/1 diff --git a/MAINTAINERS b/MAINTAINERS index e15e31c..a8c8365 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -367,6 +367,12 @@ S: Maintained F: src/mainboard/protectli/ +PRODRIVE HERMES MAINBOARD +M: Christian Walter <christian.walter(a)9elements.com> +M: Patrick Rudolph <patrick.rudolph(a)9elements.com> +S: Maintained +F: src/mainboard/prodrive/hermes + SIEMENS MC_xxxx MAINBOARDS M: Werner Zeh <werner.zeh(a)siemens.com> S: Maintained -- To view, visit https://review.coreboot.org/c/coreboot/+/42479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifaed81016be9cd2845b3a2c55ee1a5ac4d317081 Gerrit-Change-Number: 42479 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Populate SMBIOS data and set the read PPIN to BMC
by Johnny Lin (Code Review) 04 Jul '20

04 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41279 ) Change subject: mb/ocp/deltalake: Populate SMBIOS data and set the read PPIN to BMC ...................................................................... mb/ocp/deltalake: Populate SMBIOS data and set the read PPIN to BMC 1. Populate SMBIOS data from OCP_DMI driver read from FRU and PPIN MSR for OEM string 1 to 6, add string 8 for PCIE configuration. 2. Set the read PPIN MSR to BMC. Tested on OCP Delta Lake. Change-Id: I9127cf5da1c56d8012694d070615aec24cc22fdf Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/Makefile.inc A src/mainboard/ocp/deltalake/ipmi.c A src/mainboard/ocp/deltalake/ipmi.h M src/mainboard/ocp/deltalake/ramstage.c 5 files changed, 143 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/41279/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index d61a3a6..698c57b 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -9,6 +9,7 @@ select SOC_INTEL_COOPERLAKE_SP select SUPERIO_ASPEED_AST2400 select IPMI_KCS + select OCP_DMI config IPMI_KCS_REGISTER_SPACING int diff --git a/src/mainboard/ocp/deltalake/Makefile.inc b/src/mainboard/ocp/deltalake/Makefile.inc index 0cc98d4..90a3c10 100644 --- a/src/mainboard/ocp/deltalake/Makefile.inc +++ b/src/mainboard/ocp/deltalake/Makefile.inc @@ -19,7 +19,7 @@ romstage-y += romstage.c -ramstage-y += ramstage.c +ramstage-y += ramstage.c ipmi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ diff --git a/src/mainboard/ocp/deltalake/ipmi.c b/src/mainboard/ocp/deltalake/ipmi.c new file mode 100644 index 0000000..daf2d7b --- /dev/null +++ b/src/mainboard/ocp/deltalake/ipmi.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <console/console.h> +#include <drivers/ipmi/ipmi_kcs.h> +#include <drivers/ocp/dmi/ocp_dmi.h> + +#include "ipmi.h" + +enum cb_err ipmi_set_ppin(struct ppin_req *req) +{ + int ret; + struct ipmi_rsp rsp; + + ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN, + (const unsigned char *) req, sizeof(*req), + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + return CB_ERR; + } + + return CB_SUCCESS; +} + +enum cb_err ipmi_get_pcie_config(uint8_t *pcie_config) +{ + int ret; + struct ipmi_config_rsp { + struct ipmi_rsp resp; + uint8_t config; + } __packed; + struct ipmi_config_rsp rsp; + + ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_GET_PCIE_CONFIG, + NULL, 0, (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + *pcie_config = rsp.config; + + return CB_SUCCESS; +} diff --git a/src/mainboard/ocp/deltalake/ipmi.h b/src/mainboard/ocp/deltalake/ipmi.h new file mode 100644 index 0000000..6134d21 --- /dev/null +++ b/src/mainboard/ocp/deltalake/ipmi.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#ifndef DELTALAKE_IPMI_H +#define DELTALAKE_IPMI_H +#include <types.h> + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_OEM_SET_PPIN 0x77 +#define IPMI_OEM_GET_PCIE_CONFIG 0xf4 + +#define PCIE_CONFIG_UNKNOWN 0x0 +#define PCIE_CONFIG_A 0x1 +#define PCIE_CONFIG_B 0x2 +#define PCIE_CONFIG_C 0x3 +#define PCIE_CONFIG_D 0x4 + +struct ppin_req { + uint32_t cpu0_lo; + uint32_t cpu0_hi; + uint32_t cpu1_lo; + uint32_t cpu1_hi; +} __packed; + +enum cb_err ipmi_set_ppin(struct ppin_req *req); +enum cb_err ipmi_get_pcie_config(uint8_t *config); +#endif diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index c9e3fbb..44699a3 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -1,8 +1,74 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include <console/console.h> +#include <drivers/ipmi/ipmi_ops.h> +#include <drivers/ocp/dmi/ocp_dmi.h> #include <soc/ramstage.h> +#include <stdio.h> + +#include "ipmi.h" + +extern struct fru_info_str fru_strings; + +static void dl_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + uint8_t pcie_config = 0; + + /* OEM string 1 to 6 */ + ocp_oem_smbios_strings(dev, t); + + /* TODO: Add real OEM string 7, add TBF for now */ + t->count = smbios_add_oem_string(t->eos, TBF); + + /* Add OEM string 8 */ + if (ipmi_get_pcie_config(&pcie_config) == CB_SUCCESS) { + switch (pcie_config) { + case PCIE_CONFIG_UNKNOWN: + t->count = smbios_add_oem_string(t->eos, "0x0: Unknown"); + break; + case PCIE_CONFIG_A: + t->count = smbios_add_oem_string(t->eos, "0x1: YV3 Config-A"); + break; + case PCIE_CONFIG_B: + t->count = smbios_add_oem_string(t->eos, "0x2: YV3 Config-B"); + break; + case PCIE_CONFIG_C: + t->count = smbios_add_oem_string(t->eos, "0x3: YV3 Config-C"); + break; + case PCIE_CONFIG_D: + t->count = smbios_add_oem_string(t->eos, "0x4: YV3 Config-D"); + break; + default: + t->count = smbios_add_oem_string(t->eos, "Check BMC return data"); + } + } else { + printk(BIOS_ERR, "Failed to get IPMI PCIe config\n"); + } +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->get_smbios_strings = dl_oem_smbios_strings, + read_fru_areas(BMC_KCS_BASE, FRU_DEVICE_ID, 0, &fru_strings); +} void mainboard_silicon_init_params(FSPS_UPD *params) { } + +static void mainboard_final(void *chip_info) +{ + struct ppin_req req = {0}; + + req.cpu0_lo = xeon_sp_ppin[0].lo; + req.cpu0_hi = xeon_sp_ppin[0].hi; + /* Set PPIN to BMC */ + if (ipmi_set_ppin(&req) != CB_SUCCESS) + printk(BIOS_ERR, "ipmi_set_ppin failed\n"); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/41279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9127cf5da1c56d8012694d070615aec24cc22fdf Gerrit-Change-Number: 41279 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Add read CPU PPIN MSR function
by Johnny Lin (Code Review) 04 Jul '20

04 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42901 ) Change subject: soc/intel/xeon_sp: Add read CPU PPIN MSR function ...................................................................... soc/intel/xeon_sp: Add read CPU PPIN MSR function Tested on OCP Tioga Pass and Delta Lake. Change-Id: I8c2eac055a065c06859a3cb7b48ed59f15ae2fc4 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/skx/include/soc/cpu.h 4 files changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/42901/1 diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 386401f..1df5c13 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -188,3 +188,34 @@ /* update numa domain for all cpu devices */ xeonsp_init_cpu_config(); } + +msr_t read_msr_ppin(void) +{ + msr_t ppin = {0}; + msr_t msr; + + /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & MSR_PPIN_CAP) == 0) { + printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n"); + return ppin; + } + + /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */ + msr = rdmsr(MSR_PPIN_CTL); + if (msr.lo & MSR_PPIN_CTL_LOCK) { + printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n"); + return ppin; + } + + if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) { + /* Set MSR_PPIN_CTL ENABLE to 1 */ + msr.lo |= MSR_PPIN_CTL_ENABLE; + wrmsr(MSR_PPIN_CTL, msr); + } + ppin = rdmsr(MSR_PPIN); + /* Set enable to 0 after reading MSR_PPIN */ + msr.lo &= ~MSR_PPIN_CTL_ENABLE; + wrmsr(MSR_PPIN_CTL, msr); + return ppin; +} diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 2d12699..1458000 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -4,6 +4,7 @@ #define _SOC_CPU_H #include <device/device.h> +#include <cpu/x86/msr.h> #define CPUID_COOPERLAKE_SP_A0 0x05065a @@ -11,5 +12,6 @@ #define CPU_BCLK 100 void cpx_init_cpus(struct device *dev); +msr_t read_msr_ppin(void); #endif diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index f97c37d..c59edab 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -244,3 +244,34 @@ FUNC_EXIT(); } + +msr_t read_msr_ppin(void) +{ + msr_t ppin = {0}; + msr_t msr; + + /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & MSR_PPIN_CAP) == 0) { + printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n"); + return ppin; + } + + /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */ + msr = rdmsr(MSR_PPIN_CTL); + if (msr.lo & MSR_PPIN_CTL_LOCK) { + printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n"); + return ppin; + } + + if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) { + /* Set MSR_PPIN_CTL ENABLE to 1 */ + msr.lo |= MSR_PPIN_CTL_ENABLE; + wrmsr(MSR_PPIN_CTL, msr); + } + ppin = rdmsr(MSR_PPIN); + /* Set enable to 0 after reading MSR_PPIN */ + msr.lo &= ~MSR_PPIN_CTL_ENABLE; + wrmsr(MSR_PPIN_CTL, msr); + return ppin; +} diff --git a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h index 0221c7d..c2af265 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h @@ -4,6 +4,7 @@ #define _SOC_CPU_H_ #include <device/device.h> +#include <cpu/x86/msr.h> /* SKXSP CPUID */ #define CPUID_SKYLAKE_SP_A0_A1 0x506f0 @@ -15,5 +16,6 @@ int get_cpu_count(void); void xeon_sp_init_cpus(struct device *dev); +msr_t read_msr_ppin(void); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c2eac055a065c06859a3cb7b48ed59f15ae2fc4 Gerrit-Change-Number: 42901 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: drivers/ipmi: Add IPMI KCS support in romstage
by Johnny Lin (Code Review) 04 Jul '20

04 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40234 ) Change subject: drivers/ipmi: Add IPMI KCS support in romstage ...................................................................... drivers/ipmi: Add IPMI KCS support in romstage It's necessary to run IPMI commands in romstage for writing error SEL such as memory initialization error SEL, and also for other usages such as starting FRB2 timer, OEM commands, etc. Change-Id: Ie3198965670454b123e570f9056673fdf515f52b Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/drivers/ipmi/Kconfig M src/drivers/ipmi/Makefile.inc M src/drivers/ipmi/ipmi_kcs.h A src/drivers/ipmi/ipmi_kcs_ops_premem.c 4 files changed, 129 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40234/1 diff --git a/src/drivers/ipmi/Kconfig b/src/drivers/ipmi/Kconfig index 37cfc0d..0304cb0 100644 --- a/src/drivers/ipmi/Kconfig +++ b/src/drivers/ipmi/Kconfig @@ -18,3 +18,10 @@ IPMB messages are limited to 32-bytes total. When the data size is larger than this value, IPMI can complete reading/writing the data over multiple commands. + +config IPMI_KCS_ROMSTAGE + bool + default n + depends on IPMI_KCS + help + IPMI KCS support in romstage. diff --git a/src/drivers/ipmi/Makefile.inc b/src/drivers/ipmi/Makefile.inc index 973fff8..06a3433 100644 --- a/src/drivers/ipmi/Makefile.inc +++ b/src/drivers/ipmi/Makefile.inc @@ -2,3 +2,6 @@ ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs_ops.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_ops.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_fru.c +romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_kcs_ops_premem.c +romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_kcs.c +romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ops.c diff --git a/src/drivers/ipmi/ipmi_kcs.h b/src/drivers/ipmi/ipmi_kcs.h index 9a04377..5de77ed 100644 --- a/src/drivers/ipmi/ipmi_kcs.h +++ b/src/drivers/ipmi/ipmi_kcs.h @@ -40,6 +40,9 @@ const unsigned char *inmsg, int inlen, unsigned char *outmsg, int outlen); +/* Run basic IPMI init functions in romstage from the provided PnP device */ +void ipmi_kcs_premem_init(const u16 port, const u16 device); + struct ipmi_rsp { uint8_t lun; uint8_t cmd; diff --git a/src/drivers/ipmi/ipmi_kcs_ops_premem.c b/src/drivers/ipmi/ipmi_kcs_ops_premem.c new file mode 100644 index 0000000..e601041 --- /dev/null +++ b/src/drivers/ipmi/ipmi_kcs_ops_premem.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> + +#include <device/pnp.h> +#include <delay.h> +#include <timer.h> +#include "ipmi_kcs.h" +#include "chip.h" + +static int ipmi_get_bmc_self_test_result(const struct device *dev, + struct ipmi_selftest_rsp *rsp) +{ + int ret; + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_APPLICATION, 0, + IPMI_BMC_GET_SELFTEST_RESULTS, NULL, 0, (u8 *)rsp, + sizeof(*rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp->resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp->resp.completion_code); + return 1; + } + if (ret != sizeof(*rsp)) { + printk(BIOS_ERR, "IPMI: %s response truncated\n", __func__); + return 1; + } + + return 0; +} + +void ipmi_kcs_premem_init(const u16 port, const u16 device) +{ + const struct drivers_ipmi_config *conf = NULL; + struct ipmi_selftest_rsp selftestrsp; + uint8_t retry_count; + const struct device *dev; + + /* Find IPMI pnp device from devicetree in romstage */ + dev = dev_find_slot_pnp(port, device); + + if (!dev) { + printk(BIOS_ERR, "IPMI: Cannot find pnp device port: %x, device %x\n", + port, device); + return; + } + if (!dev->enabled) + return; + + printk(BIOS_DEBUG, "IPMI: romstage PNP KCS 0x%x\n", dev->path.pnp.port); + if (dev->chip_info) + conf = dev->chip_info; + + if (conf && conf->wait_for_bmc && conf->bmc_boot_timeout) { + struct stopwatch sw; + stopwatch_init_msecs_expire(&sw, conf->bmc_boot_timeout * 1000); + printk(BIOS_INFO, "IPMI: Waiting for BMC...\n"); + + while (!stopwatch_expired(&sw)) { + if (inb(dev->path.pnp.port) != 0xff) + break; + mdelay(100); + } + if (stopwatch_expired(&sw)) { + printk(BIOS_INFO, "IPMI: Waiting for BMC timed out\n"); + return; + } + } + + printk(BIOS_INFO, "Get BMC self test result..."); + for (retry_count = 0; retry_count < conf->bmc_boot_timeout; retry_count++) { + if (!ipmi_get_bmc_self_test_result(dev, &selftestrsp)) + break; + + mdelay(1000); + } + + switch (selftestrsp.result) { + case IPMI_APP_SELFTEST_NO_ERROR: /* 0x55 */ + printk(BIOS_DEBUG, "No Error\n"); + break; + case IPMI_APP_SELFTEST_NOT_IMPLEMENTED: /* 0x56 */ + printk(BIOS_DEBUG, "Function Not Implemented\n"); + break; + case IPMI_APP_SELFTEST_ERROR: /* 0x57 */ + printk(BIOS_ERR, "BMC: Corrupted or inaccessible data or device\n"); + /* Don't write tables if communication failed */ + break; + case IPMI_APP_SELFTEST_FATAL_HW_ERROR: /* 0x58 */ + printk(BIOS_ERR, "BMC: Fatal Hardware Error\n"); + /* Don't write tables if communication failed */ + break; + case IPMI_APP_SELFTEST_RESERVED: /* 0xFF */ + printk(BIOS_DEBUG, "Reserved\n"); + break; + + default: /* Other Device Specific Hardware Error */ + printk(BIOS_ERR, "BMC: Device Specific Error\n"); + /* Don't write tables if communication failed */ + break; + } + +} -- To view, visit https://review.coreboot.org/c/coreboot/+/40234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3198965670454b123e570f9056673fdf515f52b Gerrit-Change-Number: 40234 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-MessageType: newchange

7 28

Change in coreboot[master]: mb/google/volteer: Enable CSE Firmware Lite SKU
by Jamie Ryu (Code Review) 03 Jul '20

03 Jul '20

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42070 ) Change subject: mb/google/volteer: Enable CSE Firmware Lite SKU ...................................................................... mb/google/volteer: Enable CSE Firmware Lite SKU BUG=B:158140797 TEST=build and boot volteer with CSE Lite SKU Change-Id: I4f939883617a1271b30c76d41e61113bbdd6ab5b Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/google/volteer/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/42070/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 76acb9a..cc00b06 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -25,6 +25,7 @@ select MAINBOARD_HAS_TPM2 select PCIEXP_HOTPLUG select SOC_INTEL_TIGERLAKE + select SOC_INTEL_CSE_LITE_SKU if BOARD_GOOGLE_BASEBOARD_VOLTEER -- To view, visit https://review.coreboot.org/c/coreboot/+/42070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f939883617a1271b30c76d41e61113bbdd6ab5b Gerrit-Change-Number: 42070 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

5 24

Change in coreboot[master]: soc/intel/tgl: Disable hybrid storage mode in recovery mode
by Jamie Ryu (Code Review) 03 Jul '20

03 Jul '20

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42282 ) Change subject: soc/intel/tgl: Disable hybrid storage mode in recovery mode ...................................................................... soc/intel/tgl: Disable hybrid storage mode in recovery mode This is WA to initialize NVME with CSE Lite in recovery mode. CSME Lite does not support hybrid storage dynamic configuration in RO. Hence, hybrid storage mode is disabled in recovery mode for CSME Lite until the functionality is supported by CSE Lite RO. BUG=b:158643194 TEST=boot and verified with tglrvp and volteer in recovery mode Cq-Depend: chrome-internal:3100721 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: I5397cfc007069debe3701bf1e38e81bd17a29f0c --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/42282/1 diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c old mode 100644 new mode 100755 index 926d8eb..e931a22 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -10,6 +10,7 @@ #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> +#include <security/vboot/vboot_common.h> #include <soc/gpio_soc_defs.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> @@ -251,7 +252,17 @@ params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; /* Enable Hybrid storage auto detection */ - params->HybridStorageMode = config->HybridStorageMode; + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && vboot_recovery_mode_enabled()) { + /* + * Since CSME Lite SKU does not support hybrid storage dynamic + * configuration in recovery boot mode, dynamic configuration is + * disabled as a temporary WA until the fix is available. + */ + printk(BIOS_DEBUG, "cse_lite: recovery mode enabled\n"); + params->HybridStorageMode = 0; + } else { + params->HybridStorageMode = config->HybridStorageMode; + } /* USB4/TBT */ for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5397cfc007069debe3701bf1e38e81bd17a29f0c Gerrit-Change-Number: 42282 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

8 40

Change in coreboot[master]: drivers/intel/pmx_mux: Remove redundant declaration
by Kyösti Mälkki (Code Review) 03 Jul '20

03 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41871 ) Change subject: drivers/intel/pmx_mux: Remove redundant declaration ...................................................................... drivers/intel/pmx_mux: Remove redundant declaration Change-Id: Ie64b267ac01afa9774105e1ab8a7c18021726ff3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/pmc_mux/chip.h M src/soc/intel/tigerlake/pmc.c 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/41871/1 diff --git a/src/drivers/intel/pmc_mux/chip.h b/src/drivers/intel/pmc_mux/chip.h index f73a070..dcca2a3 100644 --- a/src/drivers/intel/pmc_mux/chip.h +++ b/src/drivers/intel/pmc_mux/chip.h @@ -3,8 +3,6 @@ #ifndef __DRIVERS_INTEL_PMC_MUX_H__ #define __DRIVERS_INTEL_PMC_MUX_H__ -extern struct chip_operations drivers_intel_pmc_mux_ops; - struct drivers_intel_pmc_mux_config { }; diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 84a18e3..8afa412 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -124,6 +124,9 @@ dev_path(dev)); } +/* FIXME: Rewrite loop below without this. */ +extern struct chip_operations drivers_intel_pmc_mux_ops; + /* By default, TGL uses the PMC MUX for all ports, so port_number is unused */ const struct device *soc_get_pmc_mux_device(int port_number) { -- To view, visit https://review.coreboot.org/c/coreboot/+/41871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie64b267ac01afa9774105e1ab8a7c18021726ff3 Gerrit-Change-Number: 41871 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: [WIP] mb/intel/cannonlake_rvp: Unconditionally select audio drivers
by Kyösti Mälkki (Code Review) 03 Jul '20

03 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41706 ) Change subject: [WIP] mb/intel/cannonlake_rvp: Unconditionally select audio drivers ...................................................................... [WIP] mb/intel/cannonlake_rvp: Unconditionally select audio drivers Change-Id: Ic9f2e44692b20c2efabc468b10ec531e8b5a3e59 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/intel/cannonlake_rvp/Kconfig 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/41706/1 diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig index e4885a8..b34079b 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -10,6 +10,9 @@ select GENERIC_SPD_BIN select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_DA7219 + select DRIVERS_I2C_MAX98373 + select DRIVERS_GENERIC_MAX98357A select SOC_INTEL_CANNONLAKE select MAINBOARD_USES_IFD_EC_REGION select INTEL_LPSS_UART_FOR_CONSOLE @@ -42,8 +45,6 @@ config INCLUDE_SND_MAX98357_DA7219_NHLT bool "Include blobs for audio with MAX98357_DA7219" - select DRIVERS_GENERIC_MAX98357A - select DRIVERS_I2C_DA7219 select NHLT_DMIC_4CH_16B select NHLT_DMIC_2CH_16B select NHLT_DA7219 @@ -51,7 +52,6 @@ config INCLUDE_SND_MAX98373_NHLT bool "Include blobs for audio with MAX98373" - select DRIVERS_I2C_MAX98373 select NHLT_DMIC_4CH_16B select NHLT_DMIC_2CH_16B select NHLT_MAX98373 -- To view, visit https://review.coreboot.org/c/coreboot/+/41706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9f2e44692b20c2efabc468b10ec531e8b5a3e59 Gerrit-Change-Number: 41706 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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