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Change in coreboot[master]: tests: Complete lib/string-test test case
by Anna Karas (Code Review) 06 Jul '20

06 Jul '20

Anna Karas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42311 ) Change subject: tests: Complete lib/string-test test case ...................................................................... tests: Complete lib/string-test test case Implement unit tests for remaining string library functions. Fix memory leak in test_strdup(). Signed-off-by: Anna Karas <aka(a)semihalf.com> Change-Id: I8ac6a6b2413d9077dc9ea81f638a2b0acd5c8862 --- M tests/lib/string-test.c 1 file changed, 212 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/42311/1 diff --git a/tests/lib/string-test.c b/tests/lib/string-test.c index 08f4177..39e9be9 100644 --- a/tests/lib/string-test.c +++ b/tests/lib/string-test.c @@ -1,50 +1,243 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> +#include <stdlib.h> +#include <stdint.h> #include <tests/test.h> +#define DST_SIZE 20 + /* * Important note: In every particular test, don't use any string-related * functions other than function under test. We are linking against * src/lib/string.c not the standard library. This is important for proper test - * isolation. One can use __builtin_xxx for many of the most simple str*() - * functions, when non-coreboot one is required. + * isolation. */ -struct strings_t { - char *str; - size_t size; -} strings[] = { - {"coreboot", 8}, - {"is\0very", 2}, /* strlen should be 2 because of the embedded \0 */ - {"nice\n", 5} +struct string_pairs_t { + char *dst; + char *src; +} string_pairs[] = { + {"Hello ", "world!"}, + {"He\0llo ", "world"}, + {"", "world!"}, + {"", ""}, }; -static void test_strlen_strings(void **state) -{ - int i; +const char *strings[] = { + "coreboot", + "is\0very", + "nice\n" +}; - for (i = 0; i < ARRAY_SIZE(strings); i++) - assert_int_equal(strings[i].size, strlen(strings[i].str)); -} +struct str_with_l_val_t { + char *str; + long value; +} str_with_l_val[] = { + {"42", 42}, + {"four42", 0}, + {"42five5", 42}, + {"4\02", 4}, + {"+42", 42}, + {"-42", -42}, + {"\t\n\r\f\v-42", -42}, +}; + +struct str_with_u_val_t { + char *str; + uint32_t value; +} str_with_u_val[] = { + {"42aa", 42}, + {"a", 0}, + {"0", 0}, + {"4a2", 4}, +}; static void test_strdup(void **state) { char str[] = "Hello coreboot\n"; - char *duplicate; - - duplicate = strdup(str); + char *duplicate = strdup(str); /* There is a more suitable Cmocka's function 'assert_string_equal()', but it is using strcmp() internally. */ assert_int_equal(0, memcmp(str, duplicate, __builtin_strlen(str))); + + free(duplicate); +} + +static void test_strconcat(void **state) +{ + int i; + size_t str_len, str2_len, res_len; + char *result; + + for (i = 0; i < ARRAY_SIZE(string_pairs); i++) { + str_len = __builtin_strlen(string_pairs[i].dst); + str2_len = __builtin_strlen(string_pairs[i].src); + + result = strconcat(string_pairs[i].dst, string_pairs[i].src); + res_len = __builtin_strlen(result); + + assert_int_equal(res_len, str_len + str2_len); + assert_int_equal(0, memcmp(string_pairs[i].dst, result, str_len)); + assert_int_equal(0, memcmp(string_pairs[i].src, result + str_len, str2_len)); + + free(result); + } +} + +static void test_strnlen(void **state) +{ + int i, n = 5; + size_t str_len, limited_len; + + for (i = 0; i < ARRAY_SIZE(strings); i++) { + str_len = __builtin_strlen(strings[i]); + limited_len = str_len > n ? n : str_len; + assert_int_equal(limited_len, strnlen(strings[i], n)); + } +} + +static void test_strlen(void **state) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(strings); i++) + assert_int_equal(__builtin_strlen(strings[i]), strlen(strings[i])); +} + +static void test_strchr(void **state) +{ + char str[] = "Abracadabra!\n"; + + assert_ptr_equal(str, strchr(str, 'A')); + assert_ptr_equal(str + 3, strchr(str, 'a')); + assert_ptr_not_equal(str + 10, strchr(str, 'a')); + + assert_null(strchr(str, 'z')); +} + + +static void test_strrchr(void **state) +{ + char str[] = "Abracadabra!\n"; + + assert_ptr_equal(str + 9, strrchr(str, 'r')); + assert_ptr_not_equal(str + 2, strrchr(str, 'r')); + + assert_null(strrchr(str, 'z')); +} + + +static void test_strncpy(void **state) +{ + int i, n = 7; + char dst[DST_SIZE]; + char src[] = "Hello coreboot\n"; + size_t src_len = __builtin_strlen(src); + + strncpy(dst, src, n); + + assert_int_equal(0, memcmp(dst, src, n)); + + for (i = src_len; i < n; i++) + assert_true(dst[i] == '\0'); +} + +static void test_strcpy(void **state) +{ + char dst[DST_SIZE]; + char src[] = "Hello coreboot\n"; + + /* Make sure that strcpy() sets '\0' by initializing a whole + dst array to fixed, non-'\0' value */ + memset(dst, 'x', DST_SIZE); + + strcpy(dst, src); + + assert_int_equal(0, memcmp(dst, src, __builtin_strlen(src))); + assert_true(dst[__builtin_strlen(dst)] == '\0'); +} + +static void test_strcmp(void **state) +{ + char str[] = "Banana"; + char str2[] = "Bananas"; + + assert_true(strcmp(str, str2) < 0); + assert_int_equal(0, strcmp(str, str)); + assert_true(strcmp(str2, str) > 0); +} + +static void test_strncmp(void **state) +{ + char str[] = "Banana"; + char str2[] = "Bananas"; + + size_t str2_len = __builtin_strlen(str2); + + assert_true(strncmp(str, str2, str2_len) < 0); + assert_int_equal(0, strncmp(str, str2, str2_len - 1)); +} + +static void test_skip_atoi(void **state) +{ + int i; + char *ptr; + + for (i = 0; i < ARRAY_SIZE(str_with_u_val); i++) { + ptr = str_with_u_val[i].str; + assert_int_equal(str_with_u_val[i].value, skip_atoi(&ptr)); + } +} + +static void test_strspn(void **state) +{ + char str[] = "123404567"; + char str2[] = "01234"; + char str3[] = "1234"; + + assert_int_equal(4, strspn(str, str3)); + assert_int_equal(0, strspn(str2, str3)); +} + +static void test_strcspn(void **state) +{ + char str[] = "12340000"; + char str2[] = "00001234"; + char str3[] = "1234"; + + assert_int_equal(0, strcspn(str, str3)); + assert_int_equal(4, strcspn(str2, str3)); +} + +/* Please bear in mind that `atol()` uses `strspn()` internally, so the result + of `test_atol` is dependent on the result of `test_strspn`. */ +static void test_atol(void **state) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(str_with_l_val); i++) + assert_int_equal(str_with_l_val[i].value, atol(str_with_l_val[i].str)); } int main(void) { const struct CMUnitTest tests[] = { - cmocka_unit_test(test_strlen_strings), cmocka_unit_test(test_strdup), + cmocka_unit_test(test_strconcat), + cmocka_unit_test(test_strnlen), + cmocka_unit_test(test_strlen), + cmocka_unit_test(test_strchr), + cmocka_unit_test(test_strrchr), + cmocka_unit_test(test_strncpy), + cmocka_unit_test(test_strcpy), + cmocka_unit_test(test_strcmp), + cmocka_unit_test(test_strncmp), + cmocka_unit_test(test_skip_atoi), + cmocka_unit_test(test_strspn), + cmocka_unit_test(test_strcspn), + cmocka_unit_test(test_atol), }; return cmocka_run_group_tests(tests, NULL, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/42311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ac6a6b2413d9077dc9ea81f638a2b0acd5c8862 Gerrit-Change-Number: 42311 Gerrit-PatchSet: 1 Gerrit-Owner: Anna Karas <aka(a)semihalf.com> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: sb/intel/i82801jx/sata.c: Handle ABAR as a resource
by Angel Pons (Code Review) 06 Jul '20

06 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42643 ) Change subject: sb/intel/i82801jx/sata.c: Handle ABAR as a resource ...................................................................... sb/intel/i82801jx/sata.c: Handle ABAR as a resource Instead of directly reading ABAR without any checking, do like i82801ix and treat it as a resource. This prevents problems if ABAR is not set. Change-Id: I4f888b748204860b0a7e1bf5611f5f3e487e8081 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801jx/sata.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/42643/1 diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 73a7d82..947842a 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -20,9 +20,14 @@ { int i; u32 reg32; + struct resource *res; /* Initialize AHCI memory-mapped space */ - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + res = find_resource(dev, PCI_BASE_ADDRESS_5); + if (!res) + return; + + u8 *abar = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* Set AHCI access mode. -- To view, visit https://review.coreboot.org/c/coreboot/+/42643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f888b748204860b0a7e1bf5611f5f3e487e8081 Gerrit-Change-Number: 42643 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: Documentation/security/vboot: Add device list
by Marcello Sylvester Bauer (Code Review) 06 Jul '20

06 Jul '20

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39200 ) Change subject: Documentation/security/vboot: Add device list ...................................................................... Documentation/security/vboot: Add device list Add a list of VBOOT enabled devices to the documetation. Change-Id: Ibb57d26c5f0cb8efd27ca9a97fd762c25b566f93 Signed-off-by: Marcello Sylvester Bauer <sylv(a)sylv.io> --- M Documentation/security/vboot/index.md 1 file changed, 96 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/39200/1 diff --git a/Documentation/security/vboot/index.md b/Documentation/security/vboot/index.md index 400c2b5..75f34cc 100644 --- a/Documentation/security/vboot/index.md +++ b/Documentation/security/vboot/index.md @@ -342,3 +342,99 @@ any firmware may be placed on the device. However, accessing this screw requires opening the case and voids the system warranty! + +## VBOOT enabled devices + +### AAEON +- UP Square + +### emulation +- qemu-i440fx +- qemu-q35 + +### facebook +- monolith + +### Google +- auron +- beltino +- butterfly +- cheza +- cyan +- daisy +- dragonegg +- drallion +- eve +- fizz +- foster +- gale +- glados +- gru +- hatch +- jecht +- kahlee +- kukui +- link +- mistral +- nyan_big +- nyan_blaze +- nyan +- oak +- parrot +- peach_pit +- poppy +- rambi +- reef +- sarien +- slippy +- smaug +- storm +- stout +- trogdor +- veyron +- veyron_mickey +- veyron_rialto + +### HP +- z220_sff_workstation + +### Intel +- baskingridge +- cannonlake_rvp +- coffeelake_rvp +- emeraldlake2 +- galileo +- glkrvp +- icelake_rvp +- jasperlake_rvp +- kblrvp +- kunimitsu +- strago +- tglrvp +- wtm2 + +### Lenovo +- t400 +- t410 +- t420 +- t420s +- t520 +- x200 +- x201 +- x220 + +### OpenCellular +- elgon + +### Samsung +- lumpy +- stumpy + +### Siemens +- mc_apl2 +- mc_apl4 +- mc_apl5 +- mc_apl6 + +### Supermicro +- x11-lga1151 -- To view, visit https://review.coreboot.org/c/coreboot/+/39200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb57d26c5f0cb8efd27ca9a97fd762c25b566f93 Gerrit-Change-Number: 39200 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylv(a)sylv.io> Gerrit-MessageType: newchange

6 19

Change in coreboot[master]: mb/google/poppy: Drop VARIANT_SPECIFIC_OPTIONS_*
by Angel Pons (Code Review) 06 Jul '20

06 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42144 ) Change subject: mb/google/poppy: Drop VARIANT_SPECIFIC_OPTIONS_* ...................................................................... mb/google/poppy: Drop VARIANT_SPECIFIC_OPTIONS_* Putting variant-specific options in Kconfig.name seems to be what is popular now, so we might as well do the same for Poppy. Change-Id: I8ce3237ac620c26856b6cf3d08293729641dd0b0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/Kconfig.name 2 files changed, 49 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/42144/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 8553821..4298950 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -134,76 +134,6 @@ bool default n -config VARIANT_SPECIFIC_OPTIONS_ATLAS - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_I2C_MAX98373 - select DRIVERS_I2C_DA7219 - select DRIVERS_SPI_ACPI - select DRIVERS_USB_ACPI - select EXCLUDE_NATIVE_SD_INTERFACE - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_SPI_TPM_CR50 - select VARIANT_HAS_CAMERA_ACPI - select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR - -config VARIANT_SPECIFIC_OPTIONS_POPPY - def_bool n - select DRIVERS_I2C_MAX98927 - select NO_FADT_8042 - select VARIANT_HAS_CAMERA_ACPI - select MAINBOARD_HAS_I2C_TPM_CR50 - -config VARIANT_SPECIFIC_OPTIONS_NAMI - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_GENERIC_MAX98357A - select DRIVERS_I2C_DA7219 - select DRIVERS_SPI_ACPI - select EXCLUDE_NATIVE_SD_INTERFACE - select MAINBOARD_HAS_SPI_TPM_CR50 - -config VARIANT_SPECIFIC_OPTIONS_NAUTILUS - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_GENERIC_MAX98357A - select DRIVERS_I2C_DA7219 - select VARIANT_HAS_CAMERA_ACPI - select MAINBOARD_HAS_I2C_TPM_CR50 - -config VARIANT_SPECIFIC_OPTIONS_NOCTURNE - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_I2C_SX9310 if CHROMEOS_WIFI_SAR - select DRIVERS_I2C_MAX98373 - select DRIVERS_I2C_DA7219 - select DRIVERS_SPI_ACPI - select DRIVERS_USB_ACPI - select EXCLUDE_NATIVE_SD_INTERFACE - select MAINBOARD_HAS_SPI_TPM_CR50 - select NO_FADT_8042 - select SYSTEM_TYPE_DETACHABLE - select VARIANT_HAS_CAMERA_ACPI - select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR - -config VARIANT_SPECIFIC_OPTIONS_RAMMUS - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_I2C_MAX98927 - select DRIVERS_I2C_DA7219 - select DRIVERS_SPI_ACPI - select DRIVERS_USB_ACPI - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_SPI_TPM_CR50 - -config VARIANT_SPECIFIC_OPTIONS_SORAKA - def_bool n - select DRIVERS_I2C_MAX98927 - select NO_FADT_8042 - select SYSTEM_TYPE_DETACHABLE - select VARIANT_HAS_CAMERA_ACPI - select MAINBOARD_HAS_I2C_TPM_CR50 - config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/poppy/Kconfig.name b/src/mainboard/google/poppy/Kconfig.name index 9ecdb44..cf8d2c1 100644 --- a/src/mainboard/google/poppy/Kconfig.name +++ b/src/mainboard/google/poppy/Kconfig.name @@ -3,34 +3,76 @@ config BOARD_GOOGLE_ATLAS bool "-> Atlas (Google Pixelbook Go)" select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_ATLAS + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_MAX98373 + select DRIVERS_I2C_DA7219 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EXCLUDE_NATIVE_SD_INTERFACE + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_SPI_TPM_CR50 + select VARIANT_HAS_CAMERA_ACPI + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_POPPY bool "-> Poppy" select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_POPPY + select DRIVERS_I2C_MAX98927 + select NO_FADT_8042 + select VARIANT_HAS_CAMERA_ACPI + select MAINBOARD_HAS_I2C_TPM_CR50 config BOARD_GOOGLE_NAMI bool "-> Nami" select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_NAMI + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 + select DRIVERS_SPI_ACPI + select EXCLUDE_NATIVE_SD_INTERFACE + select MAINBOARD_HAS_SPI_TPM_CR50 config BOARD_GOOGLE_NAUTILUS bool "-> Nautilus (Samsung Chromebook Plus (V2 / LTE))" select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_NAUTILUS + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 + select VARIANT_HAS_CAMERA_ACPI + select MAINBOARD_HAS_I2C_TPM_CR50 config BOARD_GOOGLE_NOCTURNE bool "-> Nocturne (Google Pixel Slate)" select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_NOCTURNE + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_SX9310 if CHROMEOS_WIFI_SAR + select DRIVERS_I2C_MAX98373 + select DRIVERS_I2C_DA7219 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EXCLUDE_NATIVE_SD_INTERFACE + select MAINBOARD_HAS_SPI_TPM_CR50 + select NO_FADT_8042 + select SYSTEM_TYPE_DETACHABLE + select VARIANT_HAS_CAMERA_ACPI + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_RAMMUS bool "-> Rammus (Asus Chromebook C425, Flip C433, Flip C434)" select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_RAMMUS + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_MAX98927 + select DRIVERS_I2C_DA7219 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_SPI_TPM_CR50 config BOARD_GOOGLE_SORAKA bool "-> Soraka (HP Chromebook x2)" select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_SORAKA + select DRIVERS_I2C_MAX98927 + select NO_FADT_8042 + select SYSTEM_TYPE_DETACHABLE + select VARIANT_HAS_CAMERA_ACPI + select MAINBOARD_HAS_I2C_TPM_CR50 -- To view, visit https://review.coreboot.org/c/coreboot/+/42144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ce3237ac620c26856b6cf3d08293729641dd0b0 Gerrit-Change-Number: 42144 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: mb/lenovo/t60: Switch to override tree
by Peter Lemenkov (Code Review) 06 Jul '20

06 Jul '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34779 ) Change subject: mb/lenovo/t60: Switch to override tree ...................................................................... mb/lenovo/t60: Switch to override tree Change-Id: I13c0134b22e2203e6cee6ecafda0dae89e086aff Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t60/Kconfig R src/mainboard/lenovo/t60/devicetree.cb A src/mainboard/lenovo/t60/variants/t60/overridetree.cb D src/mainboard/lenovo/t60/variants/z61t/devicetree.cb A src/mainboard/lenovo/t60/variants/z61t/overridetree.cb 5 files changed, 135 insertions(+), 257 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/34779/1 diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 725528d..ad74f63 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -33,9 +33,9 @@ default "t60" if BOARD_LENOVO_T60 default "z61t" if BOARD_LENOVO_Z61T -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/t60/variants/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb similarity index 93% rename from src/mainboard/lenovo/t60/variants/t60/devicetree.cb rename to src/mainboard/lenovo/t60/devicetree.cb index 9279dcb..70900ea 100644 --- a/src/mainboard/lenovo/t60/variants/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -116,7 +116,6 @@ end register "scr" = "0x0844d070" register "mrr" = "0x01d01002" - end end device pci 1e.2 off end # AC'97 Audio @@ -159,10 +158,6 @@ register "eventb_enable" = "0xff" register "eventc_enable" = "0x3c" register "eventd_enable" = "0xff" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "7" - register "bdc_gpio_lvl" = "0" end chip superio/nsc/pc87382 device pnp 164e.2 on # IR @@ -209,21 +204,12 @@ end end end - device pci 1f.1 on # IDE - subsystemid 0x17aa 0x200c - end device pci 1f.2 on # SATA subsystemid 0x17aa 0x200d end device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x200f chip drivers/i2c/ck505 - register "mask" = "{ 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff }" - register "regs" = "{ 0x2e, 0xf7, 0x3c, - 0x20, 0x01, 0x00, 0x1b, 0x01, - 0x54, 0xff, 0xff, 0x07 }" device i2c 69 on end end # eeprom, 8 virtual devices, same chip diff --git a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb new file mode 100644 index 0000000..eee3a4d --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb @@ -0,0 +1,69 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2015 + end + device pci 01.0 on # PCI-e + device pci 00.0 on # VGA + subsystemid 0x17aa 0x20a4 + end + end + chip southbridge/intel/i82801gx + device pci 1c.0 on # Ethernet + subsystemid 0x17aa 0x2001 + end + device pci 1c.1 on end # WLAN + device pci 1c.2 on end # PCIe port 3 + device pci 1c.3 on end # PCIe port 4 + device pci 1e.0 on # PCI Bridge + chip southbridge/ti/pci1x2x + device pci 00.0 on + subsystemid 0x17aa 0x2012 + end + end + end + device pci 1f.0 on # PCI-LPC bridge + chip ec/lenovo/h8 + register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "7" + register "bdc_gpio_lvl" = "0" + end + chip superio/nsc/pc87384 + device pnp 2e.2 off # Serial Port / IR + irq 0x70 = 4 + end + end + end + device pci 1f.1 on # IDE + subsystemid 0x17aa 0x200c + end + device pci 1f.3 on # SMBUS + chip drivers/i2c/ck505 + register "mask" = "{ 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }" + register "regs" = "{ 0x2e, 0xf7, 0x3c, + 0x20, 0x01, 0x00, 0x1b, 0x01, + 0x54, 0xff, 0xff, 0x07 }" + end + end + end + end +end diff --git a/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb b/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb deleted file mode 100644 index d35c62b..0000000 --- a/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb +++ /dev/null @@ -1,241 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/i945 - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - register "gpu_hotplug" = "0x00000220" - register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "pwm_freq" = "275" - register "gpu_panel_power_up_delay" = "250" - register "gpu_panel_power_backlight_on_delay" = "2380" - register "gpu_panel_power_down_delay" = "250" - register "gpu_panel_power_backlight_off_delay" = "2380" - register "gpu_panel_power_cycle_delay" = "2" - - device cpu_cluster 0 on - chip cpu/intel/socket_m - device lapic 0 on end - end - end - - register "pci_mmio_size" = "768" - - device domain 0 on - device pci 00.0 on # Host bridge - subsystemid 0x17aa 0x2017 - end - - device pci 01.0 on # PEG - device pci 00.0 on end # VGA - end - - device pci 02.0 on # GMA Graphics controller - subsystemid 0x17aa 0x201a - end - device pci 02.1 on # display controller - subsystemid 0x17aa 0x201a - end - - chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi13_routing" = "2" - register "gpi12_routing" = "2" - register "gpi8_routing" = "2" - - register "sata_ports_implemented" = "0x01" - - register "gpe0_en" = "0x11000006" - register "alt_gp_smi_en" = "0x1000" - - register "c4onc3_enable" = "1" - register "c3_latency" = "0x23" - register "docking_supported" = "1" - register "p_cnt_throttling_supported" = "1" - - device pci 1b.0 on # Audio Controller - subsystemid 0x17aa 0x2010 - end - device pci 1c.0 on # PCI Express Port 1 - subsystemid 0x17aa 0x2011 - end - device pci 1c.1 on # PCI Express Port 2 - subsystemid 0x17aa 0x2011 - end - device pci 1c.2 on # PCI Express Port 3 - subsystemid 0x17aa 0x2011 - end - device pci 1c.3 on # PCI Express Port 4 - subsystemid 0x17aa 0x2011 - end - device pci 1c.4 off end # PCIe port 5 - device pci 1c.5 off end # PCIe port 6 - - device pci 1d.0 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.1 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.2 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.3 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.7 on # USB2 EHCI - subsystemid 0x17aa 0x200b - end - device pci 1e.0 on # PCI Bridge - chip southbridge/ti/pci1x2x - device pci 00.0 on - subsystemid 0x17aa 0x2013 - end - register "scr" = "0x0844d070" - register "mrr" = "0x01d01002" - - end - end - device pci 1e.2 off end # AC'97 Audio - device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # PCI-LPC bridge - subsystemid 0x17aa 0x2009 - chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end - - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa6" - register "config1" = "0x05" - register "config2" = "0xa0" - register "config3" = "0x01" - - register "beepmask0" = "0xfe" - register "beepmask1" = "0x96" - register "has_power_management_beeps" = "1" - - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xf4" - register "event5_enable" = "0x3f" - register "event6_enable" = "0x80" - register "event7_enable" = "0x01" - register "event8_enable" = "0x01" - register "event9_enable" = "0xff" - register "eventa_enable" = "0xff" - register "eventb_enable" = "0xff" - register "eventc_enable" = "0x3c" - register "eventd_enable" = "0xff" - - end - chip superio/nsc/pc87382 - device pnp 164e.2 on # IR - io 0x60 = 0x2f8 - end - - device pnp 164e.3 off # Serial Port - io 0x60 = 0x3f8 - end - - device pnp 164e.7 on # GPIO - io 0x60 = 0x1680 - end - - device pnp 164e.19 on # DLPC - io 0x60 = 0x164c - end - end - - chip superio/nsc/pc87384 - device pnp 2e.0 off #FDC - end - - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x3bc - irq 0x70 = 7 - end - - device pnp 2e.2 off # Serial Port / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - - device pnp 2e.3 on # Serial Port - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - - device pnp 2e.7 on # GPIO - io 0x60 = 0x1620 - end - - device pnp 2e.a off # WDT - end - end - end - device pci 1f.2 on # SATA - subsystemid 0x17aa 0x200d - end - device pci 1f.3 on # SMBUS - subsystemid 0x17aa 0x200f - chip drivers/i2c/ck505 - register "mask" = "{ 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff }" - # vendor clockgen setup - register "regs" = "{ 0x6d, 0xff, 0xff, - 0x20, 0x41, 0x7f, 0x18, 0x00 }" - device i2c 69 on end - end - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end - end - end -end diff --git a/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb new file mode 100644 index 0000000..d29df3b --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2017 + end + device pci 01.0 on # PEG + device pci 00.0 on end # VGA + end + chip southbridge/intel/i82801gx + device pci 1c.0 on # PCI Express Port 1 + subsystemid 0x17aa 0x2011 + end + device pci 1c.1 on # PCI Express Port 2 + subsystemid 0x17aa 0x2011 + end + device pci 1c.2 on # PCI Express Port 3 + subsystemid 0x17aa 0x2011 + end + device pci 1c.3 on # PCI Express Port 4 + subsystemid 0x17aa 0x2011 + end + device pci 1e.0 on # PCI Bridge + chip southbridge/ti/pci1x2x + device pci 00.0 on + subsystemid 0x17aa 0x2013 + end + end + end + device pci 1f.0 on # PCI-LPC bridge + chip superio/nsc/pc87384 + device pnp 2e.2 off # Serial Port / IR + irq 0x70 = 3 + end + end + end + device pci 1f.3 on # SMBUS + chip drivers/i2c/ck505 + register "mask" = "{ 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff }" + # vendor clockgen setup + register "regs" = "{ 0x6d, 0xff, 0xff, + 0x20, 0x41, 0x7f, 0x18, 0x00 }" + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/34779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13c0134b22e2203e6cee6ecafda0dae89e086aff Gerrit-Change-Number: 34779 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: soc/intel/xeon_sp/skx: use mem32 address space for PCIe mem64 assignment
by Jonathan Zhang (Code Review) 06 Jul '20

06 Jul '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40577 ) Change subject: soc/intel/xeon_sp/skx: use mem32 address space for PCIe mem64 assignment ...................................................................... soc/intel/xeon_sp/skx: use mem32 address space for PCIe mem64 assignment FSP HOB indicates whether mem32 address space is used for PCIe mem64 allocation or not. If that is the case, split PCIe mem32 address space to support both mem32 assignment and mem64 assignment. TESTED=booted TiogaPass with different PCIe configurations; Verified PCIe devices work in target OS, and resource assignments are correct. Change-Id: Ic7064526bdcba770ff377960045a8aea59e9c0bb --- M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c 3 files changed, 21 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/40577/1 diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 938edf1..c097457 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -444,7 +444,23 @@ xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL); struct iiostack_resource stack_info = {0}; - get_iiostack_info(&stack_info); + uint8_t pci64bit_alloc_flag = get_iiostack_info(&stack_info); + + /* + * pci64bit_alloc_flag is obtained from FSP HOB. It indicates whether + * 32bit address space needs to be split between mem32 and + * mem64 windows. + */ + if (!pci64bit_alloc_flag) { + for (int s = 0; s < stack_info.no_of_stacks; ++s) { + STACK_RES *res = &stack_info.res[s]; + uint64_t length = (res->PciResourceMem32Limit - + res->PciResourceMem32Base + 1) / 2; + res->PciResourceMem64Limit = res->PciResourceMem32Limit; + res->PciResourceMem32Limit = (res->PciResourceMem32Base + length - 1); + res->PciResourceMem64Base = res->PciResourceMem32Limit + 1; + } + } /* assign resources */ assign_stack_resources(&stack_info, dev, NULL); diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 8ba4b29..002fb2b 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -22,7 +22,7 @@ uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset); uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); -void get_iiostack_info(struct iiostack_resource *info); +uint8_t get_iiostack_info(struct iiostack_resource *info); int get_threads_per_package(void); int get_platform_thread_count(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index edacafd..94f2a38 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -364,7 +364,7 @@ return get_cpu_count() * get_threads_per_package(); } -void get_iiostack_info(struct iiostack_resource *info) +uint8_t get_iiostack_info(struct iiostack_resource *info) { size_t hob_size; const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; @@ -386,6 +386,8 @@ memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); } } + + return hob->PlatformData.Pci64BitResourceAllocation; } #if ENV_RAMSTAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/40577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7064526bdcba770ff377960045a8aea59e9c0bb Gerrit-Change-Number: 40577 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: soc/intel/xeon_sp: support for mem64 non-prefetchable BAR assignment
by Jonathan Zhang (Code Review) 06 Jul '20

06 Jul '20

Hello Anjaneya "Reddy" Chagam, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40500 to review the following change. Change subject: soc/intel/xeon_sp: support for mem64 non-prefetchable BAR assignment ...................................................................... soc/intel/xeon_sp: support for mem64 non-prefetchable BAR assignment PCIe End Point device's BARS need to be accomondated in bridge device's resource base/limit config registers. In particular, mem32/mem64 (non-prefetchable) BARs need to be accomondated in bridge device's mem base/limit config registers. This patches fixes the bug that mem64 BAR is not considered when setting bridge device's mem base/limit config registers. Without this patch, TiogaPass without riser card works fine; but on TiogaPass with riser card, the boot fails with MTRR table overflow. While at this, optimized the code, and also taken into account whether FSP HOB indicates that mem32 address space is used for PCIe mem64 allocation or not. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Tested-by: Morgan_Jang(a)wiwynn.com Tested-by: Ryback.Hung(a)quantatw.com Change-Id: I8dd7d94d52ad02f22c8e69b2e5d6dde2a79bc1f7 --- M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c 3 files changed, 114 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/40500/1 diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index be452a0..e3b71cf 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -32,6 +32,74 @@ struct stack_dev_resource *next; }; +typedef enum { + RES_TYPE_IO = 0, + RES_TYPE_NONPREF_MEM, + RES_TYPE_PREF_MEM, + MAX_RES_TYPES +} ResType; + +/* + * This function maps from type 0 end point device BAR resource types + * to type 1 bridge device base/limit resource types. There are 3 base/limt + * resource types: + * RES_TYPE_IO: IO base/limit. IO BAR is mapped to it. + * RES_TYPE_NONPREF_MEM: Memory base/limit (below 4GB address space). mem64 + * and mem32 BARs are mapped to it. + * RES_TYPE_PREF_MEM: Prefetchable base/limit. Prefetchable BARs are mapped + * to it. +*/ +static ResType get_res_type(uint64_t flags) +{ + if (flags & IORESOURCE_IO) + return RES_TYPE_IO; + if (flags & IORESOURCE_MEM) { + if (flags & IORESOURCE_PREFETCH) + return RES_TYPE_PREF_MEM; + else + return RES_TYPE_NONPREF_MEM; + printk(BIOS_ERR, "Invalid resource type 0x%llx\n", flags); + die("Invalid resource type"); +} + +static bool need_assignment(uint64_t flags) +{ + if (flags & (IORESOURCE_STORED | IORESOURCE_RESERVE | IORESOURCE_FIXED | + IORESOURCE_ASSIGNED)) + return false; + return true; +} + +static uint64_t get_resource_base(STACK_RES *stack, ResType res_type) +{ + if (res_type == RES_TYPE_IO) { + assert(stack->PciResourceIoBase <= stack->PciResourceIoLimit); + return stack->PciResourceIoBase; + } + + if (res_type == RES_TYPE_NONPREF_MEM) { + assert(stack->PciResourceMem32Base <= stack->PciResourceMem32Limit); + return stack->PciResourceMem32Base; + } + + assert(stack->PciResourceMem64Base <= stack->PciResourceMem64Limit); + return stack->PciResourceMem64Base; +} + +static void set_resource_base(STACK_RES *stack, ResType res_type, uint64_t base) +{ + if (res_type == RES_TYPE_IO) { + assert(base <= (stack->PciResourceIoLimit + 1)); + stack->PciResourceIoBase = base; + } else if (res_type == RES_TYPE_NONPREF_MEM) { + assert(base <= (stack->PciResourceMem32Limit + 1)); + stack->PciResourceMem32Base = base; + } else { + assert(base <= (stack->PciResourceMem64Limit + 1)); + stack->PciResourceMem64Base = base; + } +} + static void assign_stack_resources(struct iiostack_resource *stack_list, struct device *dev, struct resource *bridge); @@ -176,19 +244,13 @@ } } -static void reserve_dev_resources(STACK_RES *stack, unsigned long res_type, +static void reserve_dev_resources(STACK_RES *stack, ResType res_type, struct stack_dev_resource *res_root, struct resource *bridge) { uint8_t align; uint64_t orig_base, base; - if (res_type & IORESOURCE_IO) - orig_base = stack->PciResourceIoBase; - else if ((res_type & IORESOURCE_MEM) && ((res_type & IORESOURCE_PCI64) || - (!res_root && bridge && (bridge->flags & IORESOURCE_PREFETCH)))) - orig_base = stack->PciResourceMem64Base; - else - orig_base = stack->PciResourceMem32Base; + orig_base = get_resource_base(stack, res_type); align = 0; base = orig_base; @@ -236,14 +298,7 @@ base = bridge->limit + 1; } - /* update new limits */ - if (res_type & IORESOURCE_IO) - stack->PciResourceIoBase = base; - else if ((res_type & IORESOURCE_MEM) && ((res_type & IORESOURCE_PCI64) || - (!res_root && bridge && (bridge->flags & IORESOURCE_PREFETCH)))) - stack->PciResourceMem64Base = base; - else - stack->PciResourceMem32Base = base; + set_resource_base(stack, res_type, base); } static void reclaim_resource_mem(struct stack_dev_resource *res_root) @@ -273,15 +328,14 @@ for (res = dev->resource_list; res; res = res->next) { if (!(res->flags & IORESOURCE_BRIDGE) || - (bridge && ((bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | - IORESOURCE_PREFETCH | IORESOURCE_PCI64)) != - (res->flags & (IORESOURCE_IO | IORESOURCE_MEM | - IORESOURCE_PREFETCH | IORESOURCE_PCI64))))) + (bridge && (get_res_type(bridge->flags) != get_res_type(res->flags)))) continue; assign_stack_resources(stack_list, dev, res); + if (!bridge) continue; + /* for 1st time update, overlading IORESOURCE_ASSIGNED */ if (!(bridge->flags & IORESOURCE_ASSIGNED)) { bridge->base = res->base; @@ -317,36 +371,40 @@ assign_bridge_resources(stack_list, curdev, bridge); /* Pick non-bridged resources for resource allocation for each resource type */ - unsigned long flags[5] = {IORESOURCE_IO, IORESOURCE_MEM, - (IORESOURCE_PCI64|IORESOURCE_MEM), (IORESOURCE_MEM|IORESOURCE_PREFETCH), - (IORESOURCE_PCI64|IORESOURCE_MEM|IORESOURCE_PREFETCH)}; - uint8_t no_res_types = 5; + ResType res_types[MAX_RES_TYPES] = { + RES_TYPE_IO, + RES_TYPE_NONPREF_MEM, + RES_TYPE_PREF_MEM + }; + uint8_t no_res_types = MAX_RES_TYPES; + if (bridge) { - flags[0] = bridge->flags & - (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); - if ((bridge->flags & IORESOURCE_MEM) && - (bridge->flags & IORESOURCE_PREFETCH)) - flags[0] |= IORESOURCE_PCI64; + res_types[0] = get_res_type(bridge->flags); no_res_types = 1; } + printk(BIOS_SPEW, "%s:%d no_res_types: %d\n", __func__, __LINE__, no_res_types); + /* Process each resource type */ for (int rt = 0; rt < no_res_types; ++rt) { struct stack_dev_resource *res_root = NULL; + printk(BIOS_SPEW, "%s:%d rt: %d\n", __func__, __LINE__, rt); for (curdev = bus->children; curdev; curdev = curdev->sibling) { struct resource *res; + printk(BIOS_SPEW, "%s:%d dev: %s\n", __func__, __LINE__, + dev_path(curdev)); if (!curdev->enabled) continue; for (res = curdev->resource_list; res; res = res->next) { - if ((res->flags & IORESOURCE_BRIDGE) || (res->flags & - (IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_ASSIGNED) - ) || ((res->flags & (IORESOURCE_IO | - IORESOURCE_MEM | IORESOURCE_PCI64 - | IORESOURCE_PREFETCH)) - != flags[rt]) || res->size == 0) + printk(BIOS_SPEW, "%s:%d dev: %s, flags: 0x%lx\n", + __func__, __LINE__, + dev_path(curdev), res->flags); + if (res->size == 0 || + get_res_type(res->flags) != res_types[rt] || + (res->flags & IORESOURCE_BRIDGE) || + !need_assignment(res->flags)) continue; else add_res_to_stack(&res_root, curdev, res); @@ -355,51 +413,13 @@ /* Allocate resources and update bridge range */ if (res_root || (bridge && !(bridge->flags & IORESOURCE_ASSIGNED))) { - reserve_dev_resources(stack, flags[rt], res_root, bridge); + reserve_dev_resources(stack, res_types[rt], res_root, bridge); reclaim_resource_mem(res_root); } } } } -static void xeonsp_constrain_pci_resources(struct device *dev, struct resource *res, void *data) -{ - STACK_RES *stack = (STACK_RES *) data; - if (!(res->flags & IORESOURCE_FIXED)) - return; - - uint64_t base, limit; - if (res->flags & IORESOURCE_IO) { - base = stack->PciResourceIoBase; - limit = stack->PciResourceIoLimit; - } else if ((res->flags & IORESOURCE_MEM) && (res->flags & IORESOURCE_PCI64)) { - base = stack->PciResourceMem64Base; - limit = stack->PciResourceMem64Limit; - } else { - base = stack->PciResourceMem32Base; - limit = stack->PciResourceMem32Limit; - } - - if (((res->base + res->size - 1) < base) || (res->base > limit)) /* outside window */ - return; - - if (res->limit > limit) /* resource end is out of limit */ - limit = res->base - 1; - else - base = res->base + res->size; - - if (res->flags & IORESOURCE_IO) { - stack->PciResourceIoBase = base; - stack->PciResourceIoLimit = limit; - } else if ((res->flags & IORESOURCE_MEM) && (res->flags & IORESOURCE_PCI64)) { - stack->PciResourceMem64Base = base; - stack->PciResourceMem64Limit = limit; - } else { - stack->PciResourceMem32Base = base; - stack->PciResourceMem32Limit = limit; - } -} - static void xeonsp_pci_domain_read_resources(struct device *dev) { struct bus *link; @@ -421,18 +441,23 @@ for (link = dev->link_list; link; link = link->next) xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL); - /* - * 1. group devices, resources for each stack - * 2. order resources in descending order of requested resource allocation sizes - */ struct iiostack_resource stack_info = {0}; - get_iiostack_info(&stack_info); + uint8_t pci64bit_alloc_flag = get_iiostack_info(&stack_info); - /* constrain stack window */ - for (link = dev->link_list; link; link = link->next) { - STACK_RES *stack = find_stack_for_bus(&stack_info, link->secondary); - assert(stack != 0); - xeonsp_pci_dev_iterator(link, NULL, xeonsp_constrain_pci_resources, stack); + /* + * pci64bit_alloc_flag is obtained from FSP HOB. It indicates whether + * 32bit address space needs to be split between mem32 and + * mem64 windows. + */ + if (!pci64bit_alloc_flag) { + for (int s = 0; s < stack_info.no_of_stacks; ++s) { + STACK_RES *res = &stack_info.res[s]; + uint64_t length = (res->PciResourceMem32Limit - + res->PciResourceMem32Base + 1) / 2; + res->PciResourceMem64Limit = res->PciResourceMem32Limit; + res->PciResourceMem32Limit = (res->PciResourceMem32Base + length - 1); + res->PciResourceMem64Base = res->PciResourceMem32Limit + 1; + } } /* assign resources */ @@ -491,11 +516,9 @@ #endif }; -/* Attach IIO stack bus numbers with dummy device to PCI DOMAIN 0000 device */ static void attach_iio_stacks(struct device *dev) { struct bus *iiostack_bus; - struct device dummy; struct iiostack_resource stack_info = {0}; DEV_FUNC_ENTER(dev); @@ -518,14 +541,6 @@ iiostack_bus->next = NULL; iiostack_bus->link_num = 1; - dummy.bus = iiostack_bus; - dummy.path.type = DEVICE_PATH_PCI; - dummy.path.pci.devfn = 0; - uint32_t id = pci_read_config32(&dummy, PCI_VENDOR_ID); - if (id == 0xffffffff) - printk(BIOS_WARNING, "IIO Stack device %s not visible\n", - dev_path(&dummy)); - if (dev->link_list == NULL) { dev->link_list = iiostack_bus; } else { diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 8ba4b29..002fb2b 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -22,7 +22,7 @@ uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset); uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); -void get_iiostack_info(struct iiostack_resource *info); +uint8_t get_iiostack_info(struct iiostack_resource *info); int get_threads_per_package(void); int get_platform_thread_count(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index edacafd..94f2a38 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -364,7 +364,7 @@ return get_cpu_count() * get_threads_per_package(); } -void get_iiostack_info(struct iiostack_resource *info) +uint8_t get_iiostack_info(struct iiostack_resource *info) { size_t hob_size; const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; @@ -386,6 +386,8 @@ memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); } } + + return hob->PlatformData.Pci64BitResourceAllocation; } #if ENV_RAMSTAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/40500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dd7d94d52ad02f22c8e69b2e5d6dde2a79bc1f7 Gerrit-Change-Number: 40500 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: mb/google/volteer: Enable HotPlug on PCIe root port for the SD express
by Nick Chen (Code Review) 06 Jul '20

06 Jul '20

Nick Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42897 ) Change subject: mb/google/volteer: Enable HotPlug on PCIe root port for the SD express ...................................................................... mb/google/volteer: Enable HotPlug on PCIe root port for the SD express Enable HotPlug for the PCIe root port that the SD express is on so the OS can re-train the link without needing a reboot if it goes down unexpectedly at runtime. BUG=b:156879564 BRANCH=master TEST=enable HotPlug on Volteer Root Port 7 (SD express) and check in linux that it is identified as a HotPlug capable root port Signed-off-by: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Change-Id: Ie9d427dd297567f06123119a670b5ed2e1f73701 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/42897/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 0c581a5..48ea18f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -88,6 +88,7 @@ register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" + register "PcieRpHotPlug[7]" = "1" # Enable WLAN PCIE 7 using clk 1 register "PcieRpEnable[6]" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/42897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9d427dd297567f06123119a670b5ed2e1f73701 Gerrit-Change-Number: 42897 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: [TESTONLY] devicetree: Remove weak declarations for ops
by Kyösti Mälkki (Code Review) 06 Jul '20

06 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35086 ) Change subject: [TESTONLY] devicetree: Remove weak declarations for ops ...................................................................... [TESTONLY] devicetree: Remove weak declarations for ops Change-Id: Ifb783e2f733d5c65c615e5c1879e3e4c7a83e049 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M util/sconfig/main.c 1 file changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/35086/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 5e3a1d4..586de06 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -936,9 +936,14 @@ chip = tmp; while (chip) { - fprintf(fil, - "__attribute__((weak)) struct chip_operations %s_ops = {};\n", - chip->name_underscore); + if (strstr(chip->name_underscore, "cpu_") == chip->name_underscore) { + fprintf(fil, + "__attribute__((weak)) struct chip_operations %s_ops = {};\n", + chip->name_underscore); + } else { + fprintf(fil, "extern struct chip_operations %s_ops;\n", + chip->name_underscore); + } chip = chip->next; } fprintf(fil, "#endif\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/35086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb783e2f733d5c65c615e5c1879e3e4c7a83e049 Gerrit-Change-Number: 35086 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

9 25

Change in coreboot[master]: mb/asus/p8z77-m_pro: Remove PS/2 keyboard & mouse duplicate
by Keith Hui (Code Review) 06 Jul '20

06 Jul '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41225 ) Change subject: mb/asus/p8z77-m_pro: Remove PS/2 keyboard & mouse duplicate ...................................................................... mb/asus/p8z77-m_pro: Remove PS/2 keyboard & mouse duplicate PS/2 keyboard and mouse devices are declared twice in the DSDT, once in mainboard and once in southbridge. It would appear in Windows Device Manager as two PS/2 keyboards and two PS/2 mouses, all with resource conflicts. This change drops the declaration from mainboard. The issue was discovered when this setup was copied for p8z77-m and then boot tested there. Change-Id: I746a960aaf3992acbcb6a7364641fc4fd12002d2 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8z77-m_pro/dsdt.asl 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/41225/1 diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl index 21b3954..e5446a9 100644 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -12,7 +12,6 @@ ) { #include "acpi/platform.asl" - #include "acpi/superio.asl" #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/common/acpi/platform.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/41225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I746a960aaf3992acbcb6a7364641fc4fd12002d2 Gerrit-Change-Number: 41225 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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