coreboot-gerrit June 2020

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Change in coreboot[master]: drivers/ipmi: Increase BMC waiting message level from DEBUG to INFO
by Paul Menzel (Code Review) 06 Jul '20

06 Jul '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41998 ) Change subject: drivers/ipmi: Increase BMC waiting message level from DEBUG to INFO ...................................................................... drivers/ipmi: Increase BMC waiting message level from DEBUG to INFO As the booting the system can be delayed for a noticeable amount of time, often 60 seconds is the default, this is not a debug message. Chose log level BIOS_INFO. Change-Id: I941792148820c0e1d3fbc80197125fee8cedf09f Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/drivers/ipmi/ipmi_kcs_ops.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/41998/1 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index a5a963e..edc8c18 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -88,7 +88,7 @@ if (conf && conf->wait_for_bmc && conf->bmc_boot_timeout) { struct stopwatch sw; stopwatch_init_msecs_expire(&sw, conf->bmc_boot_timeout * 1000); - printk(BIOS_DEBUG, "IPMI: Waiting for BMC...\n"); + printk(BIOS_INFO, "IPMI: Waiting for BMC...\n"); while (!stopwatch_expired(&sw)) { if (inb(dev->path.pnp.port) != 0xff) -- To view, visit https://review.coreboot.org/c/coreboot/+/41998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I941792148820c0e1d3fbc80197125fee8cedf09f Gerrit-Change-Number: 41998 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/i440bx: Add PMCR register to ACPI code
by Keith Hui (Code Review) 06 Jul '20

06 Jul '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41092 ) Change subject: nb/intel/i440bx: Add PMCR register to ACPI code ...................................................................... nb/intel/i440bx: Add PMCR register to ACPI code p3b-f suspend code is going to use it. Change-Id: Iebc17257e9f690115ec35d94c7c36df39341f0df Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/41092/1 diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl index fa5948f..476be30 100644 --- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl +++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl @@ -10,6 +10,8 @@ { Offset (0x67), // DRB7 DRB7, 8, + Offset (0x7A), // PMCR + PMCR, 8 } Method(TOM1, 0) { /* Multiply by 8MB to get TOM */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc17257e9f690115ec35d94c7c36df39341f0df Gerrit-Change-Number: 41092 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/i440bx: DSDT upgrade
by Keith Hui (Code Review) 06 Jul '20

06 Jul '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41049 ) Change subject: nb/intel/i440bx: DSDT upgrade ...................................................................... nb/intel/i440bx: DSDT upgrade - Separate northbridge DSDT memory device into its own ACPI device, in its own file, to be placed in the \_SB scope. The existing file goes to \_SB.PCI0. - Add PMCR register. It'll come in handy for S3 support. - Add a memory device in ACPI to match ASUS P3B-F vendor DSDT. Memory ranges between TOM and 4GB was declared available for MMIO, now it is between TOM and (4GB - CONFIG_ROM_SIZE). Change-Id: I2c74ef30a9bb48e02154f963b1ca3a4f5f3004df Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A src/northbridge/intel/i440bx/acpi/i440bx.asl M src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl 2 files changed, 66 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/41049/1 diff --git a/src/northbridge/intel/i440bx/acpi/i440bx.asl b/src/northbridge/intel/i440bx/acpi/i440bx.asl new file mode 100644 index 0000000..ae82625 --- /dev/null +++ b/src/northbridge/intel/i440bx/acpi/i440bx.asl @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* i440bx Northbridge resources that sits on \_SB */ + +Device (MEM1) +{ + Name (_HID, EisaId ("PNP0C01") /* System Board */) // _HID: Hardware ID + Method (_CRS, 0) // _CRS: Current Resource Settings + { + Name (BUF1, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00000000, // Address Base + 0x000A0000, // Address Length + ) + Memory32Fixed (ReadOnly, + 0x000F0000, // Address Base + 0x00010000, // Address Length + ) + /* + * Main memory. Length of this block will be adjusted to TOM1, + * TOM1-4GB is declared in sb_pci0_crs.asl for MMIO. + */ + Memory32Fixed (ReadWrite, + 0x00100000, // Address Base + 0x00000000, // Address Length + _Y00) + /* Reserved for firmware flash */ + Memory32Fixed (ReadOnly, + 0xFFFC0000, // Address Base + CONFIG_ROM_SIZE, // Address Length + _Y01) + }) + CreateDWordField (BUF1, _Y00._LEN, EMLN) // _LEN: Length + CreateDWordField (BUF1, _Y01._BAS, FLSB) // _BAS: Base + + /* + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + + /* Top of 4GB */ + ShiftLeft(0x10000000, 4, Local0) + FLSB = Local0 - CONFIG_ROM_SIZE; + EMLN = \_SB.PCI0.NB.TOM1 - 0x100000; + Return (BUF1) /* \_SB_.MEM1._CRS.BUF1 */ + } +} diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl index 856b3e8..476be30 100644 --- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl +++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl @@ -1,22 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -/* i440bx Northbridge */ +/* i440bx Northbridge resources that sits on \_SB.PCI0 */ Device (NB) { Name(_ADR, 0x00000000) OperationRegion(PCIC, PCI_Config, 0x00, 0x100) -} - -Field (NB.PCIC, AnyAcc, NoLock, Preserve) -{ - Offset (0x67), // DRB7 - DRB7, 8, -} - -Method(TOM1, 0) { - /* Multiply by 8MB to get TOM */ - Return(ShiftLeft(DRB7, 23)) + Field (PCIC, ByteAcc, NoLock, Preserve) + { + Offset (0x67), // DRB7 + DRB7, 8, + Offset (0x7A), // PMCR + PMCR, 8 + } + Method(TOM1, 0) { + /* Multiply by 8MB to get TOM */ + Return(ShiftLeft(DRB7, 23)) + } } Method(_CRS, 0) { @@ -61,10 +61,10 @@ * 32bit (0x00000000 - TOM1) will wrap and give the same * result as 64bit (0x100000000 - TOM1). */ - Store(TOM1, MM1B) + MM1B = \_SB.PCI0.NB.TOM1 ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + Local0 -= CONFIG_ROM_SIZE + MM1L = Local0 - MM1B Return(TMP) } -- To view, visit https://review.coreboot.org/c/coreboot/+/41049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c74ef30a9bb48e02154f963b1ca3a4f5f3004df Gerrit-Change-Number: 41049 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82371eb: Don't fill \_SB.PCI0.MBRS
by Keith Hui (Code Review) 06 Jul '20

06 Jul '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41457 ) Change subject: sb/intel/i82371eb: Don't fill \_SB.PCI0.MBRS ...................................................................... sb/intel/i82371eb: Don't fill \_SB.PCI0.MBRS Only two mainboard groups use this southbridge: emulation/qemu-i440fx: Nothing creates or consumes this ACPI path. asus/p2b: It only fills the (mostly static) PIIX4E PM/SMBus I/O resources, which are being declared in DSDT. It is not doing anything useful and causes ACPI errors in Linux kernel[1][2], so it has to stop. [1] https://review.coreboot.org/c/coreboot/+/38601 [2] https://review.coreboot.org/c/coreboot/+/38304 Change-Id: I770047610e02c08191613b57c989b3bc1d464684 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/isa.c 1 file changed, 1 insertion(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/41457/1 diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index efbfb22..83e2789 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -104,21 +104,13 @@ #endif } -#if CONFIG(HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(const struct device *device) -{ - acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - generate_cpu_entries(device); -} -#endif - static const struct device_operations isa_ops = { .read_resources = sb_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, - .acpi_fill_ssdt = southbridge_acpi_fill_ssdt_generator, + .acpi_fill_ssdt = generate_cpu_entries, #endif .init = isa_init, .scan_bus = scan_static_bus, -- To view, visit https://review.coreboot.org/c/coreboot/+/41457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I770047610e02c08191613b57c989b3bc1d464684 Gerrit-Change-Number: 41457 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/intel/dg43gt: Don't redefine MMCONF_BASE_ADDRESS
by Arthur Heymans (Code Review) 06 Jul '20

06 Jul '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35871 ) Change subject: mb/intel/dg43gt: Don't redefine MMCONF_BASE_ADDRESS ...................................................................... mb/intel/dg43gt: Don't redefine MMCONF_BASE_ADDRESS Change-Id: I4d62a04778c8f634b48eee459808f640451b9b48 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/dg43gt/Kconfig 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/35871/1 diff --git a/src/mainboard/intel/dg43gt/Kconfig b/src/mainboard/intel/dg43gt/Kconfig index 341baaa..64bda37 100644 --- a/src/mainboard/intel/dg43gt/Kconfig +++ b/src/mainboard/intel/dg43gt/Kconfig @@ -40,11 +40,6 @@ string default "8086,2e22" - -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - config MAINBOARD_DIR string default "intel/dg43gt" -- To view, visit https://review.coreboot.org/c/coreboot/+/35871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d62a04778c8f634b48eee459808f640451b9b48 Gerrit-Change-Number: 35871 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/voxel: Update gpio settings and overridetree.cb
by David Wu (Code Review) 06 Jul '20

06 Jul '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42731 ) Change subject: mb/google/volteer/var/voxel: Update gpio settings and overridetree.cb ...................................................................... mb/google/volteer/var/voxel: Update gpio settings and overridetree.cb Based on schematic and gpio table of voxel, generate gpio settings and overridetree.cb for terrador. BUG=b:157879197,b:155062762 TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage Verify that the image-voxel.bin is generated successfully. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I49c1923e63d87f11de362fd893905ac2f1137bba --- M src/mainboard/google/volteer/variants/voxel/gpio.c M src/mainboard/google/volteer/variants/voxel/overridetree.cb 2 files changed, 407 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/42731/1 diff --git a/src/mainboard/google/volteer/variants/voxel/gpio.c b/src/mainboard/google/volteer/variants/voxel/gpio.c index a54aeca..750725d 100644 --- a/src/mainboard/google/volteer/variants/voxel/gpio.c +++ b/src/mainboard/google/volteer/variants/voxel/gpio.c @@ -5,19 +5,295 @@ #include <commonlib/helpers.h> /* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + /* B3 : CPU_GP2 ==> PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B5 : ISH_I2C0_CVF_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : ISH_I2C0_CVF_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_NC(GPP_B23, DN_20K), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> EN_USB_CAM_PWR */ + PAD_CFG_GPO(GPP_C1, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, DN_20K), + /* C3 : SML0CLK ==> USB4_SMB_SCL */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : SML0DATA ==> USB4_SMB_SDA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_NC(GPP_C5, DN_20K), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : UART0_CTS# ==> CVF_LPSS_INT_L */ + PAD_CFG_GPI(GPP_C11, NONE, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + PAD_NC(GPP_D0, UP_20K), + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, UP_20K, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, UP_20K, DEEP), + /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */ + PAD_CFG_GPI(GPP_D3, UP_20K, DEEP), + /* D4 : IMGCLKOUT0 ==> CAM_CVF_RST_L */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> PCH_GSPI2_CVF_CS_L */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF7), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), + /* D11 : ISH_SPI_MISO ==> PCH_GSPI2_CVF_MISO */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF7), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_CVF_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* D18 : ISH_GP5 ==> CVF_ACE_ISH_INT_L */ + PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1), + + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */ + PAD_CFG_GPO(GPP_E10, 0, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_E12, 1, DEEP), + /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */ + PAD_CFG_GPO(GPP_E13, 0, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ + PAD_CFG_TERM_GPO(GPP_E17, 1, DN_20K, DEEP), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), + + /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, DN_20K), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_F11, 1, DEEP), + /* F12 : GSXDOUT ==> WWAN_RST_ODL */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F14 : GSXDIN ==> SAR0_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + /* F15 : GSXSRESET# ==> SAR1_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F15, NONE, PLTRST, EDGE_SINGLE), + /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_F17, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, DN_20K), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, DN_20K), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, DN_20K), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SAR1_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SAR1_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H14 : M2_SKT2_CFG2 # ==> WWAN_CONFIG2 */ + PAD_CFG_GPI(GPP_H14, NONE, DEEP), + /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ + PAD_CFG_GPI(GPP_H15, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> PCH_CAM_VSYNC */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + /* H20 : IMGCLKOUT1 ==> EN_MIPI_CAM_PWR */ + PAD_CFG_GPO(GPP_H20, 0, PLTRST), + /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* H23 : IMGCLKOUT4 ==> WWAN_ESIM_SEL_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R4 : HDA_RST# ==> HDA_RST_L */ + PAD_CFG_NF(GPP_R4, DN_20K, DEEP, NF1), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S4 : SNDW2_CLK ==> DMIC_CLK1 */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* S5 : SNDW2_DATA ==> DMIC_DATA1 */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), }; -const struct pad_config *variant_base_gpio_table(size_t *num) +const struct pad_config *variant_override_gpio_table(size_t *num) { - *num = ARRAY_SIZE(gpio_table); - return gpio_table; + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; } /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_E12, 1, DEEP), + + /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_F11, 1, DEEP), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, RSMRST), }; const struct pad_config *variant_early_gpio_table(size_t *num) @@ -25,12 +301,3 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } - -static const struct cros_gpio cros_gpios[] = { -}; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 75422d8..4315edc 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,4 +1,131 @@ chip soc/intel/tigerlake device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + end + end + end # I2C #0 0xA0E8 + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end # I2C1 0xA0E9 + device pci 15.2 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR0 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "0" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C2 0xA0EA + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end # I2C5 0xA0C6 + device pci 1f.2 hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/con + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 on end + end + chip drivers/intel/pmc_mux/con + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end # PMC end end -- To view, visit https://review.coreboot.org/c/coreboot/+/42731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49c1923e63d87f11de362fd893905ac2f1137bba Gerrit-Change-Number: 42731 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: libpayload: cbgfx: Fix add_fractions() overflow reduction
by Julius Werner (Code Review) 06 Jul '20

06 Jul '20

Hello Yu-Ping Wu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42845 to review the following change. Change subject: libpayload: cbgfx: Fix add_fractions() overflow reduction ...................................................................... libpayload: cbgfx: Fix add_fractions() overflow reduction log2(1) is 0 and log2(0) is -1. If we have the int64_t 0xffffffff then log2(0xffffffff >> 31) = log2(0x1) = 0, so the current reduction code would not shift. That's a bad idea, though, since 0xffffffff when interpreted as an int32_t would become a negative number. We need to always shift one more than the current code does to get a safe reduction. This also means we can get rid of another compare/branch since -1 is the smallest result log2() can return, so the shift can no longer go negative now. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ib1eb6364c35c26924804261c02171139cdbd1034 --- M payloads/libpayload/drivers/video/graphics.c 1 file changed, 3 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/42845/1 diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index 81d2bb9..97334af 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -85,13 +85,9 @@ n = (int64_t)f1->n * f2->d + (int64_t)f2->n * f1->d; d = (int64_t)f1->d * f2->d; /* Simplest way to reduce the fraction until fitting in int32_t */ - shift = log2(MAX(ABS(n), ABS(d)) >> 31); - if (shift > 0) { - n >>= shift; - d >>= shift; - } - out->n = n; - out->d = d; + shift = log2(MAX(ABS(n), ABS(d)) >> 31) + 1; + out->n = n >> shift; + out->d = d >> shift; } static void add_scales(struct scale *out, -- To view, visit https://review.coreboot.org/c/coreboot/+/42845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1eb6364c35c26924804261c02171139cdbd1034 Gerrit-Change-Number: 42845 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: soc/amd/common: Fix missing gpio_banks.h include
by Kyösti Mälkki (Code Review) 06 Jul '20

06 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42943 ) Change subject: soc/amd/common: Fix missing gpio_banks.h include ...................................................................... soc/amd/common: Fix missing gpio_banks.h include Change-Id: I2c92280f3bbd80bd7a0d3abfb2fddcef997e144e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/42943/1 diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 4d6d164..e19965b 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -5,6 +5,7 @@ #include <console/console.h> #include <gpio.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/gpio_banks.h> #include <soc/gpio.h> #include <soc/smi.h> #include <assert.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/42943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c92280f3bbd80bd7a0d3abfb2fddcef997e144e Gerrit-Change-Number: 42943 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/amd/picasso/memlayout: Verify bootblock is 16-bit aligned
by Raul Rangel (Code Review) 06 Jul '20

06 Jul '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42885 ) Change subject: soc/amd/picasso/memlayout: Verify bootblock is 16-bit aligned ...................................................................... soc/amd/picasso/memlayout: Verify bootblock is 16-bit aligned The bootblock must be 16-bit aligned for it to boot. BUG=b:159081993 TEST=Made sure trembyle still compiles. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I29c244a3f08df46c5992fe81683b9c0d740ff248 --- M src/soc/amd/picasso/memlayout.ld 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/42885/1 diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/picasso/memlayout.ld index a82e303..6f43ba1 100644 --- a/src/soc/amd/picasso/memlayout.ld +++ b/src/soc/amd/picasso/memlayout.ld @@ -81,6 +81,7 @@ FMAP_CACHE(., FMAP_SIZE) _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock"); + _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned"); BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE) REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/42885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29c244a3f08df46c5992fe81683b9c0d740ff248 Gerrit-Change-Number: 42885 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/Makefile.inc: Drop unused reset.c rule
by Angel Pons (Code Review) 05 Jul '20

05 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42582 ) Change subject: arch/x86/Makefile.inc: Drop unused reset.c rule ...................................................................... arch/x86/Makefile.inc: Drop unused reset.c rule No x86 mainboard has a reset.c file. Change-Id: I167629c7addf485944926d57cf0228606c0f32e5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/x86/Makefile.inc 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/42582/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6297384..f0d7b03 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -288,9 +288,6 @@ ifeq ($(CONFIG_GENERATE_PIRQ_TABLE),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/irq_tables.c endif -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/reset.c),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c -endif ramstage-libs ?= -- To view, visit https://review.coreboot.org/c/coreboot/+/42582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I167629c7addf485944926d57cf0228606c0f32e5 Gerrit-Change-Number: 42582 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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