coreboot-gerrit June 2020

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Change in coreboot[master]: security/vboot: Allow files to go into only RW-A or RW-B region
by Martin Roth (Code Review) 08 Jul '20

08 Jul '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42822 ) Change subject: security/vboot: Allow files to go into only RW-A or RW-B region ...................................................................... security/vboot: Allow files to go into only RW-A or RW-B region The AMD firmware package created by amdfwtool contains pointers to the various binaries and settings. This means that we need different copies of the package in each region. This change allows for the different files in each of the 3 vboot regions. BUG=b:158124527 TEST=Build trembyle; see the correct versions of the files getting built into the RW-A & RW-B regions. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I45ff69dbc2266a67e05597bbe721fbf95cf41777 --- M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc 2 files changed, 26 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/42822/1 diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index ad5b61e..ee8d36a 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -218,6 +218,22 @@ Add a space delimited list of filenames that should only be in the RW sections. +config RWA_REGION_ONLY + string + default "" + depends on VBOOT_SLOTS_RW_AB + help + Add a space-delimited list of filenames that should only be in the + RW-A section. + +config RWB_REGION_ONLY + string + default "" + depends on VBOOT_SLOTS_RW_AB + help + Add a space-delimited list of filenames that should only be in the + RW-B section. + config VBOOT_ENABLE_CBFS_FALLBACK bool default n diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 1e0166e..90b2756 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -165,8 +165,9 @@ endif # Return the regions a specific file should be placed in. The files listed below and the ones -# that are specified in CONFIG_RO_REGION_ONLY are only specified in the RO region. The files -# specified in the CONFIG_RW_REGION_ONLY are only placed in the RW regions. +# that are specified in CONFIG_RO_REGION_ONLY, are only specified in the RO region. The files +# specified in the CONFIG_RW_REGION_ONLY are placed in all RW regions. Files specified +# in CONFIG_RWA_REGION_ONLY or CONFIG_RWB_REGION_ONLY get placed only in those sections. # All other files will be installed into RO and RW regions # Use $(sort) to cut down on extra spaces that would be translated to commas regions-for-file = $(subst $(spc),$(comma),$(sort \ @@ -185,9 +186,15 @@ $(call strip_quotes,$(CONFIG_RO_REGION_ONLY)) \ ,$(1)),COREBOOT,\ $(if $(filter \ + $(call strip_quotes,$(CONFIG_RWA_REGION_ONLY)) \ + ,$(1)), FW_MAIN_A, \ + $(if $(filter \ + $(call strip_quotes,$(CONFIG_RWB_REGION_ONLY)) \ + ,$(1)), FW_MAIN_B, \ + $(if $(filter \ $(call strip_quotes,$(CONFIG_RW_REGION_ONLY)) \ ,$(1)), $(RW_PARTITIONS), $(VBOOT_PARTITIONS) ) \ - ))) + ))))) CONFIG_GBB_HWID := $(call strip_quotes,$(CONFIG_GBB_HWID)) CONFIG_GBB_BMPFV_FILE := $(call strip_quotes,$(CONFIG_GBB_BMPFV_FILE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/42822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45ff69dbc2266a67e05597bbe721fbf95cf41777 Gerrit-Change-Number: 42822 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/amd/picasso:Add psp_verstage components to amdfw binary
by Martin Roth (Code Review) 08 Jul '20

08 Jul '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42380 ) Change subject: soc/amd/picasso:Add psp_verstage components to amdfw binary ...................................................................... soc/amd/picasso:Add psp_verstage components to amdfw binary This adds the psp_verstage userspace application and the location of the shared memory area to the amdfw binary tables. BUG=b:158124527 TEST=Build & boot psp_verstage on trembyle Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I45309b5998e6e442ff37cf1d2adb8ccfa1b6a619 --- M src/soc/amd/picasso/Makefile.inc 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/42380/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 783b9a4..8e14d9d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -239,6 +239,18 @@ PSP_UCODE_FILE2=$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin PSP_UCODE_FILE3=$(FIRMWARE_LOCATE)/UcodePatch_RV2_A0.bin +# type = 0x6B - PSP Shared memory location +ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) +PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) +_PSP_SHAREDMEM_BASE=$(shell grep -ir _vboot2_work $(obj)/cbfs/$(CONFIG_CBFS_PREFIX)/bootblock.map | cut -f1 -d' ') +PSP_SHAREDMEM_BASE=$(shell printf "0x%x" $(_PSP_SHAREDMEM_BASE)) +endif + +# type = 0x52 - PSP Bootloader Userspace Application (verstage) +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +PSP_VERSTAGE_FILE=$(obj)/psp_verstage.bin +endif + # type = 0xb - See #55758 (NDA) for bit definitions. PSP_SOFTFUSE_BITS += 28 @@ -281,6 +293,7 @@ OPT_ABL6_FILE=$(call add_opt_prefix, $(PSP_ABL6_FILE), --abl-image) OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) +OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ @@ -299,6 +312,8 @@ OPT_PSP_PMUD_FILE3=$(call add_opt_prefix, $(PSP_PMUD_FILE3), --subprogram 1 --instance 1 --pmu-data) OPT_PSP_PMUD_FILE4=$(call add_opt_prefix, $(PSP_PMUD_FILE4), --subprogram 1 --instance 4 --pmu-data) OPT_MP2CFG_FILE=$(call add_opt_prefix, $(PSP_MP2CFG_FILE), --mp2-config) +OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) +OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) # Copy prebuild APCBs if they exist $(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin @@ -376,6 +391,7 @@ $(call_strip_quotes, $(PSP_S0I3_FILE)) \ $(call_strip_quotes, $(PSP_IKEK_FILE)) \ $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ + $(PSP_VERSTAGE_FILE) \ $$(PSP_APCB_FILES) \ $(AMDFWTOOL) \ $(obj)/fmap.fmd @@ -430,6 +446,9 @@ $(OPT_SEC_DEBUG_FILE) \ --combo-capable \ $(OPT_TOKEN_UNLOCK) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_PSP_SHAREDMEM_BASE) \ + $(OPT_PSP_SHAREDMEM_SIZE) \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/42380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45309b5998e6e442ff37cf1d2adb8ccfa1b6a619 Gerrit-Change-Number: 42380 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: soc/amd/picasso: Split I2c implementation for psp_verstage
by Martin Roth (Code Review) 08 Jul '20

08 Jul '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42064 ) Change subject: soc/amd/picasso: Split I2c implementation for psp_verstage ...................................................................... soc/amd/picasso: Split I2c implementation for psp_verstage BUG=b:158124527 TEST=Build & boot psp_verstage on trembyle Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I45380e0c61e1bb7a94a96630e5867b7ffca0909c --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/i2c-psp.c A src/soc/amd/picasso/i2c-x86.c M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/i2c.h 5 files changed, 86 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/42064/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index ce0a7a8..250b9d1 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -13,6 +13,7 @@ bootblock-y += bootblock/pre_c.S bootblock-y += bootblock/bootblock.c bootblock-y += southbridge.c +bootblock-y += i2c-x86.c bootblock-y += i2c.c bootblock-$(CONFIG_PICASSO_UART) += uart.c bootblock-y += tsc_freq.c @@ -21,6 +22,7 @@ bootblock-y += config.c romstage-y += i2c.c +romstage-y += i2c-x86.c romstage-y += romstage.c romstage-y += gpio.c romstage-y += pmutil.c @@ -37,10 +39,16 @@ verstage-y += i2c.c verstage-y += pmutil.c verstage-y += config.c +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +verstage-y += i2c-psp.c +else +verstage-y += i2c-x86.c +endif verstage-$(CONFIG_PICASSO_UART) += uart.c verstage-y += tsc_freq.c ramstage-y += i2c.c +ramstage-y += i2c-x86.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += data_fabric_util.c diff --git a/src/soc/amd/picasso/i2c-psp.c b/src/soc/amd/picasso/i2c-psp.c new file mode 100644 index 0000000..c4840cd --- /dev/null +++ b/src/soc/amd/picasso/i2c-psp.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <commonlib/helpers.h> +#include <console/console.h> +#include <drivers/i2c/designware/dw_i2c.h> +#include <soc/i2c.h> +#include <soc/iomap.h> +#include <stdint.h> + +static uintptr_t i2c_bus_address[I2C_MASTER_DEV_COUNT]; + +uintptr_t dw_i2c_base_address(unsigned int bus) +{ + if (bus >= ARRAY_SIZE(i2c_bus_address)) + return 0; + + return i2c_bus_address[bus]; +} +void i2c_set_bar(unsigned int bus, uintptr_t bar) +{ + if (bus >= ARRAY_SIZE(i2c_bus_address)) { + printk(BIOS_ERR, "Error: i2c index out of bounds: %u.", bus); + return; + } + + i2c_bus_address[bus] = bar; +} diff --git a/src/soc/amd/picasso/i2c-x86.c b/src/soc/amd/picasso/i2c-x86.c new file mode 100644 index 0000000..444a430 --- /dev/null +++ b/src/soc/amd/picasso/i2c-x86.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdint.h> +#include <soc/iomap.h> +#include <commonlib/helpers.h> +#include <drivers/i2c/designware/dw_i2c.h> + +/* + * We don't have addresses for I2C0-1. + */ +static const uintptr_t i2c_bus_address[] = { + 0, + 0, + APU_I2C2_BASE, + APU_I2C3_BASE, + APU_I2C4_BASE, /* Can only be used in slave mode */ +}; + +_Static_assert( + ARRAY_SIZE(i2c_bus_address) == I2C_MASTER_DEV_COUNT + I2C_SLAVE_DEV_COUNT, + "ARRAY_SIZE(i2c_bus_address) must equal I2C_MASTER_DEV_COUNT + I2C_SLAVE_DEV_COUNT"); + +uintptr_t dw_i2c_base_address(unsigned int bus) +{ + if (bus >= ARRAY_SIZE(i2c_bus_address)) + return 0; + + return i2c_bus_address[bus]; +} diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 4c8c669..4818455 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -1,40 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/mmio.h> -#include <acpi/acpi.h> #include <console/console.h> #include <delay.h> -#include <device/device.h> #include <drivers/i2c/designware/dw_i2c.h> #include <amdblocks/acpimmio.h> #include <soc/i2c.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> +#include <soc/soc_util.h> #include <soc/southbridge.h> #include "chip.h" /* Global to provide access to chip.c */ const char *i2c_acpi_name(const struct device *dev); -/* - * We don't have addresses for I2C0-1. - */ -static const uintptr_t i2c_bus_address[I2C_MASTER_DEV_COUNT + I2C_SLAVE_DEV_COUNT] = { - 0, - 0, - APU_I2C2_BASE, - APU_I2C3_BASE, - APU_I2C4_BASE, /* Can only be used in slave mode */ -}; - -uintptr_t dw_i2c_base_address(unsigned int bus) -{ - if (bus >= ARRAY_SIZE(i2c_bus_address)) - return 0; - - return i2c_bus_address[bus]; -} - const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { const struct soc_amd_picasso_config *config; @@ -159,7 +137,7 @@ { uint32_t *gpio_ptr; - gpio_ptr = (uint32_t *)gpio_get_address(gpio); + gpio_ptr = gpio_get_address(gpio); save_table->mux_value = iomux_read8(gpio); save_table->control_value = read32(gpio_ptr); } @@ -169,7 +147,7 @@ { uint32_t *gpio_ptr; - gpio_ptr = (uint32_t *)gpio_get_address(gpio); + gpio_ptr = gpio_get_address(gpio); iomux_write8(gpio, save_table->mux_value); iomux_read8(gpio); write32(gpio_ptr, save_table->control_value); @@ -180,13 +158,17 @@ void sb_reset_i2c_slaves(void) { const struct soc_amd_picasso_config *cfg; - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); struct soc_amd_i2c_save save_table[saved_pins_count]; uint8_t i, j, control; + /* I2C0-1 is not accessible from the x86. */ + uint32_t *i2c_gpio_ptr[] = { + NULL, + NULL, + gpio_get_address(I2C2_SCL_PIN), + gpio_get_address(I2C3_SCL_PIN), + }; - if (!dev || !dev->chip_info) - return; - cfg = dev->chip_info; + cfg = config_of_soc(); control = cfg->i2c_scl_reset & GPIO_I2C_MASK; if (control == 0) return; @@ -202,19 +184,19 @@ */ for (j = 0; j < 9; j++) { if (control & GPIO_I2C2_SCL) - write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); + write32(i2c_gpio_ptr[2], GPIO_SCL_LOW); if (control & GPIO_I2C3_SCL) - write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW); + write32(i2c_gpio_ptr[3], GPIO_SCL_LOW); - read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + read32(i2c_gpio_ptr[3]); /* Flush posted write */ udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */ if (control & GPIO_I2C2_SCL) - write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); + write32(i2c_gpio_ptr[2], GPIO_SCL_HIGH); if (control & GPIO_I2C3_SCL) - write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH); + write32(i2c_gpio_ptr[3], GPIO_SCL_HIGH); - read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + read32(i2c_gpio_ptr[3]); /* Flush posted write */ udelay(4); } diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index 58c27a4..f468d74 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -27,4 +27,7 @@ void sb_reset_i2c_slaves(void); +/* Sets the base address for the specific I2C bus. */ +void i2c_set_bar(unsigned int bus, uintptr_t bar); + #endif /* __PICASSO_I2C_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45380e0c61e1bb7a94a96630e5867b7ffca0909c Gerrit-Change-Number: 42064 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 33

Change in coreboot[master]: soc/amd/common: Init interrupts without gevent
by Martin Roth (Code Review) 08 Jul '20

08 Jul '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42809 ) Change subject: soc/amd/common: Init interrupts without gevent ...................................................................... soc/amd/common: Init interrupts without gevent Previously, the code wouldn't initialize any of the special flags, including the interrupt flag, if the pin wasn't associated with a GEVENT. BUG=b:158124527 TEST=Build & boot Trembyle with psp_verstage Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I65efde0a9d347db77c6518c2b988eb29718e778b --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 19 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/42809/1 diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 2ebef8b..a5f7904 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -173,6 +173,17 @@ return gpio; } +static int gevent_missing(uint8_t gpio, int gevent_num, const char *string) +{ + if (gevent_num < 0) { + printk(BIOS_WARNING, "Warning: GPIO pin %d has" + " no associated gevent!\n", gpio); + printk (BIOS_WARNING, "Not programming %s\n", string); + return 1; + } + return 0; +} + __weak void soc_gpio_hook(uint8_t gpio, uint8_t mux) {} void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) @@ -211,14 +222,9 @@ iomux_read8(gpio); /* Flush posted write */ soc_gpio_hook(gpio, mux); - + printk(BIOS_DEBUG, "Setting GPIO: %d\n",gpio); if (control_flags & GPIO_SPECIAL_FLAG) { gevent_num = get_gpio_gevent(gpio, gev_tbl, gev_items); - if (gevent_num < 0) { - printk(BIOS_WARNING, "Warning: GPIO pin %d has" - " no associated gevent!\n", gpio); - continue; - } switch (control_flags & GPIO_SPECIAL_MASK) { case GPIO_DEBOUNCE_FLAG: __gpio_setbits32(gpio, GPIO_DEBOUNCE_MASK, control); @@ -233,6 +239,9 @@ /* Can't set SMI flags from PSP */ if (!can_set_smi_flags) break; + if (gevent_missing(gpio, gevent_num, "SMI Flag")) + break; + __gpio_setbits32(gpio, INT_SCI_SMI_MASK, control); program_smi(control_flags & FLAGS_TRIGGER_MASK, gevent_num); @@ -241,6 +250,8 @@ /* Can't set SCI flags from PSP */ if (!can_set_smi_flags) break; + if (gevent_missing(gpio, gevent_num, "SCI Flag")) + break; __gpio_setbits32(gpio, INT_SCI_SMI_MASK, control); fill_sci_trigger(control_flags & FLAGS_TRIGGER_MASK, gevent_num, @@ -267,7 +278,8 @@ master_switch_set(GPIO_INTERRUPT_EN); /* Set all SCI trigger polarity (high/low) and level (edge/level). */ - set_sci_trigger(&sci_trigger_cfg); + if (can_set_smi_flags) + set_sci_trigger(&sci_trigger_cfg); } int gpio_interrupt_status(gpio_t gpio) -- To view, visit https://review.coreboot.org/c/coreboot/+/42809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65efde0a9d347db77c6518c2b988eb29718e778b Gerrit-Change-Number: 42809 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: ACPI: Add and fill gnvs_ptr for smm_runtime
by Kyösti Mälkki (Code Review) 08 Jul '20

08 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42464 ) Change subject: ACPI: Add and fill gnvs_ptr for smm_runtime ...................................................................... ACPI: Add and fill gnvs_ptr for smm_runtime Change-Id: I823d04a4851437b4267a60886e5ab205bb2e1b10 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/smm/smm_module_loader.c M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 3 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/42464/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 6e9781a..c195979 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> +#include <acpi/acpi_gnvs.h> #include <rmodule.h> #include <cpu/x86/smm.h> #include <commonlib/helpers.h> @@ -261,6 +262,7 @@ stub_params->runtime.smm_size = smm_size; stub_params->runtime.save_state_size = params->per_cpu_save_state_size; stub_params->runtime.num_cpus = params->num_concurrent_stacks; + stub_params->runtime.gnvs_ptr = acpi_get_gnvs(); /* Initialize the APIC id to CPU number table to be 1:1 */ for (i = 0; i < params->num_concurrent_stacks; i++) diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 8086b75..425724d 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -36,6 +36,8 @@ .long 0 num_cpus: .long 0 +gnvs_ptr: +.long 0 /* allows the STM to bring up SMM in 32-bit mode */ start32_offset: .long smm_trampoline32 - _start diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 9c4d227..72b9dd5 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -59,6 +59,7 @@ u32 smm_size; u32 save_state_size; u32 num_cpus; + u32 gnvs_ptr; /* STM's 32bit entry into SMI handler */ u32 start32_offset; /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. -- To view, visit https://review.coreboot.org/c/coreboot/+/42464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I823d04a4851437b4267a60886e5ab205bb2e1b10 Gerrit-Change-Number: 42464 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC
by Bryant Ou (Code Review) 08 Jul '20

08 Jul '20

Bryant Ou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42856 ) Change subject: mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC ...................................................................... mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC BIC use LPCflash utility to flash FW, it use LPC to send the bridge IC image form host to bridge IC, 0x600 ~ 0x6FF is used to send BIC image for in-band update support. TEST=Use LPCflash utility to flash BIC FW on YV3 successfully. [root@localhost lpcflash_101_bin]# ./lpc_update.sh Y3BRDL_D06.bin Update Bridge IC Firmware from LPC Deltalake linux utility ver:1.01 build time: Feb 11 2020 14:30:55 Processing image file: Y3BRDL_D06.bin .. of size 206968 (0x00032878) bytes .. file will be padded to a 64-byte size .. with DEBUG Enabled Generating CRC-32 for file. Done (0x4e3905a3). iBytesRead (0x00007c00). Discovering LPC boot loader. Discovered @ 0x3f8. Configuring LPC boot loader. Configured @ 0x00000600. Sending header block. Sent. Loading firmware into target. Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 16512 bytes ................. Load complete. Update done! Signed-off-by: Bryant Ou <Bryant.Ou.Q(a)gmail.com> Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec --- M src/mainboard/ocp/deltalake/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/42856/1 diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index 031d11a..5682ca7 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -37,6 +37,7 @@ register "coherency_support" = "0" register "ats_support" = "0" + register "gen1_dec" = "0x00FC0601" # BIC in-band update support register "gen2_dec" = "0x000c0ca1" # IPMI KCS device cpu_cluster 0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/42856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec Gerrit-Change-Number: 42856 Gerrit-PatchSet: 1 Gerrit-Owner: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/drawcia: add elan touchscreen
by Chen Wisley (Code Review) 08 Jul '20

08 Jul '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42923 ) Change subject: mb/google/dedede/var/drawcia: add elan touchscreen ...................................................................... mb/google/dedede/var/drawcia: add elan touchscreen BUG=b:155002684 TEST=build drawcia, and check touchscreen can work Change-Id: Ib6a190d2f6fc5132af0e58c6df9919381e88f699 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/42923/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index a92dbdb..3b67510 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -47,5 +47,19 @@ device i2c 15 on end end end #I2C 0 + device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end # I2C 2 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/42923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6a190d2f6fc5132af0e58c6df9919381e88f699 Gerrit-Change-Number: 42923 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/smm: Add support for long mode
by Patrick Rudolph (Code Review) 08 Jul '20

08 Jul '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35681 ) Change subject: cpu/x86/smm: Add support for long mode ...................................................................... cpu/x86/smm: Add support for long mode Enable long mode in SMM handler. x86_32 isn't affected from this change. As the rsm instruction used to leave SMM doesn't restore MSR registers, drop back to protected mode after running the smi_handler and restore IA32_EFER MSR to previous value. Tested on Qemu Q35. Needs tests on real hardware. Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md M src/cpu/x86/smm/smmhandler.S 2 files changed, 95 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/35681/1 diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 462e7e6..b02b879 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -45,6 +45,7 @@ * Add x86_64 exception handlers - *TODO* * Setup page tables for long mode - *DONE* * Add assembly code for long mode - *DONE* +* Add assembly code for SMM - *DONE* * Add assembly code for postcar stage - *TODO* * Add assembly code to return to protected mode - *TODO* * Implement reference code for mainboard `emulation/qemu-q35` - *TODO* diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index a2be7f2..fd8af79 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -20,6 +20,7 @@ */ #include <cpu/x86/lapic_def.h> +#include <cpu/x86/msr.h> /* * +--------------------------------+ 0xaffff @@ -171,15 +172,104 @@ /* Get SMM revision */ movl $0xa8000 + 0x7efc, %ebx /* core 0 address */ subl %ebp, %ebx /* subtract core X offset */ + +#if defined(__x86_64__) + /* Backup IA32_EFER. Preserves ebx. */ + movl $(IA32_EFER), %ecx + rdmsr + movl %eax, ia32efer_backup + + /* Enable long mode if required. Preserves ebx. */ +#include <cpu/x86/64bit/entry64.inc> + + mov (%ebx), %rdi + +#else movl (%ebx), %eax pushl %eax +#endif - /* Call 32bit C handler */ + /* Call C handler */ call smi_handler +#if defined(__x86_64__) + /* + * The only reason to go back to protected mode is that rsm doesn't restore + * MSR registers and IA32_EFER was modified. + * To restore IA32_EFER go back to protected mode. + */ + + /* Ensure cache is clean. */ + invd + + /* Set 32-bit code segment and ss */ + mov $0x08, %rcx + call SetCodeSelector32 + +.code32 + /* Running in 32-bit compatibility mode */ + + /* Use flat data segment */ + movl $0x10, %eax + movl %eax, %ds + movl %eax, %es + movl %eax, %ss + movl %eax, %fs + movl %eax, %gs + + /* Disable paging */ + movl %cr0, %eax + andl $0x7FFFFFFF, %eax + movl %eax, %cr0 + + /* Disable long mode */ + movl $(IA32_EFER), %ecx + rdmsr + andl $(~EFER_LME), %eax + wrmsr + + /* Disable PAE */ + movl %cr4, %eax + andl $(~0x20), %eax + movl %eax, %cr4 + + /* Restore IA32_EFER */ + movl $(IA32_EFER), %ecx + rdmsr + movl ia32efer_backup, %eax + wrmsr +#endif + /* To return, just do rsm. It will "clean up" protected mode */ rsm +#if defined(__x86_64__) +ia32efer_backup: +.long + +.align 8 +.code64 +SetCodeSelector32: + # pop the return address from stack + pop %rbx + + # save rsp because we need to push it after ss + mov %rsp, %rdx + + # use iret to jump to a 32-bit offset in a new code segment + # iret will pop cs:rip, flags, then ss:rsp + mov %ss, %ax # need to push ss.. + push %rax # push ss instuction not valid in x64 mode, + # so use ax + push %rdx # the rsp to load + pushfq # push rflags + push %rcx # cx is code segment selector from caller + push %rbx # push the IP for the next instruction + + # the iretq will behave like ret, with the new cs/ss value loaded + iretq +#endif + .code16 .align 4, 0xff @@ -202,6 +292,9 @@ .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 + /* gdt selector 0x18, flat code segment (64-bit) */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 smm_gdt_end: -- To view, visit https://review.coreboot.org/c/coreboot/+/35681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8 Gerrit-Change-Number: 35681 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Configure IPMI FRB2 watchdog timer via VPD variable...
by Johnny Lin (Code Review) 08 Jul '20

08 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42495 ) Change subject: mb/ocp/deltalake: Configure IPMI FRB2 watchdog timer via VPD variables in romstage ...................................................................... mb/ocp/deltalake: Configure IPMI FRB2 watchdog timer via VPD variables in romstage Add VPD variables for enabling/disabling FRB2 watchdog timer and setting the timer countdown value. By default it would start the timer and trigger hard reset when it's expired. The timer is expected to be stopped later by payload or OS. Tested on OCP Delta Lake. Change-Id: I3ce3bdc24a41d27eb1877655b3148ba02f7f5497 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/ipmi.c M src/mainboard/ocp/deltalake/ipmi.h M src/mainboard/ocp/deltalake/romstage.c 3 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/42495/1 diff --git a/src/mainboard/ocp/deltalake/ipmi.c b/src/mainboard/ocp/deltalake/ipmi.c index dd81bfd..23328f8 100644 --- a/src/mainboard/ocp/deltalake/ipmi.c +++ b/src/mainboard/ocp/deltalake/ipmi.c @@ -3,9 +3,19 @@ #include <console/console.h> #include <drivers/ipmi/ipmi_kcs.h> #include <drivers/ocp/dmi/ocp_dmi.h> +#include <drivers/vpd/vpd.h> +#include <string.h> #include "ipmi.h" +/* VPD variable for enabling/disabling FRB2 timer. */ +#define FRB2_TIMER "FRB2_TIMER" +/* VPD variable for setting FRB2 timer countdown value. */ +#define FRB2_COUNTDOWN "FRB2_COUNTDOWN" +#define VPD_LEN 10 +/* Default countdown is 15 minutes. */ +#define DEFAULT_COUNTDOWN 9000 + enum cb_err ipmi_set_ppin(struct ppin_req *req) { int ret; @@ -70,3 +80,33 @@ return CB_SUCCESS; } + +void init_frb2_wdt(void) +{ + + char val[VPD_LEN]; + /* Enable FRB2 timer by default. */ + u8 enable = 1; + uint16_t countdown; + + if (vpd_get_bool(FRB2_TIMER, VPD_RW, &enable)) { + if (!enable) { + printk(BIOS_DEBUG, "Disable FRB2 timer\n"); + ipmi_stop_bmc_wdt(BMC_KCS_BASE); + return; + } + } + if (enable) { + if (vpd_gets(FRB2_COUNTDOWN, val, VPD_LEN, VPD_RW)) { + countdown = (uint16_t)atol(val); + printk(BIOS_DEBUG, "FRB2 timer countdown set to: %d ms\n", + countdown * 100); + } else { + printk(BIOS_DEBUG, "FRB2 timer use default value: %d ms\n", + DEFAULT_COUNTDOWN * 100); + countdown = DEFAULT_COUNTDOWN; + } + ipmi_init_and_start_bmc_wdt(BMC_KCS_BASE, countdown, + TIMEOUT_HARD_RESET); + } +} diff --git a/src/mainboard/ocp/deltalake/ipmi.h b/src/mainboard/ocp/deltalake/ipmi.h index b167473..52f5db9 100644 --- a/src/mainboard/ocp/deltalake/ipmi.h +++ b/src/mainboard/ocp/deltalake/ipmi.h @@ -26,4 +26,5 @@ enum cb_err ipmi_set_ppin(struct ppin_req *req); enum cb_err ipmi_get_pcie_config(uint8_t *config); enum cb_err ipmi_get_slot_id(uint8_t *slot_id); +void init_frb2_wdt(void); #endif diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 2199494..0f0ee24 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <drivers/ocp/dmi/ocp_dmi.h> #include <fsp/api.h> #include <FspmUpd.h> #include <soc/romstage.h> @@ -104,6 +105,11 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { + /* Since it's the first IPMI command, it's better to run get BMC + selftest result first */ + if (ipmi_kcs_premem_init(BMC_KCS_BASE, 0) == CB_SUCCESS) + init_frb2_wdt(); + mainboard_config_gpios(mupd); mainboard_config_iio(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ce3bdc24a41d27eb1877655b3148ba02f7f5497 Gerrit-Change-Number: 42495 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/drawcia: support elan touchpad
by Chen Wisley (Code Review) 08 Jul '20

08 Jul '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42922 ) Change subject: mb/google/dedede/var/drawcia: support elan touchpad ...................................................................... mb/google/dedede/var/drawcia: support elan touchpad BUG=155002811 TEST=build drawcia, and check touchpad can work. Change-Id: I674236aa6937a0444a85e6b8e2fb9a7925b56f5c --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 8 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/42922/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index ee1abc9..a92dbdb 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -38,15 +38,14 @@ device domain 0 on device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" - register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" - register "generic.wake" = "GPE0_DW0_03" - register "generic.probed" = "1" - register "hid_desc_reg_offset" = "0x20" - device i2c 0x2c on end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end end - end + end #I2C 0 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/42922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I674236aa6937a0444a85e6b8e2fb9a7925b56f5c Gerrit-Change-Number: 42922 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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