coreboot-gerrit June 2020

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Change in coreboot[master]: mb/asrock/b85m_pro4: Expand Super I/O comments
by Angel Pons (Code Review) 08 Jul '20

08 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42399 ) Change subject: mb/asrock/b85m_pro4: Expand Super I/O comments ...................................................................... mb/asrock/b85m_pro4: Expand Super I/O comments Change-Id: I03ca67d748725283ba8382e476d70eb5554f5fb8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/devicetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/42399/1 diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 98a2ee8..0655a32 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -60,18 +60,18 @@ io 0x60 = 0x0378 irq 0x70 = 6 drq 0x74 = 2 - irq 0xf0 = 0x3b + irq 0xf0 = 0x3b # + ECP and EPP 1.9 end device pnp 2e.2 on # UART A io 0x60 = 0x03f8 irq 0x70 = 4 end device pnp 2e.3 off end # UART B, IR - device pnp 2e.5 on # PS/2 KBC + device pnp 2e.5 on # PS/2 Keyboard/Mouse io 0x60 = 0x0060 io 0x62 = 0x0064 - irq 0x70 = 1 # + Keyboard - irq 0x72 = 12 # + Mouse + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) end device pnp 2e.6 off end # CIR device pnp 2e.7 off end # GPIO8 @@ -100,8 +100,8 @@ irq 0xf0 = 0x20 end device pnp 2e.b on # HWM, LED - irq 0x30 = 0xe1 - io 0x60 = 0x0290 + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address end device pnp 2e.d off end # VID device pnp 2e.e off end # CIR wake-up -- To view, visit https://review.coreboot.org/c/coreboot/+/42399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03ca67d748725283ba8382e476d70eb5554f5fb8 Gerrit-Change-Number: 42399 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mb/asrock/b85m_pro4: Correct PS/2 keyboard IRQ
by Angel Pons (Code Review) 08 Jul '20

08 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42398 ) Change subject: mb/asrock/b85m_pro4: Correct PS/2 keyboard IRQ ...................................................................... mb/asrock/b85m_pro4: Correct PS/2 keyboard IRQ No wonder why the PS/2 keyboard was being detected as a mouse! Change-Id: I7080c8210d96b079a5c08d98554ed154141086a6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/42398/1 diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 4bb5380..98a2ee8 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -70,7 +70,7 @@ device pnp 2e.5 on # PS/2 KBC io 0x60 = 0x0060 io 0x62 = 0x0064 - irq 0x70 = 12 # + Keyboard + irq 0x70 = 1 # + Keyboard irq 0x72 = 12 # + Mouse end device pnp 2e.6 off end # CIR -- To view, visit https://review.coreboot.org/c/coreboot/+/42398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7080c8210d96b079a5c08d98554ed154141086a6 Gerrit-Change-Number: 42398 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/asrock/b85m_pro4: Correct HWM related settings
by Angel Pons (Code Review) 08 Jul '20

08 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42131 ) Change subject: mb/asrock/b85m_pro4: Correct HWM related settings ...................................................................... mb/asrock/b85m_pro4: Correct HWM related settings Only one generic decode range is needed for the HWM. Also, pin 3 was selected as fan input, but it is not connected. Use pin 93 instead, because boardviews show that it is wired to the PWR_FAN1 connector. Change-Id: I964a073efbfaa1d79d3483d59ad04fe674bcb275 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/devicetree.cb 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/42131/1 diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index eec921ec..b17d290 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -26,9 +26,7 @@ device pci 03.0 on end # Mini-HD audio chip southbridge/intel/lynxpoint - register "gen1_dec" = "0x000c0291" - register "gen2_dec" = "0x000c0241" - register "gen3_dec" = "0x000c0251" + register "gen1_dec" = "0x000c0291" # Super I/O HWM register "pirqa_routing" = "0x8b" register "pirqb_routing" = "0x80" register "pirqc_routing" = "0x83" @@ -102,7 +100,7 @@ irq 0xf0 = 0x20 end device pnp 2e.b on # HWM, LED - irq 0x30 = 0xe1 + irq 0x30 = 0x61 # + Fan RPM sense pins io 0x60 = 0x0290 end device pnp 2e.d off end # VID -- To view, visit https://review.coreboot.org/c/coreboot/+/42131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I964a073efbfaa1d79d3483d59ad04fe674bcb275 Gerrit-Change-Number: 42131 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: mb/asus/p8z77-v_lx2: Correct Super I/O settings
by Angel Pons (Code Review) 08 Jul '20

08 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42482 ) Change subject: mb/asus/p8z77-v_lx2: Correct Super I/O settings ...................................................................... mb/asus/p8z77-v_lx2: Correct Super I/O settings Compared against superiotool dumps with vendor firmware. Still boots. Change-Id: I49f36b2805e36695d7a53865e87dfafdb897594e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asus/p8z77-v_lx2/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/42482/1 diff --git a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb index 8f51e15..6898c73 100644 --- a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb +++ b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb @@ -68,13 +68,13 @@ device pnp 2e.6 off end # CIR device pnp 2e.7 off end # GPIO6-8 device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 - device pnp 2e.108 on end # GPIO0 - device pnp 2e.9 off end # GPIO1-8 + device pnp 2e.108 off end # GPIO0 + device pnp 2e.9 off end # GPIO8 device pnp 2e.109 off end # GPIO1 - device pnp 2e.209 off end # GPIO2 + device pnp 2e.209 on end # GPIO2 device pnp 2e.309 off end # GPIO3 device pnp 2e.409 off end # GPIO4 - device pnp 2e.509 on end # GPIO5 + device pnp 2e.509 off end # GPIO5 device pnp 2e.609 off end # GPIO6 device pnp 2e.709 off end # GPIO7 device pnp 2e.a on end # ACPI -- To view, visit https://review.coreboot.org/c/coreboot/+/42482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49f36b2805e36695d7a53865e87dfafdb897594e Gerrit-Change-Number: 42482 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/amd/picasso: Update APOB size & base generation
by Martin Roth (Code Review) 08 Jul '20

08 Jul '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42824 ) Change subject: soc/amd/picasso: Update APOB size & base generation ...................................................................... soc/amd/picasso: Update APOB size & base generation Make the APOB size & base generation the same as all the other command line arguments to amdfwtool. BUG=None TEST=Build & boot trembyle Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Id78383d87bc98dd2c859c75585266411c226f950 --- M src/soc/amd/picasso/Makefile.inc 1 file changed, 10 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/42824/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 2f2d02d..35bc1e7 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -257,6 +257,12 @@ PSP_VERSTAGE_FILE=$(obj)/psp_verstage.bin endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK +APOB_NV_SIZE=$(shell printf "0x%x" $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE))) +APOB_NV_BASE=$(shell printf "0x%x" $(call int-add, \ + $(shell cat $(obj)/fmap.fmd | $(_GET_FLASH_BASE)) \ + $(shell cat $(obj)/fmap.fmd | $(_GET_BIOS_REG_BASE)) \ + $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_BASE)))) + # type = 0xb - See #55758 (NDA) for bit definitions. PSP_SOFTFUSE_BITS += 28 @@ -320,6 +326,8 @@ OPT_MP2CFG_FILE=$(call add_opt_prefix, $(PSP_MP2CFG_FILE), --mp2-config) OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) +OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) +OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) AMDFW_COMMON_ARGS=$(OPT_AMD_PUBKEY_FILE) \ $(OPT_PSPBTLDR_FILE) \ @@ -331,12 +339,8 @@ $(OPT_SMUFW2_SUB1_FILE) \ $(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ - --apob-nv-size $(shell printf "0x%x" \ - $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE))) \ - --apob-nv-base $(shell printf "0x%x" $(call int-add, \ - $(shell cat $(obj)/fmap.fmd | $(_GET_FLASH_BASE)) \ - $(shell cat $(obj)/fmap.fmd | $(_GET_BIOS_REG_BASE)) \ - $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_BASE)))) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ $(OPT_PSP_BIOSBIN_FILE) \ $(OPT_PSP_BIOSBIN_DEST) \ $(OPT_PSP_BIOSBIN_SIZE) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/42824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id78383d87bc98dd2c859c75585266411c226f950 Gerrit-Change-Number: 42824 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: arch/x86: Add memmove.c to x86 bootblock
by Martin Roth (Code Review) 08 Jul '20

08 Jul '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42823 ) Change subject: arch/x86: Add memmove.c to x86 bootblock ...................................................................... arch/x86: Add memmove.c to x86 bootblock This was specifically needed for vboot with psp_verstage, but adding it to always be built into bootblock if needed like memcpy & memset makes sense. TEST=Build & boot trembyle BUG=None Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ib724aaf1492edf053a593b42107684b7bf896592 --- M src/arch/x86/Makefile.inc M src/soc/amd/picasso/Makefile.inc 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/42823/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6297384..10f86ca 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -94,6 +94,7 @@ bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S bootblock-y += memcpy.c bootblock-y += memset.c +bootblock-y += memmove.c bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b18ad87..2f2d02d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -23,7 +23,6 @@ bootblock-y += gpio.c bootblock-y += smi_util.c bootblock-y += config.c -bootblock-y += ../../../arch/x86/memmove.c romstage-y += i2c.c romstage-y += i2c-x86.c -- To view, visit https://review.coreboot.org/c/coreboot/+/42823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib724aaf1492edf053a593b42107684b7bf896592 Gerrit-Change-Number: 42823 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/amd/picasso: Halt if workbuf is absent after psp_verstage
by Martin Roth (Code Review) 08 Jul '20

08 Jul '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42810 ) Change subject: soc/amd/picasso: Halt if workbuf is absent after psp_verstage ...................................................................... soc/amd/picasso: Halt if workbuf is absent after psp_verstage Check for the workbuf in bootblock if psp_verstage is being used. BUG=b:158124527 TEST=Build & boot Trembyle with psp_verstage Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I0ec8d2c953bce4c44cde5102d2765e0ab9b5875e --- M src/soc/amd/picasso/bootblock/bootblock.c 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/42810/1 diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index a3935cc..f633767 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -14,6 +14,11 @@ #include <amdblocks/amd_pci_mmconf.h> #include <acpi/acpi.h> +/* vboot includes directory may bot be in include path if vboot is not enabled */ +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) +#include <2struct.h> +#endif + asmlinkage void bootblock_resume_entry(void); /* PSP performs the memory training and setting up DRAM map prior to x86 cores @@ -123,5 +128,17 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) +#include <2struct.h> + unsigned int *workbuf_location = (unsigned int *)CONFIG_PSP_SHAREDMEM_BASE; + if (*workbuf_location != VB2_SHARED_DATA_MAGIC) { + printk(BIOS_ERR,"ERROR: VBOOT workbuf not valid.\n"); + + printk(BIOS_DEBUG,"Signature: %#08x\n",*workbuf_location); + + die("Halting.\n"); + } +#endif + fch_early_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ec8d2c953bce4c44cde5102d2765e0ab9b5875e Gerrit-Change-Number: 42810 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: soc/amd/common: Don't init SMIs or SCIs in psp_verstage
by Martin Roth (Code Review) 08 Jul '20

08 Jul '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42765 ) Change subject: soc/amd/common: Don't init SMIs or SCIs in psp_verstage ...................................................................... soc/amd/common: Don't init SMIs or SCIs in psp_verstage We can't set the SMI or SCI flags in psp verstage, so skip them. TEST=Build BUG=b:154142138 Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I40eb464cde6b233607de1e177702c643ea2b4bb2 --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/42765/1 diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 419f67a..3169e0e 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -180,6 +180,7 @@ int gevent_num; const struct soc_amd_event *gev_tbl; size_t gev_items; + const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && ENV_SEPARATE_VERSTAGE); inter_master = gpio_get_bar() + GPIO_MASTER_SWITCH; direction = 0; @@ -198,7 +199,9 @@ */ mem_read_write32(inter_master, 0, GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN); - soc_get_gpio_event_table(&gev_tbl, &gev_items); + if (can_set_smi_flags) { + soc_get_gpio_event_table(&gev_tbl, &gev_items); + } for (index = 0; index < size; index++) { gpio = gpio_list_ptr[index].gpio; @@ -234,11 +237,19 @@ AMD_GPIO_CONTROL_MASK); break; case GPIO_SMI_FLAG: + /* Can't set SMI flags from PSP */ + if (!can_set_smi_flags) + break; + mem_read_write32(gpio_ptr, control, INT_SCI_SMI_MASK); program_smi(control_flags, gevent_num); break; case GPIO_SCI_FLAG: + /* Can't set SCI flags from PSP */ + if (!can_set_smi_flags) + break; + mem_read_write32(gpio_ptr, control, INT_SCI_SMI_MASK); get_sci_config_bits(control_flags, &bit_edge, -- To view, visit https://review.coreboot.org/c/coreboot/+/42765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40eb464cde6b233607de1e177702c643ea2b4bb2 Gerrit-Change-Number: 42765 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 22

Change in coreboot[master]: lib: Temporarily remove timestamps from psp_verstage
by Martin Roth (Code Review) 08 Jul '20

08 Jul '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42381 ) Change subject: lib: Temporarily remove timestamps from psp_verstage ...................................................................... lib: Temporarily remove timestamps from psp_verstage The timstamp functionality is not yet added for psp_verstage, so temporarily remove it until that's completed. BUG=b:154142138 TEST=Build & Boot psp_verstage on trembyle Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I020619e3615ce92dedbe868104d2bfd83cb7caa9 --- M src/lib/Makefile.inc 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/42381/1 diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e0003bd..72d4f24 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -46,7 +46,11 @@ verstage-y += libgcc.c verstage-y += memcmp.c verstage-y += string.c + +# TODO: Remove this when PSP bootblock timestamps are implemented. +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),) verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c +endif verstage-y += boot_device.c verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c -- To view, visit https://review.coreboot.org/c/coreboot/+/42381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I020619e3615ce92dedbe868104d2bfd83cb7caa9 Gerrit-Change-Number: 42381 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions
by Martin Roth (Code Review) 08 Jul '20

08 Jul '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42225 ) Change subject: soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions ...................................................................... soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions The AMD firmware package created by amdfwtool contains pointers to the various binaries and settings. When these are moved to the RW-A & RW-B regions, the packages need to be recreated for the new addresses. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I0d50968b6ab4b3ab51f8c9bc66c56e141ef728ed --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 148 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/42225/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 3fcf50a..b77b189 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -75,10 +75,6 @@ int default 64 -config VERSTAGE_ADDR - hex - default 0x4000000 - config VGA_BIOS_ID string default "1002,15d8" @@ -399,4 +395,46 @@ Runs verstage on the PSP. Only available on certain Chrome OS branded parts from AMD. +config VERSTAGE_ADDR + hex + depends on VBOOT_STARTS_IN_BOOTBLOCK + default 0x4000000 + +config DISABLE_SPI_FLASH_ROM_SHARING + def_bool n + help + Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin + which indicates a board level ROM transaction request. This + removes arbitration with board and assumes the chipset controls + the SPI flash bus entirely. + +if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + +config RWA_REGION_ONLY + string + default "apu/amdfw_a" + help + Add a space-delimited list of filenames that should only be in the + RW-A section. + +config RWB_REGION_ONLY + string + default "apu/amdfw_b" + help + Add a space-delimited list of filenames that should only be in the + RW-B section. + +#TODO: Change this to get the positions from fmap +config PICASSO_FW_A_POSITION + hex + help + Location of the AMD firmware in the RW_A region + +config PICASSO_FW_B_POSITION + hex + help + Location of the AMD firmware in the RW_B region + +endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + endif # SOC_AMD_PICASSO diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b8c865f..d80713c 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -232,6 +232,19 @@ PSP_UCODE_FILE2=$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin PSP_UCODE_FILE3=$(FIRMWARE_LOCATE)/UcodePatch_RV2_A0.bin +# type = 0x6B - PSP Shared memory location +ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) +# Place SHAREDMEM immediately below the 4KB boundary below the reset vector. +PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) +_PSP_SHAREDMEM_BASE=$(call int-subtract, $(call int-subtract, $(call int-add, $(CONFIG_X86_RESET_VECTOR) + 0x10) $(PSP_SHAREDMEM_SIZE)) 0x1000) +PSP_SHAREDMEM_BASE=$(shell printf "0x%x" $(_PSP_SHAREDMEM_BASE)) +endif + +# type = 0x52 - PSP Bootloader Userspace Application (verstage) +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +PSP_VERSTAGE_FILE=$(obj)/psp_verstage.bin +endif + # type = 0xb - See #55758 (NDA) for bit definitions. PSP_SOFTFUSE_BITS += 28 @@ -274,6 +287,7 @@ OPT_ABL6_FILE=$(call add_opt_prefix, $(PSP_ABL6_FILE), --abl-image) OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) +OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ @@ -295,6 +309,64 @@ OPT_PSP_UCODE_FILE2=$(call add_opt_prefix, $(PSP_UCODE_FILE2), --instance 1 --ucode) OPT_PSP_UCODE_FILE3=$(call add_opt_prefix, $(PSP_UCODE_FILE3), --instance 2 --ucode) OPT_MP2CFG_FILE=$(call add_opt_prefix, $(PSP_MP2CFG_FILE), --mp2-config) +OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) +OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) + +AMDFW_COMMON_ARGS=$(OPT_AMD_PUBKEY_FILE) \ + $(OPT_PSPBTLDR_FILE) \ + $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSP_SEC_DBG_KEY_FILE) \ + $(OPT_SMUFW1_SUB2_FILE) \ + $(OPT_SMUFW2_SUB2_FILE) \ + $(OPT_SMUFW1_SUB1_FILE) \ + $(OPT_SMUFW2_SUB1_FILE) \ + $(OPT_PSP_APCB_FILES) \ + $(OPT_APOB_ADDR) \ + --apob-nv-size $(shell printf "0x%x" \ + $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE))) \ + --apob-nv-base $(shell printf "0x%x" $(call int-add, \ + $(shell cat $(obj)/fmap.fmd | $(_GET_FLASH_BASE)) \ + $(shell cat $(obj)/fmap.fmd | $(_GET_BIOS_REG_BASE)) \ + $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_BASE)))) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + $(OPT_PSP_PMUI_FILE1) \ + $(OPT_PSP_PMUI_FILE2) \ + $(OPT_PSP_PMUI_FILE3) \ + $(OPT_PSP_PMUI_FILE4) \ + $(OPT_PSP_PMUD_FILE1) \ + $(OPT_PSP_PMUD_FILE2) \ + $(OPT_PSP_PMUD_FILE3) \ + $(OPT_PSP_PMUD_FILE4) \ + $(OPT_PSP_UCODE_FILE1) \ + $(OPT_PSP_UCODE_FILE2) \ + $(OPT_PSP_UCODE_FILE3) \ + $(OPT_MP2CFG_FILE) \ + $(OPT_ABL0_FILE) \ + $(OPT_ABL1_FILE) \ + $(OPT_ABL2_FILE) \ + $(OPT_ABL3_FILE) \ + $(OPT_ABL4_FILE) \ + $(OPT_ABL5_FILE) \ + $(OPT_ABL6_FILE) \ + $(OPT_ABL7_FILE) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_SECG1_FILE) \ + $(OPT_SECG2_FILE) \ + $(OPT_MP2FW1_FILE) \ + $(OPT_MP2FW2_FILE) \ + $(OPT_DRIVERS_FILE) \ + $(OPT_PSP_S0I3_FILE) \ + $(OPT_IKEK_FILE) \ + $(OPT_SEC_DEBUG_FILE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_PSP_SHAREDMEM_BASE) \ + $(OPT_PSP_SHAREDMEM_SIZE) \ + --combo-capable \ + $(OPT_TOKEN_UNLOCK) \ + --flashsize $(CONFIG_ROM_SIZE) # Copy prebuild APCBs if they exist $(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin @@ -375,66 +447,16 @@ $(call_strip_quotes, $(PSP_S0I3_FILE)) \ $(call_strip_quotes, $(PSP_IKEK_FILE)) \ $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ + $(PSP_VERSTAGE_FILE) \ $$(PSP_APCB_FILES) \ $(AMDFWTOOL) \ $(obj)/fmap.fmd rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_PSPSCUREOS_FILE) \ - $(OPT_PSP_SEC_DBG_KEY_FILE) \ - $(OPT_SMUFW1_SUB2_FILE) \ - $(OPT_SMUFW2_SUB2_FILE) \ - $(OPT_SMUFW1_SUB1_FILE) \ - $(OPT_SMUFW2_SUB1_FILE) \ - $(OPT_PSP_APCB_FILES) \ - $(OPT_APOB_ADDR) \ - --apob-nv-size $(shell printf "0x%x" \ - $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE))) \ - --apob-nv-base $(shell printf "0x%x" $(call int-add, \ - $(shell cat $(obj)/fmap.fmd | $(_GET_FLASH_BASE)) \ - $(shell cat $(obj)/fmap.fmd | $(_GET_BIOS_REG_BASE)) \ - $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_BASE)))) \ - $(OPT_PSP_BIOSBIN_FILE) \ - $(OPT_PSP_BIOSBIN_DEST) \ - $(OPT_PSP_BIOSBIN_SIZE) \ - $(OPT_PSP_SOFTFUSE) \ - $(OPT_PSP_PMUI_FILE1) \ - $(OPT_PSP_PMUI_FILE2) \ - $(OPT_PSP_PMUI_FILE3) \ - $(OPT_PSP_PMUI_FILE4) \ - $(OPT_PSP_PMUD_FILE1) \ - $(OPT_PSP_PMUD_FILE2) \ - $(OPT_PSP_PMUD_FILE3) \ - $(OPT_PSP_PMUD_FILE4) \ - $(OPT_PSP_UCODE_FILE1) \ - $(OPT_PSP_UCODE_FILE2) \ - $(OPT_PSP_UCODE_FILE3) \ - $(OPT_MP2CFG_FILE) \ - $(OPT_ABL0_FILE) \ - $(OPT_ABL1_FILE) \ - $(OPT_ABL2_FILE) \ - $(OPT_ABL3_FILE) \ - $(OPT_ABL4_FILE) \ - $(OPT_ABL5_FILE) \ - $(OPT_ABL6_FILE) \ - $(OPT_ABL7_FILE) \ - $(OPT_WHITELIST_FILE) \ - $(OPT_SECG1_FILE) \ - $(OPT_SECG2_FILE) \ - $(OPT_MP2FW1_FILE) \ - $(OPT_MP2FW2_FILE) \ - $(OPT_DRIVERS_FILE) \ - $(OPT_PSP_S0I3_FILE) \ - $(OPT_IKEK_FILE) \ - $(OPT_SEC_DEBUG_FILE) \ - --combo-capable \ - $(OPT_TOKEN_UNLOCK) \ - --flashsize $(CONFIG_ROM_SIZE) \ - --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ - --output $@ + $(AMDFW_COMMON_ARGS) \ + --location $(shell printf "%#x" $(PICASSO_FWM_POSITION)) \ + --output $@ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @@ -442,6 +464,24 @@ $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ --maxsize $(PSP_BIOSBIN_SIZE) +$(obj)/amdfw_a.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + --location $(shell printf "%#x" $(CONFIG_PICASSO_FW_A_POSITION)) \ + --anywhere \ + --output $@ + +$(obj)/amdfw_b.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + --location $(shell printf "%#x" $(CONFIG_PICASSO_FW_B_POSITION)) \ + --anywhere \ + --output $@ + ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) PHONY+=add_amdfw INTERMEDIATE+=add_amdfw @@ -467,6 +507,18 @@ apu/amdfw-position := $(PICASSO_FWM_POSITION) apu/amdfw-type := raw +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +cbfs-files-y += apu/amdfw_a +apu/amdfw_a-file := $(obj)/amdfw_a.rom +apu/amdfw_a-position := $(call strip_quotes, $(CONFIG_PICASSO_FW_A_POSITION)) +apu/amdfw_a-type := raw + +cbfs-files-y += apu/amdfw_b +apu/amdfw_b-file := $(obj)/amdfw_b.rom +apu/amdfw_b-position := $(call strip_quotes, $(CONFIG_PICASSO_FW_B_POSITION)) +apu/amdfw_b-type := raw +endif + endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) $(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) -- To view, visit https://review.coreboot.org/c/coreboot/+/42225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d50968b6ab4b3ab51f8c9bc66c56e141ef728ed Gerrit-Change-Number: 42225 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2020