coreboot-gerrit June 2020

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Change in coreboot[master]: src: Remove unused 'include <types.h>'
by HAOUAS Elyes (Code Review) 14 Jul '20

14 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41677 ) Change subject: src: Remove unused 'include <types.h>' ...................................................................... src: Remove unused 'include <types.h>' Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/include/armv7.h M src/cpu/intel/model_206ax/common.c M src/drivers/generic/bayhub/bh720.h M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c M src/drivers/lenovo/hybrid_graphics/romstage.c M src/drivers/uart/util.c M src/include/timer.h M src/mainboard/emulation/qemu-i440fx/acpi_tables.c M src/mainboard/getac/p470/acpi_tables.c M src/mainboard/google/auron/ec.c M src/mainboard/google/beltino/acpi_tables.c M src/mainboard/google/beltino/mainboard.c M src/mainboard/google/beltino/variants/mccloud/led.c M src/mainboard/google/beltino/variants/monroe/led.c M src/mainboard/google/beltino/variants/panther/led.c M src/mainboard/google/beltino/variants/tricky/led.c M src/mainboard/google/beltino/variants/zako/led.c M src/mainboard/google/cyan/ec.c M src/mainboard/google/daisy/romstage.c M src/mainboard/google/gale/cdp.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/jecht/led.c M src/mainboard/google/link/ec.c M src/mainboard/google/parrot/acpi_tables.c M src/mainboard/google/rambi/acpi_tables.c M src/mainboard/google/rambi/ec.c M src/mainboard/google/slippy/acpi_tables.c M src/mainboard/google/slippy/ec.c M src/mainboard/google/slippy/mainboard.c M src/mainboard/google/stout/acpi_tables.c M src/mainboard/intel/baskingridge/acpi_tables.c M src/mainboard/intel/baskingridge/mainboard.c M src/mainboard/intel/emeraldlake2/acpi_tables.c M src/mainboard/intel/emeraldlake2/ec.c M src/mainboard/intel/emeraldlake2/mainboard.c M src/mainboard/intel/harcuvar/acpi_tables.c M src/mainboard/intel/strago/acpi_tables.c M src/mainboard/intel/strago/ec.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/intel/wtm2/mainboard.c M src/mainboard/samsung/lumpy/acpi_tables.c M src/mainboard/samsung/lumpy/ec.c M src/mainboard/samsung/stumpy/acpi_tables.c M src/mainboard/scaleway/tagada/acpi_tables.c M src/mainboard/ti/beaglebone/bootblock.c M src/northbridge/intel/sandybridge/common.c M src/security/memory/memory.c M src/soc/amd/picasso/include/soc/soc_util.h M src/soc/cavium/cn81xx/include/soc/twsi.h M src/soc/intel/common/vbt.h M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/qualcomm/ipq806x/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/sc7180/uart_bitbang.c M src/soc/qualcomm/sdm845/uart_bitbang.c M src/southbridge/intel/lynxpoint/acpi.c 57 files changed, 0 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/41677/1 diff --git a/src/arch/arm/include/armv7.h b/src/arch/arm/include/armv7.h index 1223d9b..0d7a8cf 100644 --- a/src/arch/arm/include/armv7.h +++ b/src/arch/arm/include/armv7.h @@ -2,7 +2,6 @@ #ifndef ARMV7_H #define ARMV7_H -#include <types.h> /* Cortex-A9 revisions */ #define MIDR_CORTEX_A9_R0P1 0x410FC091 diff --git a/src/cpu/intel/model_206ax/common.c b/src/cpu/intel/model_206ax/common.c index 216160b..a881314 100644 --- a/src/cpu/intel/model_206ax/common.c +++ b/src/cpu/intel/model_206ax/common.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <cpu/x86/msr.h> #include "model_206ax.h" diff --git a/src/drivers/generic/bayhub/bh720.h b/src/drivers/generic/bayhub/bh720.h index d8c3196..ac07f8b 100644 --- a/src/drivers/generic/bayhub/bh720.h +++ b/src/drivers/generic/bayhub/bh720.h @@ -2,7 +2,6 @@ /* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge */ -#include <types.h> enum { BH720_PROTECT = 0xd0, diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index 22b825b..ce6aa86 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <device/device.h> #include <device/smbus.h> #include <console/console.h> diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c index ec9f995..8f0e7bd 100644 --- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <option.h> #include <device/device.h> diff --git a/src/drivers/lenovo/hybrid_graphics/romstage.c b/src/drivers/lenovo/hybrid_graphics/romstage.c index 3d14646..e62215d 100644 --- a/src/drivers/lenovo/hybrid_graphics/romstage.c +++ b/src/drivers/lenovo/hybrid_graphics/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <option.h> #include <device/device.h> diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index 1ac994e..b761dd7 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/uart.h> -#include <types.h> #include <timer.h> /* Calculate divisor. Do not floor but round to nearest integer. */ diff --git a/src/include/timer.h b/src/include/timer.h index 9b7a05e..d2c67f64f 100644 --- a/src/include/timer.h +++ b/src/include/timer.h @@ -2,7 +2,6 @@ #ifndef TIMER_H #define TIMER_H -#include <types.h> #define NSECS_PER_SEC 1000000000 #define USECS_PER_SEC 1000000 diff --git a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c index c78de52..1f10837 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index 3abf8aa..e36c70b 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <string.h> #include <console/console.h> #include <acpi/acpi.h> diff --git a/src/mainboard/google/auron/ec.c b/src/mainboard/google/auron/ec.c index 8448358..5be20c0 100644 --- a/src/mainboard/google/auron/ec.c +++ b/src/mainboard/google/auron/ec.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include "ec.h" diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index d2f7f45..3275fd2 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index e343d68..6d9d500 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <arch/io.h> #include <device/device.h> diff --git a/src/mainboard/google/beltino/variants/mccloud/led.c b/src/mainboard/google/beltino/variants/mccloud/led.c index 2ba84d9..da5002f 100644 --- a/src/mainboard/google/beltino/variants/mccloud/led.c +++ b/src/mainboard/google/beltino/variants/mccloud/led.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <superio/ite/it8772f/it8772f.h> #include "../../onboard.h" diff --git a/src/mainboard/google/beltino/variants/monroe/led.c b/src/mainboard/google/beltino/variants/monroe/led.c index c67632f..5f6932d 100644 --- a/src/mainboard/google/beltino/variants/monroe/led.c +++ b/src/mainboard/google/beltino/variants/monroe/led.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include "../../onboard.h" void set_power_led(int state) diff --git a/src/mainboard/google/beltino/variants/panther/led.c b/src/mainboard/google/beltino/variants/panther/led.c index 54e4458..3fe93b4 100644 --- a/src/mainboard/google/beltino/variants/panther/led.c +++ b/src/mainboard/google/beltino/variants/panther/led.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include "../../onboard.h" void set_power_led(int state) diff --git a/src/mainboard/google/beltino/variants/tricky/led.c b/src/mainboard/google/beltino/variants/tricky/led.c index 475e4b6..49d7918 100644 --- a/src/mainboard/google/beltino/variants/tricky/led.c +++ b/src/mainboard/google/beltino/variants/tricky/led.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <superio/ite/it8772f/it8772f.h> #include "../../onboard.h" diff --git a/src/mainboard/google/beltino/variants/zako/led.c b/src/mainboard/google/beltino/variants/zako/led.c index 16c0d9f..0c83657 100644 --- a/src/mainboard/google/beltino/variants/zako/led.c +++ b/src/mainboard/google/beltino/variants/zako/led.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include "../../onboard.h" void set_power_led(int state) diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c index f69d4c4..3862434 100644 --- a/src/mainboard/google/cyan/ec.c +++ b/src/mainboard/google/cyan/ec.c @@ -5,7 +5,6 @@ #include <ec/google/chromeec/ec.h> #include "ec.h" #include <vendorcode/google/chromeos/chromeos.h> -#include <types.h> void mainboard_ec_init(void) { diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c index c70716a..b8105fd 100644 --- a/src/mainboard/google/daisy/romstage.c +++ b/src/mainboard/google/daisy/romstage.c @@ -18,7 +18,6 @@ #include <soc/trustzone.h> #include <soc/wakeup.h> #include <timestamp.h> -#include <types.h> #include "exynos5250.h" diff --git a/src/mainboard/google/gale/cdp.c b/src/mainboard/google/gale/cdp.c index 1ac44fa..ab7bc8c 100644 --- a/src/mainboard/google/gale/cdp.c +++ b/src/mainboard/google/gale/cdp.c @@ -4,7 +4,6 @@ #include <soc/cdp.h> #include <soc/ebi2.h> #include <soc/clock.h> -#include <types.h> #include <boardid.h> void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count) diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 3e8cc20..9170f0b 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <arch/ioapic.h> #include <device/device.h> diff --git a/src/mainboard/google/jecht/led.c b/src/mainboard/google/jecht/led.c index 054f0aa..8a6a304 100644 --- a/src/mainboard/google/jecht/led.c +++ b/src/mainboard/google/jecht/led.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <superio/ite/it8772f/it8772f.h> #include "onboard.h" diff --git a/src/mainboard/google/link/ec.c b/src/mainboard/google/link/ec.c index e3f68e1..6f87f1d 100644 --- a/src/mainboard/google/link/ec.c +++ b/src/mainboard/google/link/ec.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include "ec.h" diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 62722ec..203f29f 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index c4c1788..65e6af4 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <arch/ioapic.h> #include <device/device.h> diff --git a/src/mainboard/google/rambi/ec.c b/src/mainboard/google/rambi/ec.c index 0d7d110..7588eff 100644 --- a/src/mainboard/google/rambi/ec.c +++ b/src/mainboard/google/rambi/ec.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include "ec.h" diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index ba55647..338aa94 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c index b646b9c..5761a7c 100644 --- a/src/mainboard/google/slippy/ec.c +++ b/src/mainboard/google/slippy/ec.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include "ec.h" diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 9cab3a1..141a869 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <smbios.h> #include <device/device.h> #include <drivers/intel/gma/int15.h> diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 08bd4cd..f477080 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index 24edfea..ebbaf41 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 67299fd..ef59110 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <device/device.h> #include <drivers/intel/gma/int15.h> #include <acpi/acpi.h> diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 36d0d66..0312f60 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/mainboard/intel/emeraldlake2/ec.c b/src/mainboard/intel/emeraldlake2/ec.c index f6819c7..5c088a3 100644 --- a/src/mainboard/intel/emeraldlake2/ec.c +++ b/src/mainboard/intel/emeraldlake2/ec.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <types.h> #include <console/console.h> #include <ec/smsc/mec1308/ec.h> #include "ec.h" diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index c97face..6291d60 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <device/device.h> #include <drivers/intel/gma/int15.h> #include <acpi/acpi.h> diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index 1351e62..3b4f14a 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index e97d9c1..b1b3ccd 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -6,7 +6,6 @@ #include <soc/acpi.h> #include <soc/iomap.h> #include <soc/nvs.h> -#include <types.h> #include <boardid.h> #include "onboard.h" diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c index f69d4c4..3862434 100644 --- a/src/mainboard/intel/strago/ec.c +++ b/src/mainboard/intel/strago/ec.c @@ -5,7 +5,6 @@ #include <ec/google/chromeec/ec.h> #include "ec.h" #include <vendorcode/google/chromeos/chromeos.h> -#include <types.h> void mainboard_ec_init(void) { diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 87cb965..edc5a8b 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <arch/ioapic.h> #include <device/device.h> diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index 180a362..b271d53 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <device/device.h> #include <drivers/intel/gma/int15.h> #include <acpi/acpi.h> diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index aafbdb6..9d27b1c 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <ec/acpi/ec.h> diff --git a/src/mainboard/samsung/lumpy/ec.c b/src/mainboard/samsung/lumpy/ec.c index a53d033..7aac479 100644 --- a/src/mainboard/samsung/lumpy/ec.c +++ b/src/mainboard/samsung/lumpy/ec.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <types.h> #include <console/console.h> #include <ec/smsc/mec1308/ec.h> #include "ec.h" diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index b66e4dd..b9730c9 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index 1351e62..3b4f14a 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index 7e69a3d..6e9538b 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/mmio.h> -#include <types.h> #include <bootblock_common.h> #include <console/uart.h> #include <cpu/ti/am335x/clock.h> diff --git a/src/northbridge/intel/sandybridge/common.c b/src/northbridge/intel/sandybridge/common.c index d64a740..b27911d 100644 --- a/src/northbridge/intel/sandybridge/common.c +++ b/src/northbridge/intel/sandybridge/common.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <console/console.h> #include <device/device.h> #include "sandybridge.h" diff --git a/src/security/memory/memory.c b/src/security/memory/memory.c index 664e7c1..7b9b2ff 100644 --- a/src/security/memory/memory.c +++ b/src/security/memory/memory.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include "memory.h" /** diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h index 6515761..e89bcda 100644 --- a/src/soc/amd/picasso/include/soc/soc_util.h +++ b/src/soc/amd/picasso/include/soc/soc_util.h @@ -3,7 +3,6 @@ #ifndef __PICASSO_SOC_UTIL_H__ #define __PICASSO_SOC_UTIL_H__ -#include <types.h> enum socket_type { SOCKET_FP5 = 0, diff --git a/src/soc/cavium/cn81xx/include/soc/twsi.h b/src/soc/cavium/cn81xx/include/soc/twsi.h index 9756c6a..6a7923d 100644 --- a/src/soc/cavium/cn81xx/include/soc/twsi.h +++ b/src/soc/cavium/cn81xx/include/soc/twsi.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <device/i2c.h> #ifndef __SOC_CAVIUM_CN81XX_INCLUDE_SOC_TWSI_H diff --git a/src/soc/intel/common/vbt.h b/src/soc/intel/common/vbt.h index e5b0066..5cbb2c7 100644 --- a/src/soc/intel/common/vbt.h +++ b/src/soc/intel/common/vbt.h @@ -4,7 +4,6 @@ #define _INTEL_COMMON_VBT_H_ #include <commonlib/region.h> -#include <types.h> /* * Returns VBT pointer and mapping after checking prerequisites for Pre OS diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index e6bc1d4..ef1d1d4 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -3,7 +3,6 @@ #ifndef __SOC_MEDIATEK_MT6358_H__ #define __SOC_MEDIATEK_MT6358_H__ -#include <types.h> enum { PMIC_SWCID = 0x000a, diff --git a/src/soc/qualcomm/ipq806x/include/soc/clock.h b/src/soc/qualcomm/ipq806x/include/soc/clock.h index d7cb3c4..e9460d4 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/clock.h +++ b/src/soc/qualcomm/ipq806x/include/soc/clock.h @@ -5,7 +5,6 @@ #define __IPQ860X_CLOCK_H_ #include <soc/iomap.h> -#include <types.h> /* UART clock @ 7.3728 MHz */ #define UART_DM_CLK_RX_TX_BIT_RATE 0xCC diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index fb17102..945a85c 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -4,7 +4,6 @@ #define _SOC_QUALCOMM_QCS405_SYMBOLS_H_ #include <symbols.h> -#include <types.h> DECLARE_REGION(ssram); DECLARE_REGION(bsram); diff --git a/src/soc/qualcomm/sc7180/uart_bitbang.c b/src/soc/qualcomm/sc7180/uart_bitbang.c index b671fec..b3a6cd5 100644 --- a/src/soc/qualcomm/sc7180/uart_bitbang.c +++ b/src/soc/qualcomm/sc7180/uart_bitbang.c @@ -2,7 +2,6 @@ #include <console/uart.h> #include <gpio.h> -#include <types.h> #include <boot/coreboot_tables.h> #define UART_TX_PIN GPIO(44) diff --git a/src/soc/qualcomm/sdm845/uart_bitbang.c b/src/soc/qualcomm/sdm845/uart_bitbang.c index 6bcc5ba..b78db83 100644 --- a/src/soc/qualcomm/sdm845/uart_bitbang.c +++ b/src/soc/qualcomm/sdm845/uart_bitbang.c @@ -2,7 +2,6 @@ #include <console/uart.h> #include <gpio.h> -#include <types.h> #define UART_TX_PIN GPIO(4) diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index d63af6c..a568b74 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -3,7 +3,6 @@ #include <acpi/acpi.h> #include <acpi/acpigen.h> #include <cbmem.h> -#include <types.h> #include <string.h> #include <version.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb Gerrit-Change-Number: 41677 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 22

Change in coreboot[master]: src: Remove unused 'include <string.h>'
by HAOUAS Elyes (Code Review) 14 Jul '20

14 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41913 ) Change subject: src: Remove unused 'include <string.h>' ...................................................................... src: Remove unused 'include <string.h>' Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/) |grep -v vendorcode |grep '<' Change-Id: I12802d0a6254b2fa39d59f485008bb2012f7b32d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/acpi/soundwire.c M src/mainboard/dell/optiplex_9010/sch5545_ec.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/41913/1 diff --git a/src/acpi/soundwire.c b/src/acpi/soundwire.c index 341114a..701fe2a 100644 --- a/src/acpi/soundwire.c +++ b/src/acpi/soundwire.c @@ -6,7 +6,6 @@ #include <commonlib/helpers.h> #include <device/soundwire.h> #include <stdbool.h> -#include <string.h> /* Specification-defined prefix for SoundWire properties. */ #define SDW_PFX "mipi-sdw-" diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec.c b/src/mainboard/dell/optiplex_9010/sch5545_ec.c index 4013452..2719460 100644 --- a/src/mainboard/dell/optiplex_9010/sch5545_ec.c +++ b/src/mainboard/dell/optiplex_9010/sch5545_ec.c @@ -2,7 +2,6 @@ #include <cbfs.h> #include <cf9_reset.h> -#include <string.h> #include <option.h> #include <arch/io.h> #include <cpu/x86/msr.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12802d0a6254b2fa39d59f485008bb2012f7b32d Gerrit-Change-Number: 41913 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: Zork: Splits devicetree between baseboards
by Rob Barnes (Code Review) 14 Jul '20

14 Jul '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42741 ) Change subject: Zork: Splits devicetree between baseboards ...................................................................... Zork: Splits devicetree between baseboards Splits zork baseboard devicetree between dalboz and trembyle. The devicetree is simply duplicated, no other changes in this commit. BUG=b:158096224 BRANCH=none TEST=Build coreboot for zork Signed-off-by: Rob Barnes <robbarnes(a)google.com> Change-Id: I5b26770790092c69db9567fa4337edd21a6ed809 --- M src/mainboard/google/zork/Kconfig A src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb A src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb 3 files changed, 390 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42741/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index a226cd8..87713a2 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -77,7 +77,8 @@ config DEVICETREE string - default "variants/baseboard/devicetree.cb" + default "variants/baseboard/devicetree_trembyle.cb" if BOARD_GOOGLE_BASEBOARD_TREMBYLE + default "variants/baseboard/devicetree_dalboz.cb" if BOARD_GOOGLE_BASEBOARD_DALBOZ config OVERRIDE_DEVICETREE string diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb new file mode 100644 index 0000000..18c3783 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -0,0 +1,194 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Set FADT Configuration + register "fadt_pm_profile" = "PM_MOBILE" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_REMOTE_POWER_ON" + + register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" + + # Start : OPN Performance Configuration + # (Configuratin that is common for all variants) + # For the below fields, 0 indicates use SOC default + + # PROCHOT_L de-assertion Ramp Time + register "prochot_l_deassertion_ramp_time" = "20" #mS + + # Lower die temperature limit + register "thermctl_limit" = "100" #degrees C + + # FP5 Processor Voltage Supply PSI Currents + register "psi0_current_limit" = "18000" #mA + register "psi0_soc_current_limit" = "12000" #mA + register "vddcr_soc_voltage_margin" = "0" #mV + register "vddcr_vdd_voltage_margin" = "0" #mV + + # VRM Limits + register "vrm_maximum_current_limit" = "0" #mA + register "vrm_soc_maximum_current_limit" = "0" #mA + register "vrm_current_limit" = "0" #mA + register "vrm_soc_current_limit" = "0" #mA + + # Misc SMU settings + register "sb_tsi_alert_comparator_mode_en" = "0" + register "core_dldo_bypass" = "1" + register "min_soc_vid_offset" = "0" + register "aclk_dpm0_freq_400MHz" = "0" + + # End : OPN Performance Configuration + + register "sd_emmc_config" = "SD_EMMC_EMMC_HS400" + + # SPI Configuration + register "common_config.spi_config" = "{ + .normal_speed = SPI_SPEED_66M, /* MHz */ + .fast_speed = SPI_SPEED_66M, /* MHz */ + .altio_speed = SPI_SPEED_66M, /* MHz */ + .tpm_speed = SPI_SPEED_66M, /* MHz */ + .read_mode = SPI_READ_MODE_DUAL112, + }" + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x62, + /* + * Only 0x62 and 0x66 are required. But, this is not supported by + * standard IO decodes and there are only 4 generic I/O windows + * available. Hence, open a window from 0x62-0x67. + */ + .size = 5, + }, + .generic_io_range[1] = { + .base = 0x800, /* EC_HOST_CMD_REGION0 */ + .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ + }, + .generic_io_range[2] = { + .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ + .size = 255, /* EC_MEMMAP_SIZE */ + }, + .generic_io_range[3] = { + .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ + .size = 8, /* 0x200 - 0x207 */ + }, + + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .dedicated_alert_pin = 1, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 0, + .flash_ch_en = 0, + + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1) | ESPI_VW_IRQ_LEVEL_LOW(12), + }" + + register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + register "irq_override" = "{ + /* PS/2 keyboard IRQ1 override */ + {1, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH}, + + /* PS/2 mouse IRQ12 override */ + {12, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH}, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge, must be enabled + device pci 1.1 off end # GPP Bridge 0 + device pci 1.2 on end # GPP Bridge 1 - Wifi + device pci 1.3 on end # GPP Bridge 2 - SD + device pci 1.4 off end # GPP Bridge 3 + device pci 1.5 off end # GPP Bridge 4 + device pci 8.0 on end # Dummy Host Bridge, must be enabled + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.0 on end # Internal GPU + device pci 0.1 on end # Display HDA + device pci 0.2 on end # Crypto Coprocesor + device pci 0.5 on end # Audio + device pci 0.6 on end # HDA + device pci 0.7 on end # non-Sensor Fusion Hub device + end + device pci 8.2 on # Internal GPP Bridge 0 to Bus B + device pci 0.0 on end # AHCI + end + device pci 14.0 on end # SM + device pci 14.3 on # - D14F3 bridge + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + register "uid" = "1" + register "remote_bus" = "8" + device generic 0.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(62)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + end + chip ec/google/chromeec/i2c_tunnel + register "name" = ""MSTH"" + register "uid" = "1" + register "remote_bus" = "9" + device generic 1.0 on end + end + end + end + end + device pci 18.0 on end # Data fabric [0-7] + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + end # domain + + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" + register "sdmode_delay" = "5" + device generic 0.1 on end + end + + device mmio 0xfedc5000 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" + device i2c 50 on end + end + end + + device mmio 0xfedca000 off end # UART1 + device mmio 0xfedce000 off end # UART2 + device mmio 0xfedcf000 off end # UART3 + +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb new file mode 100644 index 0000000..18c3783 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -0,0 +1,194 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Set FADT Configuration + register "fadt_pm_profile" = "PM_MOBILE" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_REMOTE_POWER_ON" + + register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" + + # Start : OPN Performance Configuration + # (Configuratin that is common for all variants) + # For the below fields, 0 indicates use SOC default + + # PROCHOT_L de-assertion Ramp Time + register "prochot_l_deassertion_ramp_time" = "20" #mS + + # Lower die temperature limit + register "thermctl_limit" = "100" #degrees C + + # FP5 Processor Voltage Supply PSI Currents + register "psi0_current_limit" = "18000" #mA + register "psi0_soc_current_limit" = "12000" #mA + register "vddcr_soc_voltage_margin" = "0" #mV + register "vddcr_vdd_voltage_margin" = "0" #mV + + # VRM Limits + register "vrm_maximum_current_limit" = "0" #mA + register "vrm_soc_maximum_current_limit" = "0" #mA + register "vrm_current_limit" = "0" #mA + register "vrm_soc_current_limit" = "0" #mA + + # Misc SMU settings + register "sb_tsi_alert_comparator_mode_en" = "0" + register "core_dldo_bypass" = "1" + register "min_soc_vid_offset" = "0" + register "aclk_dpm0_freq_400MHz" = "0" + + # End : OPN Performance Configuration + + register "sd_emmc_config" = "SD_EMMC_EMMC_HS400" + + # SPI Configuration + register "common_config.spi_config" = "{ + .normal_speed = SPI_SPEED_66M, /* MHz */ + .fast_speed = SPI_SPEED_66M, /* MHz */ + .altio_speed = SPI_SPEED_66M, /* MHz */ + .tpm_speed = SPI_SPEED_66M, /* MHz */ + .read_mode = SPI_READ_MODE_DUAL112, + }" + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x62, + /* + * Only 0x62 and 0x66 are required. But, this is not supported by + * standard IO decodes and there are only 4 generic I/O windows + * available. Hence, open a window from 0x62-0x67. + */ + .size = 5, + }, + .generic_io_range[1] = { + .base = 0x800, /* EC_HOST_CMD_REGION0 */ + .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ + }, + .generic_io_range[2] = { + .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ + .size = 255, /* EC_MEMMAP_SIZE */ + }, + .generic_io_range[3] = { + .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ + .size = 8, /* 0x200 - 0x207 */ + }, + + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .dedicated_alert_pin = 1, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 0, + .flash_ch_en = 0, + + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1) | ESPI_VW_IRQ_LEVEL_LOW(12), + }" + + register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + register "irq_override" = "{ + /* PS/2 keyboard IRQ1 override */ + {1, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH}, + + /* PS/2 mouse IRQ12 override */ + {12, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH}, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge, must be enabled + device pci 1.1 off end # GPP Bridge 0 + device pci 1.2 on end # GPP Bridge 1 - Wifi + device pci 1.3 on end # GPP Bridge 2 - SD + device pci 1.4 off end # GPP Bridge 3 + device pci 1.5 off end # GPP Bridge 4 + device pci 8.0 on end # Dummy Host Bridge, must be enabled + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.0 on end # Internal GPU + device pci 0.1 on end # Display HDA + device pci 0.2 on end # Crypto Coprocesor + device pci 0.5 on end # Audio + device pci 0.6 on end # HDA + device pci 0.7 on end # non-Sensor Fusion Hub device + end + device pci 8.2 on # Internal GPP Bridge 0 to Bus B + device pci 0.0 on end # AHCI + end + device pci 14.0 on end # SM + device pci 14.3 on # - D14F3 bridge + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + register "uid" = "1" + register "remote_bus" = "8" + device generic 0.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(62)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + end + chip ec/google/chromeec/i2c_tunnel + register "name" = ""MSTH"" + register "uid" = "1" + register "remote_bus" = "9" + device generic 1.0 on end + end + end + end + end + device pci 18.0 on end # Data fabric [0-7] + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + end # domain + + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" + register "sdmode_delay" = "5" + device generic 0.1 on end + end + + device mmio 0xfedc5000 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" + device i2c 50 on end + end + end + + device mmio 0xfedca000 off end # UART1 + device mmio 0xfedce000 off end # UART2 + device mmio 0xfedcf000 off end # UART3 + +end # chip soc/amd/picasso -- To view, visit https://review.coreboot.org/c/coreboot/+/42741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b26770790092c69db9567fa4337edd21a6ed809 Gerrit-Change-Number: 42741 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: mainboard/volteer: Enable SaGv
by Shreesh Chhabbi (Code Review) 14 Jul '20

14 Jul '20

Shreesh Chhabbi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42483 ) Change subject: mainboard/volteer: Enable SaGv ...................................................................... mainboard/volteer: Enable SaGv Change-Id: I1bce3b9f837fb19ba5a20ae31750a73474a86788 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/42483/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 8cd926c..6dbc415 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -36,7 +36,7 @@ register "pmc_gpe0_dw2" = "GPP_E" # FSP configuration - register "SaGv" = "SaGv_Disabled" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "0" register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 -- To view, visit https://review.coreboot.org/c/coreboot/+/42483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bce3b9f837fb19ba5a20ae31750a73474a86788 Gerrit-Change-Number: 42483 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: mb/google/zork: Create Woomax variant
by Kane Chen (Code Review) 13 Jul '20

13 Jul '20

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42680 ) Change subject: mb/google/zork: Create Woomax variant ...................................................................... mb/google/zork: Create Woomax variant Create the Woomax variant of the zork. BUG=b:158343602 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I0bb8ce1851f4064d24e48fd8957e2f9fe1e80b53 --- M src/mainboard/google/zork/Kconfig M src/mainboard/google/zork/Kconfig.name A src/mainboard/google/zork/variants/woomax/Makefile.inc A src/mainboard/google/zork/variants/woomax/gpio.c A src/mainboard/google/zork/variants/woomax/include/variant/acpi/audio.asl A src/mainboard/google/zork/variants/woomax/include/variant/acpi/mainboard.asl A src/mainboard/google/zork/variants/woomax/include/variant/acpi/sleep.asl A src/mainboard/google/zork/variants/woomax/include/variant/acpi/thermal.asl A src/mainboard/google/zork/variants/woomax/include/variant/ec.h A src/mainboard/google/zork/variants/woomax/include/variant/gpio.h A src/mainboard/google/zork/variants/woomax/include/variant/thermal.h A src/mainboard/google/zork/variants/woomax/overridetree.cb A src/mainboard/google/zork/variants/woomax/spd/Makefile.inc 13 files changed, 334 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/42680/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index f6061c5..4aac136 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -64,6 +64,7 @@ default "dalboz" if BOARD_GOOGLE_DALBOZ default "berknip" if BOARD_GOOGLE_BERKNIP default "vilboz" if BOARD_GOOGLE_VILBOZ + default "woomax" if BOARD_GOOGLE_WOOMAX config MAINBOARD_PART_NUMBER string @@ -73,6 +74,7 @@ default "Dalboz" if BOARD_GOOGLE_DALBOZ default "Berknip" if BOARD_GOOGLE_BERKNIP default "Vilboz" if BOARD_GOOGLE_VILBOZ + default "Woomax" if BOARD_GOOGLE_WOOMAX config DEVICETREE string diff --git a/src/mainboard/google/zork/Kconfig.name b/src/mainboard/google/zork/Kconfig.name index 2f721d4..801c1b7 100644 --- a/src/mainboard/google/zork/Kconfig.name +++ b/src/mainboard/google/zork/Kconfig.name @@ -23,3 +23,7 @@ config BOARD_GOOGLE_BERKNIP bool "-> Berknip" select BOARD_GOOGLE_BASEBOARD_TREMBYLE + +config BOARD_GOOGLE_WOOMAX + bool "-> Woomax" + select BOARD_GOOGLE_BASEBOARD_TREMBYLE diff --git a/src/mainboard/google/zork/variants/woomax/Makefile.inc b/src/mainboard/google/zork/variants/woomax/Makefile.inc new file mode 100644 index 0000000..8142ac4 --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/Makefile.inc @@ -0,0 +1,16 @@ +# +# This file is part of the coreboot project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +subdirs-y += ./spd + +ramstage-y += gpio.c diff --git a/src/mainboard/google/zork/variants/woomax/gpio.c b/src/mainboard/google/zork/variants/woomax/gpio.c new file mode 100644 index 0000000..222360e --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/gpio.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> + +static const struct soc_amd_gpio woomax_gpio_set_stage_ram[] = { + /* GPIO_4 NC */ + PAD_GPI(GPIO_4, PULL_UP), + /* GPIO_5 NC */ + PAD_GPI(GPIO_5, PULL_UP), + /* GPIO_6 NC */ + PAD_GPI(GPIO_6, PULL_UP), + /* GPIO_11 NC */ + PAD_GPI(GPIO_11, PULL_UP), + /* GPIO_32 NC */ + PAD_GPI(GPIO_32, PULL_UP), + /* GPIO_69 NC */ + PAD_GPI(GPIO_69, PULL_UP), + /* RAM_ID_4 */ + PAD_GPI(GPIO_84, PULL_NONE), + /* GPIO_141 NC */ + PAD_GPI(GPIO_141, PULL_UP), + /* GPIO_143 NC */ + PAD_GPI(GPIO_143, PULL_UP), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(woomax_gpio_set_stage_ram); + return woomax_gpio_set_stage_ram; +} diff --git a/src/mainboard/google/zork/variants/woomax/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/woomax/include/variant/acpi/audio.asl new file mode 100644 index 0000000..71a4920 --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/include/variant/acpi/audio.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/zork/variants/woomax/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/woomax/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..63eb280 --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/include/variant/acpi/mainboard.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/mainboard.asl> diff --git a/src/mainboard/google/zork/variants/woomax/include/variant/acpi/sleep.asl b/src/mainboard/google/zork/variants/woomax/include/variant/acpi/sleep.asl new file mode 100644 index 0000000..a401b3a --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/include/variant/acpi/sleep.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/sleep.asl> diff --git a/src/mainboard/google/zork/variants/woomax/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/woomax/include/variant/acpi/thermal.asl new file mode 100644 index 0000000..a7e511c --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/include/variant/acpi/thermal.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/zork/variants/woomax/include/variant/ec.h b/src/mainboard/google/zork/variants/woomax/include/variant/ec.h new file mode 100644 index 0000000..fbd60dc --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/include/variant/ec.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/ec.h> diff --git a/src/mainboard/google/zork/variants/woomax/include/variant/gpio.h b/src/mainboard/google/zork/variants/woomax/include/variant/gpio.h new file mode 100644 index 0000000..726d255 --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/zork/variants/woomax/include/variant/thermal.h b/src/mainboard/google/zork/variants/woomax/include/variant/thermal.h new file mode 100644 index 0000000..addce73 --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/include/variant/thermal.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/thermal.h> diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb new file mode 100644 index 0000000..c6a3ff0 --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -0,0 +1,142 @@ +# +# This file is part of the coreboot project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #55593 Chapter 3.2 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "2" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit" = "25000" #mw + register "fast_ppt_limit" = "30000" #mw + register "slow_ppt_time_constant" = "5" #second + register "stapm_time_constant" = "200" #second + register "sustained_power_limit" = "15000" #mw + + register "telemetry_vddcr_vdd_slope" = "71222" #mA + register "telemetry_vddcr_vdd_offset" = "0" + register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_offset" = "0" + + # End : OPN Performance Configuration + + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 21, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 76, /* 2.31 to 0 */ + }" + + # Enable I2C3 for H1 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 125, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 37, /* 1.26v to 0 */ + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 1.6 off end # GPP Bridge 5 + device pci 1.7 on end # GPP Bridge 6 - NVME + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.3 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""User-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""AR Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.4 on end + end + end + end + end # USB 3.1 + device pci 0.4 on end # USB 3.1 + end + device pci 14.6 off end # Non-Functional SDHCI + end # domain + + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "22" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 10 on end + end + end + +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/woomax/spd/Makefile.inc b/src/mainboard/google/zork/variants/woomax/spd/Makefile.inc new file mode 100644 index 0000000..79fac45 --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/spd/Makefile.inc @@ -0,0 +1,37 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# Ordered List of APCB entries, upto 16. +# Entries should match this pattern {NAME}_x{1,2} +# There should be a matching SPD hex file in SPD_SOURCES_DIR +# matching the pattern {NAME}.spd.hex +# The _x{1,2} suffix denotes single or dual channel +# TODO: Remove channel suffix when b:141434940 is fixed +# Alternatively, generated APCBs stored at +# CONFIG_APCB_BLOB_DIR/APCB_{NAME}.bin can be included. +APCB_SOURCES = micron-MT40A512M16TB-062E-J_x1 # 0b00000 +APCB_SOURCES += hynix-H5AN8G6NCJR-XNC_x1 # 0b00001 +APCB_SOURCES += micron-MT40A1G16KD-062E-E_x1 # 0b00010 +APCB_SOURCES += samsung-K4AAG165WA-BCWE_x1 # 0b00011 +APCB_SOURCES += empty # 0b00100 +APCB_SOURCES += empty # 0b00101 +APCB_SOURCES += empty # 0b00110 +APCB_SOURCES += empty # 0b00111 +APCB_SOURCES += micron-MT40A512M16TB-062E-J_x2 # 0b01000 +APCB_SOURCES += hynix-H5AN8G6NCJR-XNC_x2 # 0b01001 +APCB_SOURCES += micron-MT40A1G16KD-062E-E_x2 # 0b01010 +APCB_SOURCES += samsung-K4AAG165WA-BCWE_x2 # 0b01011 +APCB_SOURCES += empty # 0b01100 +APCB_SOURCES += empty # 0b01101 +APCB_SOURCES += empty # 0b01110 +APCB_SOURCES += empty # 0b01111 -- To view, visit https://review.coreboot.org/c/coreboot/+/42680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bb8ce1851f4064d24e48fd8957e2f9fe1e80b53 Gerrit-Change-Number: 42680 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

5 29

Change in coreboot[master]: soc/intel/gpio: convert PAD_CFG0_ROUTE_* to PAD_IRQ_ROUTE()
by Maxim Polyakov (Code Review) 12 Jul '20

12 Jul '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41034 ) Change subject: soc/intel/gpio: convert PAD_CFG0_ROUTE_* to PAD_IRQ_ROUTE() ...................................................................... soc/intel/gpio: convert PAD_CFG0_ROUTE_* to PAD_IRQ_ROUTE() As with other macros, convert PAD_CFG0_ROUTE_* to PAD_IRQ_ROUTE() to make the code in gpio_defs.h cleaner. Change-Id: Iadc9c4b3c96ae04c56d060cb060737a8eba7f165 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/41034/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index ecc9489..713c808 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -138,6 +138,7 @@ #define PAD_FUNC(value) PAD_CFG0_MODE_##value #define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value #define PAD_RX_POL(value) PAD_CFG0_RX_POL_##value +#define PAD_IRQ_ROUTE(value) PAD_CFG0_ROUTE_##value #define PAD_TRIG(value) PAD_CFG0_TRIG_##value #define PAD_PULL(value) PAD_CFG1_PULL_##value @@ -159,14 +160,14 @@ #endif #define PAD_IRQ_CFG(route, trig, inv) \ - (PAD_CFG0_ROUTE_##route | \ + (PAD_IRQ_ROUTE(route) | \ PAD_TRIG(trig) | \ PAD_RX_POL(inv)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) #define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ - (PAD_CFG0_ROUTE_##route1 | \ - PAD_CFG0_ROUTE_##route2 | \ + (PAD_IRQ_ROUTE(route1) | \ + PAD_IRQ_ROUTE(route2) | \ PAD_TRIG(trig) | \ PAD_RX_POL(inv)) #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadc9c4b3c96ae04c56d060cb060737a8eba7f165 Gerrit-Change-Number: 41034 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/intel/gpio: convert PAD_CFG0_RX_POL_* to PAD_RX_POL()
by Maxim Polyakov (Code Review) 12 Jul '20

12 Jul '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41033 ) Change subject: soc/intel/gpio: convert PAD_CFG0_RX_POL_* to PAD_RX_POL() ...................................................................... soc/intel/gpio: convert PAD_CFG0_RX_POL_* to PAD_RX_POL() Converts PAD_CFG0_RX_POL_* macros to PAD_RX_POL() to make the code cleaner and reduce the length of the macro. Change-Id: I09a048fd38ccb994f53c8829c549bc2b368fa546 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/41033/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 90e669d..ecc9489 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -137,6 +137,7 @@ #define PAD_FUNC(value) PAD_CFG0_MODE_##value #define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value +#define PAD_RX_POL(value) PAD_CFG0_RX_POL_##value #define PAD_TRIG(value) PAD_CFG0_TRIG_##value #define PAD_PULL(value) PAD_CFG1_PULL_##value @@ -160,14 +161,14 @@ #define PAD_IRQ_CFG(route, trig, inv) \ (PAD_CFG0_ROUTE_##route | \ PAD_TRIG(trig) | \ - PAD_CFG0_RX_POL_##inv) + PAD_RX_POL(inv)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) #define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ (PAD_CFG0_ROUTE_##route1 | \ PAD_CFG0_ROUTE_##route2 | \ PAD_TRIG(trig) | \ - PAD_CFG0_RX_POL_##inv) + PAD_RX_POL(inv)) #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */ #define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ @@ -292,7 +293,7 @@ #define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(trig) | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE), \ + PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE) | PAD_CFG_OWN_GPIO(own)) #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ @@ -305,7 +306,7 @@ #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE), \ + PAD_RX_POL(NONE) | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) -- To view, visit https://review.coreboot.org/c/coreboot/+/41033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09a048fd38ccb994f53c8829c549bc2b368fa546 Gerrit-Change-Number: 41033 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: intel/gpio: convert PAD_CFG0_TRIG_* to PAD_TRIG()
by Maxim Polyakov (Code Review) 12 Jul '20

12 Jul '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41032 ) Change subject: intel/gpio: convert PAD_CFG0_TRIG_* to PAD_TRIG() ...................................................................... intel/gpio: convert PAD_CFG0_TRIG_* to PAD_TRIG() Converts PAD_CFG0_TRIG_ * macros to PAD_TRIG() to make the code cleaner and reduce the length of the macro, which is often used. Change-Id: I9e1b4118fd6c6f0d58ee38a743aa8c27535f0dd9 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 18 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/41032/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index d6c0287..90e669d 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -137,6 +137,7 @@ #define PAD_FUNC(value) PAD_CFG0_MODE_##value #define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value +#define PAD_TRIG(value) PAD_CFG0_TRIG_##value #define PAD_PULL(value) PAD_CFG1_PULL_##value /* Disable the input/output buffer of the pad */ @@ -158,14 +159,14 @@ #define PAD_IRQ_CFG(route, trig, inv) \ (PAD_CFG0_ROUTE_##route | \ - PAD_CFG0_TRIG_##trig | \ + PAD_TRIG(trig) | \ PAD_CFG0_RX_POL_##inv) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) #define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ (PAD_CFG0_ROUTE_##route1 | \ PAD_CFG0_ROUTE_##route2 | \ - PAD_CFG0_TRIG_##trig | \ + PAD_TRIG(trig) | \ PAD_CFG0_RX_POL_##inv) #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */ @@ -192,7 +193,7 @@ /* Native function configuration */ #define PAD_CFG_NF(pad, pull, rst, func) \ _PAD_CFG_STRUCT(pad, \ - PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_RESET(rst) | PAD_TRIG(OFF) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) /* @@ -200,7 +201,7 @@ * input/output buffer if necessary */ #define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_CFG0_TRIG_##trig | \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_TRIG(trig) | \ PAD_BUF(bufdis) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) @@ -210,62 +211,62 @@ */ #define PAD_CFG_NF_1V8(pad, pull, rst, func) \ _PAD_CFG_STRUCT(pad, \ - PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_RESET(rst) | PAD_TRIG(OFF) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8) #endif /* Native function configuration for standby state */ #define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ _PAD_CFG_STRUCT(pad, \ - PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_RESET(rst) | PAD_TRIG(OFF) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate)) /* Native function configuration for standby state, also configuring iostandby as masked */ #define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ _PAD_CFG_STRUCT(pad, \ - PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_RESET(rst) | PAD_TRIG(OFF) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(IGNORE)) /* Native function configuration for standby state, also configuring iosstate and iosterm */ #define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_RESET(rst) | PAD_TRIG(OFF) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* Configure native function, iosstate, iosterm and disable input/output buffer */ #define PAD_CFG_NF_BUF_IOSSTATE_IOSTERM(pad, pull, rst, func, bufdis, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_BUF(bufdis) | PAD_FUNC(func), \ + PAD_RESET(rst) | PAD_TRIG(OFF) | PAD_BUF(bufdis) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, with termination specified */ #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG_OWN_GPIO(DRIVER)) /* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) /* General purpose input */ @@ -291,13 +292,13 @@ #define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE), \ + PAD_TRIG(trig) | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE) | PAD_CFG_OWN_GPIO(own)) #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_BUF(TX_DISABLE), \ + PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | \ PAD_IOSSTATE(TxDRxE)) @@ -311,7 +312,7 @@ #define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_BUF(TX_RX_DISABLE), \ + PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* GPIO Interrupt */ @@ -326,7 +327,7 @@ #define PAD_NC(pad, pull) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \ - PAD_CFG0_TRIG_OFF | PAD_BUF(TX_RX_DISABLE), \ + PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS) -- To view, visit https://review.coreboot.org/c/coreboot/+/41032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e1b4118fd6c6f0d58ee38a743aa8c27535f0dd9 Gerrit-Change-Number: 41032 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: superio/nuvoton: Avoid NULL pointer dereference
by John Zhao (Code Review) 12 Jul '20

12 Jul '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42839 ) Change subject: superio/nuvoton: Avoid NULL pointer dereference ...................................................................... superio/nuvoton: Avoid NULL pointer dereference Coverity detects dereferencing a pointer that might be "NULL" when calling acpigen_write_scope. Add sanity check for scope to prevent NULL pointer dereference. Found-by: Coverity CID 1420207 Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Icc253c63aadef1c0ecb116a38b608f64f80abc79 --- M src/superio/nuvoton/npcd378/superio.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/42839/1 diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index 628bd4e..46923e0 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -325,7 +325,8 @@ acpigen_pop_len(); /* Pop Scope */ /* Inject into parent: */ - acpigen_write_scope(acpi_device_scope(dev)); + if (scope) + acpigen_write_scope(scope); acpigen_write_name_integer("MSFG", 1); acpigen_write_name_integer("KBFG", 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/42839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc253c63aadef1c0ecb116a38b608f64f80abc79 Gerrit-Change-Number: 42839 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/pcie: Remove auto-select ASPM and L1_SUB_STATE
by Christian Walter (Code Review) 12 Jul '20

12 Jul '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41696 ) Change subject: soc/intel/common/block/pcie: Remove auto-select ASPM and L1_SUB_STATE ...................................................................... soc/intel/common/block/pcie: Remove auto-select ASPM and L1_SUB_STATE Current the common soc code automatically selects PCIEXP_ASPM and PCIEXP_L1_SUB_STATE which breaks booting Windows with a PCIE NVIDIA graphics card attached. Tested on CFL with Windows 10 Change-Id: I025e13d6d8183256647e4c034e31bafa235f7eb7 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/soc/intel/common/block/pcie/Kconfig 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/41696/1 diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig index aa32324..308f197 100644 --- a/src/soc/intel/common/block/pcie/Kconfig +++ b/src/soc/intel/common/block/pcie/Kconfig @@ -1,9 +1,6 @@ config SOC_INTEL_COMMON_BLOCK_PCIE bool - select PCIEXP_ASPM - select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK - select PCIEXP_L1_SUB_STATE help Intel Processor common PCIE support -- To view, visit https://review.coreboot.org/c/coreboot/+/41696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I025e13d6d8183256647e4c034e31bafa235f7eb7 Gerrit-Change-Number: 41696 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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