coreboot-gerrit June 2020

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Change in coreboot[master]: mb/google/volteer: remove mainboard.asl
by EricR Lai (Code Review) 20 Jul '20

20 Jul '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41761 ) Change subject: mb/google/volteer: remove mainboard.asl ...................................................................... mb/google/volteer: remove mainboard.asl EGPM and RGPM are come after mainboard hook function MS0X and MPTS/MWAK. In CB:41712 is implemented EGPM and RGPM. So used the SoC level functions instead board level functions. Otherwise it will have side effects which is always store the MISCCFG_ENABLE_GPIO_PM_CONFIG and restore it. BUG=b:157280323 TEST=Check GPIO PM bits when enter/exit s0ix are expected Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ic87d4860af35296a659623043301da5520204c11 --- M src/mainboard/google/volteer/dsdt.asl D src/mainboard/google/volteer/mainboard.asl 2 files changed, 0 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/41761/1 diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index fa39e79..9a76d0a 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -32,8 +32,6 @@ #include <soc/intel/tigerlake/acpi/southbridge.asl> #include <soc/intel/tigerlake/acpi/tcss.asl> } - /* Mainboard hooks */ - #include "mainboard.asl" } // Chrome OS specific diff --git a/src/mainboard/google/volteer/mainboard.asl b/src/mainboard/google/volteer/mainboard.asl deleted file mode 100644 index c360fcf..0000000 --- a/src/mainboard/google/volteer/mainboard.asl +++ /dev/null @@ -1,47 +0,0 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#include <intelblocks/gpio.h> - -Method (PGPM, 1, Serialized) -{ - For (Local0 = 0, Local0 < 6, Local0++) - { - \_SB.PCI0.CGPM (Local0, Arg0) - } -} - -/* - * Method called from _PTS prior to system sleep state entry - * Enables dynamic clock gating for all 5 GPIO communities - */ -Method (MPTS, 1, Serialized) -{ - PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG) -} - -/* - * Method called from _WAK prior to system sleep state wakeup - * Disables dynamic clock gating for all 5 GPIO communities - */ -Method (MWAK, 1, Serialized) -{ - PGPM (0) -} - -/* - * S0ix Entry/Exit Notifications - * Called from \_SB.LPID._DSM - */ -Method (MS0X, 1, Serialized) -{ - If (Arg0 == 1) { - /* S0ix Entry */ - PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG) - } Else { - /* S0ix Exit */ - PGPM (0) - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/41761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic87d4860af35296a659623043301da5520204c11 Gerrit-Change-Number: 41761 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mb/google/deltaur: Enable SPD_READ_BY_WORD
by EricR Lai (Code Review) 20 Jul '20

20 Jul '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40645 ) Change subject: mb/google/deltaur: Enable SPD_READ_BY_WORD ...................................................................... mb/google/deltaur: Enable SPD_READ_BY_WORD SPD_READ_BY_WORD can reduce iteration of SPD reading loop. BUG=b:151702387 TEST=Check Memory SPD data is correct in console log. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ib68e830c25d95e8498eead155b2fa881b0ae0313 --- M src/mainboard/google/deltaur/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/40645/1 diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig index 74c8201..5ecad4f 100644 --- a/src/mainboard/google/deltaur/Kconfig +++ b/src/mainboard/google/deltaur/Kconfig @@ -16,6 +16,7 @@ select SOC_INTEL_TIGERLAKE select SYSTEM_TYPE_LAPTOP select MAINBOARD_USES_IFD_GBE_REGION if BOARD_GOOGLE_DELTAN + select SPD_READ_BY_WORD if BOARD_GOOGLE_BASEBOARD_DELTAUR -- To view, visit https://review.coreboot.org/c/coreboot/+/40645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib68e830c25d95e8498eead155b2fa881b0ae0313 Gerrit-Change-Number: 40645 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

6 29

Change in libgfxinit[master]: common/Makefile.inc: Factor out generation TLAs
by Angel Pons (Code Review) 19 Jul '20

19 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/42365 ) Change subject: common/Makefile.inc: Factor out generation TLAs ...................................................................... common/Makefile.inc: Factor out generation TLAs The Three Letter Acronyms that correspond to generation names appear four times inside complex sed-fu. Since they are the same, factor them out. Note the increased amount of backslashes, which are now required. Sanity-checked by building gfxtest for Haswell, whose executable remains identical regardless of whether this commit is applied or not. Change-Id: I63cb24d7334359d39aca4682632c3b9b6b698d43 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M common/Makefile.inc 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/65/42365/1 diff --git a/common/Makefile.inc b/common/Makefile.inc index e01bdc2..3519723 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -57,6 +57,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT := $(call strip_quotes,$(CONFIG_GFX_GMA_ANALOG_I2C_PORT)) CONFIG_GFX_GMA_IGNORE_PRESENCE_STRAPS := $(if $(filter y,$(CONFIG_GFX_GMA_IGNORE_PRESENCE_STRAPS)),True,False) +_GEN_TLA_SUBSTITUTIONS := '\\$g45\\\|ilk\\\|hsw\\\|skl\\$' + _GEN_NONCONST := $(strip \ $(if $(filter G45,$(CONFIG_GFX_GMA_GENERATION)),g45, \ $(if $(filter Ironlake,$(CONFIG_GFX_GMA_GENERATION)),ilk, \ @@ -86,9 +88,9 @@ sed $(GFX_GMA_COMMON_SUBSTITUTIONS) \ -e'/constant Gen_CPU$_Var$\?/d' \ -e's/<genbool>/constant Boolean/' \ - -e's/<$\(g45\|ilk\|hsw\|skl$$...$\?\)bool>/<\1var> Boolean/' \ + -e's/<$$(_GEN_TLA_SUBSTITUTIONS)\(...$\?\)bool>/<\1var> Boolean/' \ $(if $(_GEN_NONCONST),-e's/<$...$\?$(_GEN_NONCONST)$...$\?var>/<cpufunc>/') \ - -e's/<$g45\|ilk\|hsw\|skl$$...$\?var>/$(_GEN_CONST_TARGET)/' \ + -e's/<$(_GEN_TLA_SUBSTITUTIONS)$...$\?var>/$(_GEN_CONST_TARGET)/' \ -e's/$.*: *<cpufunc>.*:=$ *$.*$;/\1\n (\2);/' \ -e's/$[^ ]\+$ *: *<cpufunc> \+$[^ ]*$ *:=/function \1 return \2 is/' \ -e's/<cpunull>//' \ @@ -101,8 +103,8 @@ -e's/<<CPU_VARIANT>>/$(CONFIG_GFX_GMA_CPU_VARIANT)/' \ -e":s$$(printf '\n ')/,$$/{N;s/,\n.*Dyn_CPU$_Var$\?[^,)]*//;ts$$(printf '\n ')P;D;}" \ -e'/Dyn_CPU$_Var$\?/d' \ - -e's/<$gen\|\(g45\|ilk\|hsw\|skl$$...$\?\)bool>/constant Boolean/' \ - -e's/<$\(g45\|ilk\|hsw\|skl$$...$\?\)var>/constant/' \ + -e's/<$gen\|$(_GEN_TLA_SUBSTITUTIONS)\(...$\?\)bool>/constant Boolean/' \ + -e's/<$$(_GEN_TLA_SUBSTITUTIONS)\(...$\?\)var>/constant/' \ -e's/<cpunull>/ is null/' \ $< >$@ endif -- To view, visit https://review.coreboot.org/c/libgfxinit/+/42365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I63cb24d7334359d39aca4682632c3b9b6b698d43 Gerrit-Change-Number: 42365 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: soc/intel/gpio: do some fixes in code style
by Maxim Polyakov (Code Review) 19 Jul '20

19 Jul '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41035 ) Change subject: soc/intel/gpio: do some fixes in code style ...................................................................... soc/intel/gpio: do some fixes in code style Change-Id: Ib4b4c28153398b6275728b28bda90e527d97e823 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 96 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41035/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 713c808..f0d899d 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -146,7 +146,7 @@ #define PAD_CFG0_BUF_NO_DISABLE (0) #define PAD_CFG0_BUF_TX_DISABLE PAD_CFG0_TX_DISABLE #define PAD_CFG0_BUF_RX_DISABLE PAD_CFG0_RX_DISABLE -#define PAD_CFG0_BUF_TX_RX_DISABLE \ +#define PAD_CFG0_BUF_TX_RX_DISABLE \ (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE) #define PAD_BUF(value) PAD_CFG0_BUF_##value @@ -159,17 +159,17 @@ #define PAD_IOSTERM(value) 0 #endif -#define PAD_IRQ_CFG(route, trig, inv) \ - (PAD_IRQ_ROUTE(route) | \ - PAD_TRIG(trig) | \ - PAD_RX_POL(inv)) +#define PAD_IRQ_CFG(route, trig, inv) \ + (PAD_IRQ_ROUTE(route) | \ + PAD_TRIG(trig) | \ + PAD_RX_POL(inv)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) -#define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ - (PAD_IRQ_ROUTE(route1) | \ - PAD_IRQ_ROUTE(route2) | \ - PAD_TRIG(trig) | \ - PAD_RX_POL(inv)) +#define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ + (PAD_IRQ_ROUTE(route1) | \ + PAD_IRQ_ROUTE(route2) | \ + PAD_TRIG(trig) | \ + PAD_RX_POL(inv)) #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */ #define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ @@ -202,9 +202,10 @@ * Set native function with RX Level/Edge configuration and disable * input/output buffer if necessary */ -#define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_TRIG(trig) | \ - PAD_BUF(bufdis) | PAD_FUNC(func), \ +#define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(bufdis) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) @@ -244,56 +245,57 @@ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* General purpose output, no pullup/down. */ -#define PAD_CFG_GPO(pad, val, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ +#define PAD_CFG_GPO(pad, val, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, with termination specified */ -#define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ +#define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, no pullup/down. */ -#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ - PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG_OWN_GPIO(DRIVER)) +#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | \ + PAD_CFG_OWN_GPIO(DRIVER)) /* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) /* General purpose input */ -#define PAD_CFG_GPI(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ +#define PAD_CFG_GPI(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) -#define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ +#define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate)) -#define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ +#define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* * General purpose input. The following macro sets the * Host Software Pad Ownership to GPIO Driver mode. */ -#define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ +#define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE) | PAD_CFG_OWN_GPIO(own)) @@ -318,7 +320,7 @@ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* GPIO Interrupt */ -#define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ +#define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER) /* @@ -326,22 +328,22 @@ * Both TX and RX are disabled. RX disabling is done to avoid unnecessary * setting of GPI_STS. RX Level/Edge Trig Configuration set to disable */ -#define PAD_NC(pad, pull) \ +#define PAD_NC(pad, pull) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \ - PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \ + PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS) -#define PAD_CFG_GPI_APIC(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ +#define PAD_CFG_GPI_APIC(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(IOAPIC, LEVEL, NONE), PAD_PULL(pull)) -#define PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ +#define PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(IOAPIC, LEVEL, INVERT), PAD_PULL(pull)) #define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \ @@ -360,18 +362,18 @@ #else /* General purpose input, routed to APIC */ -#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) #endif /* General purpose input, routed to APIC - with IOStandby Config*/ -#define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* @@ -379,47 +381,47 @@ * on its own end. One just needs to pass an active high message into the * ITSS. */ -#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ +#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT) -#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ +#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE) -#define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \ +#define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \ PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT) /* General purpose input, routed to SMI */ -#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) /* General purpose input, routed to SMI */ -#define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) -#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ +#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT) -#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \ +#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \ PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE) /* General purpose input, routed to SCI */ -#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) /* General purpose input, routed to SCI */ -#define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) #define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \ @@ -428,33 +430,33 @@ #define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \ PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE) -#define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ - _PAD_CFG_STRUCT_3(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ + _PAD_CFG_STRUCT_3(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE), PAD_CFG2_DEBEN | PAD_CFG2_##dur) -#define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \ +#define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \ PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur) -#define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \ +#define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \ PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur) /* General purpose input, routed to NMI */ -#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) -#define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ +#define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) -#define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \ +#define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \ PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI) #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4b4c28153398b6275728b28bda90e527d97e823 Gerrit-Change-Number: 41035 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 25

Change in coreboot[master]: intel/gpio: set trig to default if its not a param for GPI
by Maxim Polyakov (Code Review) 18 Jul '20

18 Jul '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41031 ) Change subject: intel/gpio: set trig to default if its not a param for GPI ...................................................................... intel/gpio: set trig to default if its not a param for GPI If RX Level/Edge Configuration (RXEVCFG) isn't set in the macro using the parameter, then this should be the default value (2h = Drive '0'). Change-Id: I389435000d50af3e1815de5bc57025f85ab1cd38 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 17 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/41031/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 4bb318b..d6c0287 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -289,24 +289,29 @@ * Host Software Pad Ownership to GPIO Driver mode. */ #define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \ - _PAD_CFG_STRUCT(pad, PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE) | PAD_CFG_OWN_GPIO(own)) -#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ - PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE)) +#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_BUF(TX_DISABLE), \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | \ + PAD_IOSSTATE(TxDRxE)) -#define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \ - PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | \ +#define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE), \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) -#define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \ +#define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* GPIO Interrupt */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I389435000d50af3e1815de5bc57025f85ab1cd38 Gerrit-Change-Number: 41031 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: mb/supermicro/x11ssh-tf: set Host SW Pad Ownership to DRIVER
by Maxim Polyakov (Code Review) 17 Jul '20

17 Jul '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42920 ) Change subject: mb/supermicro/x11ssh-tf: set Host SW Pad Ownership to DRIVER ...................................................................... mb/supermicro/x11ssh-tf: set Host SW Pad Ownership to DRIVER Change-Id: I91ac4fce4bb27b763fcb4b4dfdf396b46bf103e1 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h 1 file changed, 44 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/42920/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h index 114095a..13d44c2 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h @@ -45,7 +45,7 @@ PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), /* GPP_A12 - GPIO */ - PAD_CFG_GPO(GPP_A12, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_A12, 1, PLTRST, NONE), /* GPP_A13 - SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), @@ -63,7 +63,7 @@ PAD_NC(GPP_A17, NONE), /* GPP_A18 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, PLTRST, OFF, DRIVER), /* GPP_A19 - RESERVED */ @@ -80,10 +80,10 @@ PAD_NC(GPP_A23, NONE), /* GPP_B0 - GPIO */ - PAD_CFG_GPO(GPP_B0, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B0, 1, DEEP, NONE), /* GPP_B1 - GPIO */ - PAD_CFG_GPO(GPP_B1, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B1, 1, DEEP, NONE), /* GPP_B2 - GPIO */ PAD_NC(GPP_B2, NONE), @@ -113,7 +113,7 @@ PAD_NC(GPP_B10, NONE), /* GPP_B11 - GPIO */ - PAD_CFG_GPO(GPP_B11, 0, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE), /* GPP_B12 - SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), @@ -140,7 +140,7 @@ PAD_NC(GPP_B19, NONE), /* GPP_B20 - GPIO */ - PAD_CFG_GPO(GPP_B20, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B20, 1, PLTRST, NONE), /* GPP_B21 - GPIO */ PAD_NC(GPP_B21, NONE), @@ -163,20 +163,20 @@ /* GPP_C4 - RESERVED */ /* GPP_C5 - GPIO */ - PAD_CFG_GPO(GPP_C5, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_C5, 1, DEEP, NONE), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* GPP_C8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, DRIVER), /* GPP_C9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, DRIVER), /* GPP_C10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, DRIVER), /* GPP_C11 - GPIO */ PAD_NC(GPP_C11, NONE), @@ -221,7 +221,7 @@ PAD_NC(GPP_D0, NONE), /* GPP_D1 - GPIO */ - PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), /* GPP_D2 - GPIO */ PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), @@ -230,7 +230,7 @@ PAD_NC(GPP_D3, NONE), /* GPP_D4 - GPIO */ - PAD_CFG_GPO(GPP_D4, 0, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE), /* GPP_D5 - GPIO */ PAD_NC(GPP_D5, NONE), @@ -272,19 +272,19 @@ PAD_NC(GPP_D17, NONE), /* GPP_D18 - GPIO */ - PAD_CFG_GPO(GPP_D18, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), /* GPP_D19 - GPIO */ - PAD_CFG_GPO(GPP_D19, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), /* GPP_D20 - GPIO */ PAD_NC(GPP_D20, NONE), /* GPP_D21 - GPIO */ - PAD_CFG_GPO(GPP_D21, 0, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE), /* GPP_D22 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, DRIVER), /* GPP_D23 - GPIO */ PAD_NC(GPP_D23, NONE), @@ -347,16 +347,16 @@ PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), /* GPP_F6 - GPIO */ - PAD_CFG_GPO(GPP_F6, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 1, PLTRST, NONE), /* GPP_F7 - GPIO */ - PAD_CFG_GPO(GPP_F7, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 1, PLTRST, NONE), /* GPP_F8 - GPIO */ - PAD_CFG_GPO(GPP_F8, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 1, PLTRST, NONE), /* GPP_F9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, DRIVER), /* GPP_F10 - SATA_SCLOCK */ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), @@ -398,19 +398,19 @@ PAD_NC(GPP_F22, NONE), /* GPP_F23 - GPIO */ - PAD_CFG_GPO(GPP_F23, 0, RSMRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, RSMRST, NONE), /* GPP_G0 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, DRIVER), /* GPP_G1 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, DRIVER), /* GPP_G2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, DRIVER), /* GPP_G3 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, DRIVER), /* GPP_G4 - GPIO */ PAD_NC(GPP_G4, NONE), @@ -437,19 +437,19 @@ PAD_NC(GPP_G11, NONE), /* GPP_G12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, DRIVER), /* GPP_G13 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, DRIVER), /* GPP_G14 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, DRIVER), /* GPP_G15 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, DRIVER), /* GPP_G16 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, DRIVER), /* GPP_G17 - GPIO */ PAD_NC(GPP_G17, NONE), @@ -473,34 +473,34 @@ PAD_NC(GPP_G23, NONE), /* GPP_H0 - GPIO */ - PAD_CFG_GPO(GPP_H0, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, DEEP, NONE), /* GPP_H1 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, DRIVER), /* GPP_H2 - GPIO */ - PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, DEEP, NONE), /* GPP_H3 - SRCCLKREQ9# */ PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), /* GPP_H4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, DRIVER), /* GPP_H5 - GPIO */ - PAD_CFG_GPO(GPP_H5, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H5, 1, PLTRST, NONE), /* GPP_H6 - GPIO */ - PAD_CFG_GPO(GPP_H6, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H6, 1, PLTRST, NONE), /* GPP_H7 - GPIO */ - PAD_CFG_GPO(GPP_H7, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H7, 1, PLTRST, NONE), /* GPP_H8 - GPIO */ - PAD_CFG_GPO(GPP_H8, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H8, 1, PLTRST, NONE), /* GPP_H9 - GPIO */ - PAD_CFG_GPO(GPP_H9, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H9, 1, PLTRST, NONE), /* GPP_H10 - SML2CLK */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), @@ -530,19 +530,19 @@ PAD_NC(GPP_H18, NONE), /* GPP_H19 - GPIO */ - PAD_CFG_GPO(GPP_H19, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H19, 1, PLTRST, NONE), /* GPP_H20 - GPIO */ - PAD_CFG_GPO(GPP_H20, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H20, 1, PLTRST, NONE), /* GPP_H21 - GPIO */ - PAD_CFG_GPO(GPP_H21, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H21, 1, PLTRST, NONE), /* GPP_H22 - GPIO */ - PAD_CFG_GPO(GPP_H22, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H22, 1, PLTRST, NONE), /* GPP_H23 - GPIO */ - PAD_CFG_GPO(GPP_H23, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H23, 1, PLTRST, NONE), /* GPD0 - GPIO */ PAD_NC(GPD0, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/42920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91ac4fce4bb27b763fcb4b4dfdf396b46bf103e1 Gerrit-Change-Number: 42920 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 18

Change in libgfxinit[master]: gfxtest: Update color mapping
by Angel Pons (Code Review) 17 Jul '20

17 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/42704 ) Change subject: gfxtest: Update color mapping ...................................................................... gfxtest: Update color mapping The color component order changed, but this was not updated. Tested on Asus P8Z77-V LX2 with two displays, no noticeable changes. Note that gfxtest is still very dangerous for people with epilepsy. Change-Id: I054f79be89720cc35946fb2ca4b198227ac0491a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M gfxtest/hw-gfx-gma-gfx_test.adb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/04/42704/1 diff --git a/gfxtest/hw-gfx-gma-gfx_test.adb b/gfxtest/hw-gfx-gma-gfx_test.adb index 63ab099..38d11d0 100644 --- a/gfxtest/hw-gfx-gma-gfx_test.adb +++ b/gfxtest/hw-gfx-gma-gfx_test.adb @@ -173,9 +173,9 @@ begin return (case Pipe is - when GMA.Primary => (Map (Xn, Yn), Map (Xp, Yn), Map (Xp, Yp), 255), - when GMA.Secondary => (Map (Xn, Yp), Map (Xn, Yn), Map (Xp, Yn), 255), - when GMA.Tertiary => (Map (Xp, Yp), Map (Xn, Yp), Map (Xn, Yn), 255)); + when GMA.Primary => (Map (Xp, Yp), Map (Xp, Yn), Map (Xn, Yn), 255), + when GMA.Secondary => (Map (Xp, Yn), Map (Xn, Yn), Map (Xn, Yp), 255), + when GMA.Tertiary => (Map (Xn, Yn), Map (Xn, Yp), Map (Xp, Yp), 255)); end Fill; procedure Test_Screen -- To view, visit https://review.coreboot.org/c/libgfxinit/+/42704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I054f79be89720cc35946fb2ca4b198227ac0491a Gerrit-Change-Number: 42704 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in libgfxinit[master]: gfxtest: Fix build failure with newer toolchain
by Angel Pons (Code Review) 17 Jul '20

17 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/42364 ) Change subject: gfxtest: Fix build failure with newer toolchain ...................................................................... gfxtest: Fix build failure with newer toolchain Looks like there's a new warning that requires us to have the same ordering in both a record definition and its memory layout definition. This is not the case on the `Pixel_Type` record in gfxtest, so gfxtest would not build with the GNAT 10.1.0 toolchain because of the warning. Since we define colors using positional notation, reordering the fields will result in the wrong colors being displayed. Account for that with the `Pixel_RGBA` inline function, which simply reorders the components. Change-Id: Ic4b6cfd7f933ffaeeac389e45e211483d35fc6ac Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M gfxtest/hw-gfx-gma-gfx_test.adb 1 file changed, 11 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/64/42364/1 diff --git a/gfxtest/hw-gfx-gma-gfx_test.adb b/gfxtest/hw-gfx-gma-gfx_test.adb index e5bc393..63ab099 100644 --- a/gfxtest/hw-gfx-gma-gfx_test.adb +++ b/gfxtest/hw-gfx-gma-gfx_test.adb @@ -51,10 +51,11 @@ end loop; end Restore_GTT; + -- FIXME: Intel Hardware enforces BGRA byte order. type Pixel_Type is record - Red : Byte; - Green : Byte; Blue : Byte; + Green : Byte; + Red : Byte; Alpha : Byte; end record; @@ -65,11 +66,14 @@ Alpha at 3 range 0 .. 7; end record; - White : constant Pixel_Type := (255, 255, 255, 255); - Black : constant Pixel_Type := ( 0, 0, 0, 255); - Red : constant Pixel_Type := (255, 0, 0, 255); - Green : constant Pixel_Type := ( 0, 255, 0, 255); - Blue : constant Pixel_Type := ( 0, 0, 255, 255); + function Pixel_RGBA (R, G, B, A : Byte) return Pixel_Type is + ((Red => R, Green => G, Blue => B, Alpha => A)) with Inline; + + White : constant Pixel_Type := Pixel_RGBA (255, 255, 255, 255); + Black : constant Pixel_Type := Pixel_RGBA ( 0, 0, 0, 255); + Red : constant Pixel_Type := Pixel_RGBA (255, 0, 0, 255); + Green : constant Pixel_Type := Pixel_RGBA ( 0, 255, 0, 255); + Blue : constant Pixel_Type := Pixel_RGBA ( 0, 0, 255, 255); function Pixel_To_Word (P : Pixel_Type) return Word32 with -- To view, visit https://review.coreboot.org/c/libgfxinit/+/42364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ic4b6cfd7f933ffaeeac389e45e211483d35fc6ac Gerrit-Change-Number: 42364 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Config PCH PCIe ports
by Morgan Jang (Code Review) 16 Jul '20

16 Jul '20

Morgan Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41690 ) Change subject: mb/ocp/deltalake: Config PCH PCIe ports ...................................................................... mb/ocp/deltalake: Config PCH PCIe ports Tested on OCP Delta Lake with lspci checking if PCIe speed is changed are expected. Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1 Signed-off-by: Morgan Jang <Morgan_Jang(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/romstage.c 1 file changed, 12 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/41690/1 diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index c456913..f6b828f 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -22,24 +22,28 @@ static void mainboard_config_iio(FSPM_UPD *mupd) { + int index; mupd->FspmConfig.IIoBifurcationTablePtr = (uint32_t) dl_iio_bifur_table; mupd->FspmConfig.NumOfIIoBifurcationTable = ARRAY_SIZE(dl_iio_bifur_table); + #if 0 mupd->FspmConfig.IioPciConfig.ConfigurationTable = (UPD_PCI_PORT_CONFIG *) dl_iio_pci_port; mupd->FspmConfig.IioPciConfig.NumberOfEntries = ARRAY_SIZE(dl_iio_pci_port); - - mupd->FspmConfig.PchPciConfig.PciPortConfig = - (UPD_PCH_PCIE_PORT *) dl_pch_pci_port; - mupd->FspmConfig.PchPciConfig.NumberOfEntries = - ARRAY_SIZE(dl_pch_pci_port); - - mupd->FspmConfig.PchPciConfig.RootPortFunctionSwapping = 0x00; - mupd->FspmConfig.PchPciConfig.PciePllSsc = 0x00; #endif + + for (index = 0; index < ARRAY_SIZE(dl_pch_pci_port); index++) { + mupd->FspmConfig.PchPcieForceEnable[dl_pch_pci_port[index].PortIndex] = + dl_pch_pci_port[index].ForceEnable; + mupd->FspmConfig.PchPciePortLinkSpeed[dl_pch_pci_port[index].PortIndex] = + dl_pch_pci_port[index].PortLinkSpeed; + } + + mupd->FspmConfig.PchPcieRootPortFunctionSwap = 0x00; + mupd->FspmConfig.PchPciePllSsc = 0xFE; } void mainboard_memory_init_params(FSPM_UPD *mupd) -- To view, visit https://review.coreboot.org/c/coreboot/+/41690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1 Gerrit-Change-Number: 41690 Gerrit-PatchSet: 1 Gerrit-Owner: Morgan Jang Gerrit-MessageType: newchange

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Change in coreboot[master]: util/board-status: Reject logs with unknown timestamps
by Paul Menzel (Code Review) 15 Jul '20

15 Jul '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41857 ) Change subject: util/board-status: Reject logs with unknown timestamps ...................................................................... util/board-status: Reject logs with unknown timestamps Check the output of `cbmem -t` for unknown timestamps. If present, ask the user to rebuild `cbmem`. Change-Id: Ief7aa1a698f10d9721964ad1bee057fcd9f4aa40 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M util/board_status/board_status.sh 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/41857/1 diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 2e93fe2..e772238 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -431,6 +431,11 @@ echo "Getting timestamp data" cmd_nonfatal $LOCAL "$cbmem_cmd -t" "${tmpdir}/${results}/coreboot_timestamps.txt" + if [ $(grep -- unknown "${tmpdir}/${results}/coreboot_timestamps.txt") ]; then + echo "Unknown timestamps found in 'coreboot_timestamps.txt'." \ + "Please rebuild the utility 'cbmem'." + exit $EXIT_FAILURE + fi if [ "$cmos_enabled" -eq 1 ]; then echo "Verifying that nvramtool is available" -- To view, visit https://review.coreboot.org/c/coreboot/+/41857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief7aa1a698f10d9721964ad1bee057fcd9f4aa40 Gerrit-Change-Number: 41857 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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