coreboot-gerrit June 2020

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Change in coreboot[master]: mb/ocp/tiogapass: Populate SMBIOS type 11 OEM data
by Johnny Lin (Code Review) 24 Jul '20

24 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40524 ) Change subject: mb/ocp/tiogapass: Populate SMBIOS type 11 OEM data ...................................................................... mb/ocp/tiogapass: Populate SMBIOS type 11 OEM data 1. Populate SMBIOS type 11 OEM data according to OEM specification. 2. Set the read PPIN MSR for CPU0 and CPU1 to BMC. Tested on OCP Tioga Pass. Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e --- M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/ipmi.c A src/mainboard/ocp/tiogapass/ipmi.h M src/mainboard/ocp/tiogapass/ramstage.c 4 files changed, 111 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40524/1 diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc index 27370fd..33ae2ff 100644 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -15,6 +15,7 @@ bootblock-y += bootblock.c ramstage-y += ramstage.c +ramstage-y += ipmi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ diff --git a/src/mainboard/ocp/tiogapass/ipmi.c b/src/mainboard/ocp/tiogapass/ipmi.c new file mode 100644 index 0000000..7d98c0c --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ipmi.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdint.h> +#include <drivers/ipmi/ipmi_kcs.h> +#include <console/console.h> +#include "ipmi.h" + +void ipmi_set_ppin(struct ppin_req *req) +{ + int ret; + struct ipmi_rsp rsp; + + ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN, + (const unsigned char *) req, sizeof(*req), + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + return; + } + printk(BIOS_INFO, "IPMI Set PPIN done.\n"); +} diff --git a/src/mainboard/ocp/tiogapass/ipmi.h b/src/mainboard/ocp/tiogapass/ipmi.h new file mode 100644 index 0000000..f8a98c9 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ipmi.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef TIOGAPASS_IPMI_H +#define TIOGAPASS_IPMI_H +#include <types.h> +#include <drivers/ipmi/ipmi_ops.h> + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_OEM_SET_PPIN 0x77 + +#define BMC_KCS_BASE 0xca2 + +/* PPIN for 2 CPU IPMI request */ +struct ppin_req { + uint32_t CPU0lo; + uint32_t CPU0hi; + uint32_t CPU1lo; + uint32_t CPU1hi; +} __packed; +/* Send CPU0 and CPU1 PPIN to BMC */ +void ipmi_set_ppin(struct ppin_req *req); +#endif diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index 4820ed4..61d6aef 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -16,17 +16,17 @@ #include <bootstate.h> #include <gpio.h> #include <soc/lewisburg_pch_gpio_defs.h> +#include <soc/msr.h> #include <smbios.h> #include <drivers/ipmi/ipmi_ops.h> +#include "ipmi.h" #define FRU_DEVICE_ID 0 -#define BMC_KCS_BASE 0xca2 static struct fru_info_str fru_strings; void mainboard_silicon_init_params(FSPS_UPD *params) { - read_fru_areas(BMC_KCS_BASE, FRU_DEVICE_ID, 0, &fru_strings); } /* Override SMBIOS type 1 data. */ @@ -148,4 +148,65 @@ gpio_output(GPP_B20, 0); } +/* Override SMBIOS type 11 OEM string */ +static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + char ppin[17]; + char blank[] = " "; + + /* Add OEM string 1 to 3 */ + if (*fru_strings.board_info.board_custom != NULL) + t->count = smbios_add_string(t->eos, *fru_strings.board_info.board_custom); + else + t->count = smbios_add_string(t->eos, blank); + if (*fru_strings.prod_info.product_custom != NULL) + t->count = smbios_add_string(t->eos, *fru_strings.prod_info.product_custom); + else + t->count = smbios_add_string(t->eos, blank); + + if (*(fru_strings.prod_info.product_custom + 1) != NULL) + t->count = smbios_add_string(t->eos, + *(fru_strings.prod_info.product_custom + 1)); + else + t->count = smbios_add_string(t->eos, blank); + + /* Add blank for OEM String 4 */ + t->count = smbios_add_string(t->eos, blank); + /* Add CPU0 and CPU1 PPIN to OEM string 5 and 6. */ + snprintf(ppin, sizeof(ppin), "%x%x", xeon_sp_ppin[0].hi, xeon_sp_ppin[0].lo); + t->count = smbios_add_string(t->eos, ppin); + snprintf(ppin, sizeof(ppin), "%x%x", xeon_sp_ppin[1].hi, xeon_sp_ppin[1].lo); + t->count = smbios_add_string(t->eos, ppin); + /* Add OEM string 7 */ + if (*(fru_strings.board_info.board_custom + 1) != NULL) + t->count = smbios_add_string(t->eos, + *(fru_strings.board_info.board_custom + 1)); + else + t->count = smbios_add_string(t->eos, blank); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->get_smbios_strings = mainboard_smbios_strings, + + read_fru_areas(BMC_KCS_BASE, FRU_DEVICE_ID, 0, &fru_strings); +} + +static void mainboard_final(void *chip_info) +{ + struct ppin_req req; + + req.CPU0lo = xeon_sp_ppin[0].lo; + req.CPU0hi = xeon_sp_ppin[0].hi; + req.CPU1lo = xeon_sp_ppin[1].lo; + req.CPU1hi = xeon_sp_ppin[1].hi; + /* Set PPIN to BMC */ + ipmi_set_ppin(&req); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; + BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/40524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e Gerrit-Change-Number: 40524 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 17

Change in coreboot[master]: [UNTESTED] mb/google/zork: don't enable IRQ1/IRQ12 filter
by Felix Held (Code Review) 23 Jul '20

23 Jul '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42611 ) Change subject: [UNTESTED] mb/google/zork: don't enable IRQ1/IRQ12 filter ...................................................................... [UNTESTED] mb/google/zork: don't enable IRQ1/IRQ12 filter Some zork devices had issues with keyboard and touchpad IRQs not being delivered under some conditions. Disabling the IRQ1/IRQ12 filter might fix this issue. Change-Id: If646d4745454cdc1b3a0da5187a5af2d31116b90 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/zork/mainboard.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/42611/1 diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index c6b4bdd..9a755d9 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -117,7 +117,7 @@ /* The MISC registers are not interrupt numbers */ { PIRQ_MISC, 0xfa, 0x00 }, - { PIRQ_MISC0, 0xf1, 0x00 }, + { PIRQ_MISC0, 0x91, 0x00 }, { PIRQ_MISC1, 0x00, 0x00 }, { PIRQ_MISC2, 0x00, 0x00 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/42611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If646d4745454cdc1b3a0da5187a5af2d31116b90 Gerrit-Change-Number: 42611 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/google/sarien: Enable bayhub 720 on Sarien
by Frank Wu (Code Review) 23 Jul '20

23 Jul '20

Hello Ivy Jian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42740 to review the following change. Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ...................................................................... mb/google/sarien: Enable bayhub 720 on Sarien Add PCIe-eMMC bridge bayhub 720 on Sarien. BUG=b:157971972 BRANCH=sarien TEST=local build and boot from storage successfully Change-Id: I28f40a420d51f476487655548f386cfbdc2e5329 Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> --- M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/variants/sarien/Makefile.inc M src/mainboard/google/sarien/variants/sarien/devicetree.cb A src/mainboard/google/sarien/variants/sarien/mainboard.c 4 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42740/1 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index df5e5b8..53b9243 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_BH720 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_ISH if BOARD_GOOGLE_ARCADA diff --git a/src/mainboard/google/sarien/variants/sarien/Makefile.inc b/src/mainboard/google/sarien/variants/sarien/Makefile.inc index eff19f5..238c6e9 100644 --- a/src/mainboard/google/sarien/variants/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/variants/sarien/Makefile.inc @@ -2,5 +2,6 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += mainboard.c romstage-y += gpio.c verstage-y += gpio.c diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 09b4240..24bccc0 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -395,12 +395,20 @@ device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on end # PCI Express Port 8 device pci 1d.0 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 diff --git a/src/mainboard/google/sarien/variants/sarien/mainboard.c b/src/mainboard/google/sarien/variants/sarien/mainboard.c new file mode 100644 index 0000000..f4df8b4 --- /dev/null +++ b/src/mainboard/google/sarien/variants/sarien/mainboard.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/mmio.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <drivers/generic/bayhub/bh720.h> +#include <string.h> + +void board_bh720(struct device *dev) +{ + u32 sdbar; + u32 bh720_pcr_data; + + printk(BIOS_DEBUG, "mainboard: board_bh720 init\n"); + sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); + + /* Enable Memory Access Function */ + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + + /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); + + /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + bh720_pcr_data &= 0x0000FFFF; + bh720_pcr_data |= 0x2510 << 16; + write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); + + /* Use PLL Base clock PCR 0x3E4[22] = 1 */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_CSR); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_CSR); + + /* Disable Memory Access */ + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28f40a420d51f476487655548f386cfbdc2e5329 Gerrit-Change-Number: 42740 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

7 24

Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory initialization parameters
by Maulik V Vaghela (Code Review) 23 Jul '20

23 Jul '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38507 ) Change subject: mb/intel/jasperlake_rvp: Add memory initialization parameters ...................................................................... mb/intel/jasperlake_rvp: Add memory initialization parameters JasperLake RVP has 2 different memory support: DDR4 and LPDDR4x Since there are no major difference except for memory configuration, we're not creating variants for this. We'll handle memory parameters based on board id. Board Id for DDR4 board is 1 and LPDDR4 board is 4. BUG=NONE BRANCH=NONE TEST=Build jslrvp board and check compilation Change-Id: Ia59b37900a7f3dba66f47c8f7333aa3503847fff Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c M src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc A src/mainboard/intel/jasperlake_rvp/spd/micron16Gb.spd.hex M src/mainboard/intel/jasperlake_rvp/spd/spd_util.c 4 files changed, 113 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/38507/1 diff --git a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c index 0ab1f48..f63f1b3 100644 --- a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,10 +13,71 @@ * GNU General Public License for more details. */ +#include <arch/byteorder.h> +#include <console/console.h> #include <fsp/api.h> #include <soc/romstage.h> +#include <spd_bin.h> +#include "board_id.h" +#include "spd/spd.h" + +#define BOARD_ID_JSL_DDR4 0x01 void mainboard_memory_init_params(FSPM_UPD *mupd) { - /* ToDo : Fill FSP-M memory params */ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + + u8 board_id = (get_board_id() & 0x1F) & 0x7; + printk(BIOS_DEBUG, "Board Id is 0x%x\n", board_id); + + struct region_device spd_rdev; + + if(board_id == BOARD_ID_JSL_DDR4) { + /* Set Board type for and SmBus Addresses for DDR4 */ + mem_cfg->UserBd = BOARD_TYPE_MOBILE; + + mem_cfg->SpdAddressTable[0] = 0xA0; + mem_cfg->SpdAddressTable[1] = 0xA2; + mem_cfg->SpdAddressTable[2] = 0xA4; + mem_cfg->SpdAddressTable[3] = 0xA6; + + } else { + + mem_cfg->UserBd = BOARD_TYPE_ULT_ULX; + + /* + * Currently only one SPD is required so keeping spd_index = 0 + * In future if we have more variants, we can change it to be based + * on board id. + */ + uint8_t spd_index = 0; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + + /* set smbus addresses to 0 for Lp4x board */ + + mem_cfg->SpdAddressTable[0] = 0x00; + mem_cfg->SpdAddressTable[1] = 0x00; + mem_cfg->SpdAddressTable[2] = 0x00; + mem_cfg->SpdAddressTable[3] = 0x00; + + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + } + + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->CaVrefConfig = 0x2; /* VREF_CA->CHA/CHB */ + mem_cfg->ECT = 1; /* Early Command Training Enabled */ + mem_cfg->RefClk = 0; /* Auto Select CLK freq */ + + mainboard_fill_dq_map_ch0(mem_cfg->DqByteMapCh0); + mainboard_fill_dq_map_ch1(mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_ch0(mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_ch1(mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(mem_cfg->RcompTarget); } diff --git a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc index b8b059a..afe855a 100644 --- a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Intel Corporation. +## Copyright (C) 2020 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,4 +17,4 @@ SPD_BIN = $(obj)/spd.bin -SPD_SOURCES = empty # 0b000 +SPD_SOURCES = micron16Gb # 0b000 diff --git a/src/mainboard/intel/jasperlake_rvp/spd/micron16Gb.spd.hex b/src/mainboard/intel/jasperlake_rvp/spd/micron16Gb.spd.hex new file mode 100644 index 0000000..a27c249 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/spd/micron16Gb.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 B0 08 00 40 00 00 0A 22 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c b/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c index bdf8ede..afccaf1 100644 --- a/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,10 +21,8 @@ #include "spd.h" enum jsl_dimm_type { - jsl_u_ddr4 = 0, - jsl_u_lpddr4 = 1, - jsl_u_lpddr4_type_3 = 4, - jsl_y_lpddr4 = 6 + jsl_u_ddr4 = 1, + jsl_u_lpddr4 = 4, }; void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr) @@ -37,7 +35,7 @@ memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } -static uint8_t get_spd_index(void) +static uint8_t get_board_type(void) { return get_board_id() & 0x7; } @@ -54,24 +52,15 @@ void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr) { /* DQS CPU<>DRAM map Ch0 */ - const u8 dqs_map_u_ddr[8] = { 2, 0, 1, 3, 6, 4, 7, 5 }; - const u8 dqs_map_u_lpddr[8] = { 2, 3, 0, 1, 7, 6, 4, 5 }; - const u8 dqs_map_u_lpddr_type_3[8] = { 2, 3, 1, 0, 7, 6, 4, 5 }; - const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; + const u8 dqs_map_u_ddr4[8] = { 0, 1, 3, 2, 4, 5, 6, 7 }; + const u8 dqs_map_u_lpddr4[8] = { 0, 3, 2, 1, 7, 5, 4, 6 }; - switch (get_spd_index()) { + switch (get_board_type()) { case jsl_u_ddr4: - memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); + memcpy(dqs_map_ptr, dqs_map_u_ddr4, sizeof(dqs_map_u_ddr4)); break; case jsl_u_lpddr4: - memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); - break; - case jsl_u_lpddr4_type_3: - memcpy(dqs_map_ptr, dqs_map_u_lpddr_type_3, - sizeof(dqs_map_u_lpddr_type_3)); - break; - case jsl_y_lpddr4: - memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); + memcpy(dqs_map_ptr, dqs_map_u_lpddr4, sizeof(dqs_map_u_lpddr4)); break; default: break; @@ -81,20 +70,15 @@ void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr) { /* DQS CPU<>DRAM map Ch1 */ - const u8 dqs_map_u_ddr[8] = { 1, 3, 2, 0, 5, 7, 6, 4 }; - const u8 dqs_map_u_lpddr[8] = { 1, 0, 3, 2, 5, 4, 7, 6 }; - const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 5, 4, 7, 6 }; + const u8 dqs_map_u_ddr4[8] = { 1, 0, 4, 5, 2, 3, 6, 7 }; + const u8 dqs_map_u_lpddr4[8] = { 3, 1, 2, 0, 4, 7, 6, 5 }; - switch (get_spd_index()) { + switch (get_board_type()) { case jsl_u_ddr4: - memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); + memcpy(dqs_map_ptr, dqs_map_u_ddr4, sizeof(dqs_map_u_ddr4)); break; case jsl_u_lpddr4: - case jsl_u_lpddr4_type_3: - memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); - break; - case jsl_y_lpddr4: - memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); + memcpy(dqs_map_ptr, dqs_map_u_lpddr4, sizeof(dqs_map_u_lpddr4)); break; default: break; @@ -112,18 +96,16 @@ { /* Rcomp target */ static const u16 RcompTarget_DDR4[RCOMP_TARGET_PARAMS] = { - 100, 33, 32, 33, 28 }; + 0, 0, 0, 0, 0 }; static const u16 RcompTarget_LPDDR4_Ax[RCOMP_TARGET_PARAMS] = { 80, 40, 40, 40, 30 }; - switch (get_spd_index()) { + switch (get_board_type()) { case jsl_u_ddr4: memcpy(rcomp_strength_ptr, RcompTarget_DDR4, sizeof(RcompTarget_DDR4)); break; - case jsl_y_lpddr4: case jsl_u_lpddr4: - case jsl_u_lpddr4_type_3: memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax, sizeof(RcompTarget_LPDDR4_Ax)); break; -- To view, visit https://review.coreboot.org/c/coreboot/+/38507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia59b37900a7f3dba66f47c8f7333aa3503847fff Gerrit-Change-Number: 38507 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

2 5

Change in ...coreboot[master]: soc/intel/cannonlake: Enable all C states in FSP
by Maulik V Vaghela (Code Review) 23 Jul '20

23 Jul '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32463 Change subject: soc/intel/cannonlake: Enable all C states in FSP ...................................................................... soc/intel/cannonlake: Enable all C states in FSP FSP will not enable all C-states by default when we use FSP to do MP initialization. We need to set UPD from coreboot to enable C-states in FSP. Change-Id: I845c61fd14f2f5de21288067eeb7c371710da249 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32463/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 2b83275..7b28058 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -352,6 +352,9 @@ /* Unlock all GPIO pads */ tconfig->PchUnlockGpioPads = config->PchUnlockGpioPads; + + /* Enable all Cx state in FSP */ + tconfig->Cx = 1; } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I845c61fd14f2f5de21288067eeb7c371710da249 Gerrit-Change-Number: 32463 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: drivers/ocp/ipmi: Add ipmi POST start/end command
by Tim Chu (Code Review) 23 Jul '20

23 Jul '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41605 ) Change subject: drivers/ocp/ipmi: Add ipmi POST start/end command ...................................................................... drivers/ocp/ipmi: Add ipmi POST start/end command Add functions of sending POST start/end command to BMC. These functions are used in ramstage. Signed-off-by: TimChu <Tim.Chu(a)quantatw.com> Change-Id: Ide0e2a52876db555ed8b5e919215e85731fd80ed --- A src/drivers/ocp/ipmi/Kconfig A src/drivers/ocp/ipmi/Makefile.inc A src/drivers/ocp/ipmi/ipmi_ocp.c A src/drivers/ocp/ipmi/ipmi_ocp.h 4 files changed, 132 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/41605/1 diff --git a/src/drivers/ocp/ipmi/Kconfig b/src/drivers/ocp/ipmi/Kconfig new file mode 100644 index 0000000..95c51c0 --- /dev/null +++ b/src/drivers/ocp/ipmi/Kconfig @@ -0,0 +1,3 @@ +config IPMI_OCP + bool + default n diff --git a/src/drivers/ocp/ipmi/Makefile.inc b/src/drivers/ocp/ipmi/Makefile.inc new file mode 100644 index 0000000..8291f82 --- /dev/null +++ b/src/drivers/ocp/ipmi/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_IPMI_OCP) += ipmi_ocp.c diff --git a/src/drivers/ocp/ipmi/ipmi_ocp.c b/src/drivers/ocp/ipmi/ipmi_ocp.c new file mode 100644 index 0000000..c1766d9 --- /dev/null +++ b/src/drivers/ocp/ipmi/ipmi_ocp.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Place in devicetree.cb: + * + * chip drivers/ocp/ipmi # OCP specific IPMI porting + device pnp ca2.1 on end + * end + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "chip.h" +#include "drivers/ipmi/ipmi_kcs.h" +#include "ipmi_ocp.h" + +static int ipmi_set_post_start(struct device *dev, struct ipmi_rsp *rsp) +{ + int ret; + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_OEM, 0, + IPMI_BMC_SET_POST_START, NULL, 0, (u8 *)rsp, + sizeof(*rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp->completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp->completion_code); + return 1; + } + if (ret != sizeof(*rsp)) { + printk(BIOS_ERR, "IPMI: %s response truncated\n", __func__); + return 1; + } + return 0; +} + +static int ipmi_set_post_end(struct device *dev, struct ipmi_rsp *rsp) +{ + int ret; + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_OEM, 0, + IPMI_BMC_SET_POST_END, NULL, 0, (u8 *)rsp, + sizeof(*rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp->completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp->completion_code); + return 1; + } + if (ret != sizeof(*rsp)) { + printk(BIOS_ERR, "IPMI: %s response truncated\n", __func__); + return 1; + } + return 0; +} + +static void ipmi_ocp_init(struct device *dev) +{ + struct ipmi_rsp postrsp; + + /* Send POST start to BMC. */ + if (!ipmi_set_post_start(dev, &postrsp)) + printk(BIOS_DEBUG, "IPMI BMC POST is started\n"); +} + +static void ipmi_ocp_final(struct device *dev) +{ + struct ipmi_rsp postrsp; + + /* Send POST end to BMC. */ + if (!ipmi_set_post_end(dev, &postrsp)) + printk(BIOS_DEBUG, "IPMI BMC POST is ended\n"); +} + +static void ipmi_set_resources(struct device *dev) +{ + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) { + if (!(res->flags & IORESOURCE_ASSIGNED)) + continue; + + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } +} + +static void ipmi_read_resources(struct device *dev) +{ + struct resource *res = new_resource(dev, 0); + res->base = dev->path.pnp.port; + res->size = 2; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static struct device_operations ops = { + .read_resources = ipmi_read_resources, + .set_resources = ipmi_set_resources, + .init = ipmi_ocp_init, + .final = ipmi_ocp_final, +}; + +static void enable_dev(struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PNP) + printk(BIOS_ERR, "%s: Unsupported device type\n", + dev_path(dev)); + else if (dev->path.pnp.port & 1) + printk(BIOS_ERR, "%s: Base address needs to be aligned to 2\n", + dev_path(dev)); + else + dev->ops = &ops; +} + +struct chip_operations drivers_ocp_ipmi_ops = { + CHIP_NAME("IPMI OCP") + .enable_dev = enable_dev, +}; diff --git a/src/drivers/ocp/ipmi/ipmi_ocp.h b/src/drivers/ocp/ipmi/ipmi_ocp.h new file mode 100644 index 0000000..1cdea2f --- /dev/null +++ b/src/drivers/ocp/ipmi/ipmi_ocp.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __IPMI_OCP_H +#define __IPMI_OCP_H + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_BMC_SET_POST_START 0x73 +#define IPMI_BMC_SET_POST_END 0x74 + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/41605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide0e2a52876db555ed8b5e919215e85731fd80ed Gerrit-Change-Number: 41605 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

6 21

Change in coreboot[master]: mb/ocp/deltalake: Implement SMBIOS type 9 by SKU
by Morgan Jang (Code Review) 23 Jul '20

23 Jul '20

Morgan Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42280 ) Change subject: mb/ocp/deltalake: Implement SMBIOS type 9 by SKU ...................................................................... mb/ocp/deltalake: Implement SMBIOS type 9 by SKU Create SMBIOS type 9 by getting PCIe config from BMC. TEST=Check SMBIOS type 9 is created correctly by different SKU. Change-Id: Ifd2031b91c960ff2add8807247271eb7c38a0bf2 Signed-off-by: Morgan Jang <Morgan_Jang(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 148 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/42280/1 diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index ae11296..bac6eea 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -4,11 +4,47 @@ #include <drivers/ipmi/ipmi_ops.h> #include <drivers/ocp/dmi/ocp_dmi.h> #include <soc/ramstage.h> +#include <string.h> +#include <smbios.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <soc/util.h> #include "ipmi.h" extern struct fru_info_str fru_strings; +/* System Slot Socket, Stack, Type and Data bus width Information */ +typedef struct { + u8 stack; + u8 slot_type; + u8 slot_data_bus_width; + u8 dev_func; + const char *slot_designator; +} slot_info; + +#define STACK_BUS0 0x0 +#define STACK_BUS15 0x1 +#define STACK_BUS63 0x2 +#define STACK_BUSB2 0x4 + +slot_info slotinfo[] = { + {STACK_BUS0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0xE8, "DL on board M.2 #1 - boot"}, + {STACK_BUS63, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "DL on board M.2 #2"}, + {STACK_BUS63, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "Mezz Card"}, + {STACK_BUSB2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "1ou expansion M.2 #1"}, + {STACK_BUSB2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "1ou expansion M.2 #2"}, + {STACK_BUSB2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "1ou expansion M.2 #3"}, + {STACK_BUSB2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "1ou expansion M.2 #4"}, + {STACK_BUS15, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "2ou expansion M.2 #1"}, + {STACK_BUS15, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "2ou expansion M.2 #2"}, + {STACK_BUS15, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "2ou expansion M.2 #3"}, + {STACK_BUS15, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "2ou expansion M.2 #4"}, + {STACK_BUS63, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "2ou expansion M.2 #5"}, + {STACK_BUS63, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "2ou expansion M.2 #6"}, + {STACK_BUSB2, SlotTypePciExpressGen3X16, SlotDataBusWidth16X, 0x00, "Mezz Card(Class-2)"}, +}; + static void dl_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) { uint8_t pcie_config = 0; @@ -45,10 +81,122 @@ } } +#if CONFIG(GENERATE_SMBIOS_TABLES) +static int create_smbios_type9(int *handle, unsigned long *current) +{ + int index; + int length = 0; + uint8_t slot_length; + uint8_t sec_bus; + uint8_t slot_usage; + uint8_t pcie_config = 0; + uint8_t characteristics_1 = 0; + uint8_t characteristics_2 = 0; + uint32_t vendor_device_id; + uint32_t stack_busnos[6]; + pci_devfn_t pci_dev; + unsigned int cap; + uint16_t sltcap; + + if (ipmi_get_pcie_config(&pcie_config) != CB_SUCCESS) + printk(BIOS_ERR, "Failed to get IPMI PCIe config\n"); + + get_stack_busnos(stack_busnos); + + for (index = 0; index < sizeof(slotinfo); index++) { + if (pcie_config == PCIE_CONFIG_A) { + if (index == 0 || index == 2) + printk(BIOS_INFO, "Find Config-A slot: %s\n", + slotinfo[index].slot_designator); + else + continue; + } + if (pcie_config == PCIE_CONFIG_B) { + if (index == 0 || index == 1 || index == 2 || index == 3 || index == 4 + || index == 5 || index == 6) + printk(BIOS_INFO, "Find Config-B slot: %s\n", + slotinfo[index].slot_designator); + else + continue; + } + if (pcie_config == PCIE_CONFIG_C) { + if (index == 0 || index == 1 || index == 7 || index == 8 || index == 9 + || index == 10 || index == 11 || index == 12 || index == 13) + printk(BIOS_INFO, "Find Config-C slot: %s\n", + slotinfo[index].slot_designator); + else + continue; + } + if (pcie_config == PCIE_CONFIG_D) { + if (index != 13) + printk(BIOS_INFO, "Find Config-D slot: %s\n", + slotinfo[index].slot_designator); + else + continue; + } + + if (slotinfo[index].slot_data_bus_width == SlotDataBusWidth16X) + slot_length = SlotLengthLong; + else + slot_length = SlotLengthShort; + + pci_dev = PCI_DEV(stack_busnos[index], slotinfo[index].dev_func >> 3, + slotinfo[index].dev_func & 0x7); + sec_bus = pci_s_read_config8(pci_dev, PCI_SECONDARY_BUS); + + if (sec_bus == 0xFF) { + slot_usage = SlotUsageUnknown; + } else { + /* Checking for Slot device availability */ + pci_dev = PCI_DEV(sec_bus, 0, 0); + vendor_device_id = pci_s_read_config32(pci_dev, 0); + if (vendor_device_id == 0xFFFFFFFF) + slot_usage = SlotUsageAvailable; + else + slot_usage = SlotUsageInUse; + } + + characteristics_1 |= SMBIOS_SLOT_3P3V; // Provides33Volts + characteristics_2 |= SMBIOS_SLOT_PME; // PmeSiganalSupported + + cap = pci_s_find_capability(pci_dev, PCI_CAP_ID_PCIE); + sltcap = pci_s_read_config16(pci_dev, cap + PCI_EXP_SLTCAP); + if (sltcap & PCI_EXP_SLTCAP_HPC) + characteristics_2 |= SMBIOS_SLOT_HOTPLUG; + + length += smbios_write_type9(current, handle, + slotinfo[index].slot_designator, + slotinfo[index].slot_type, + slotinfo[index].slot_data_bus_width, + slot_usage, + slot_length, + characteristics_1, + characteristics_2, + stack_busnos[slotinfo[index].stack], + slotinfo[index].dev_func); + } + + return length; +} + +static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) +{ + int len = 0; + + len += create_smbios_type9(handle, current); + + return len; +} +#endif + + static void mainboard_enable(struct device *dev) { dev->ops->get_smbios_strings = dl_oem_smbios_strings, read_fru_areas(BMC_KCS_BASE, FRU_DEVICE_ID, 0, &fru_strings); +#if (CONFIG(GENERATE_SMBIOS_TABLES)) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif } void mainboard_silicon_init_params(FSPS_UPD *params) -- To view, visit https://review.coreboot.org/c/coreboot/+/42280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd2031b91c960ff2add8807247271eb7c38a0bf2 Gerrit-Change-Number: 42280 Gerrit-PatchSet: 1 Gerrit-Owner: Morgan Jang Gerrit-MessageType: newchange

6 19

Change in coreboot[master]: mb/google/dedede: Enable the CSE Lite SKU for waddledoo
by V Sowmya (Code Review) 23 Jul '20

23 Jul '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41818 ) Change subject: mb/google/dedede: Enable the CSE Lite SKU for waddledoo ...................................................................... mb/google/dedede: Enable the CSE Lite SKU for waddledoo This patch enables enables the CSE Lite SKU for the waddledoo board. Change-Id: I24d7d715d55524807af0127aa4a346a008164b8c Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/dedede/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/41818/1 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 25ad61f..9f6cd52 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -12,6 +12,7 @@ select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 select VARIANT_HAS_CAMERA_ACPI + select SOC_INTEL_CSE_LITE_SKU config BOARD_GOOGLE_WADDLEDEE bool "Waddledee" -- To view, visit https://review.coreboot.org/c/coreboot/+/41818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24d7d715d55524807af0127aa4a346a008164b8c Gerrit-Change-Number: 41818 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: mb/google/dedede: Skip the CPU replacement check for dedede
by V Sowmya (Code Review) 23 Jul '20

23 Jul '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42930 ) Change subject: mb/google/dedede: Skip the CPU replacement check for dedede ...................................................................... mb/google/dedede: Skip the CPU replacement check for dedede This patches enables the SkipCpuReplacementCheck config for the dedede baseboard to avoid the forced MRC training for all its variants with the soldered down SOC. Change-Id: I611e66f74a3b9b090ab5e0d836231643d3f919dc Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/42930/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index f95d123..61ffae9 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -161,6 +161,9 @@ # register "common_soc_config.<variable_name>" = "value" register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT + # Skip the CPU repalcement check + register "SkipCpuReplacementCheck" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- To view, visit https://review.coreboot.org/c/coreboot/+/42930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I611e66f74a3b9b090ab5e0d836231643d3f919dc Gerrit-Change-Number: 42930 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/intel/jasperlake: Enable the SkipCpuReplacementCheck
by V Sowmya (Code Review) 23 Jul '20

23 Jul '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42453 ) Change subject: soc/intel/jasperlake: Enable the SkipCpuReplacementCheck ...................................................................... soc/intel/jasperlake: Enable the SkipCpuReplacementCheck This patch enable the fspm upd to SkipCpuReplacementCheck. Change-Id: I63fcdab3686322406cf7c24fc26cbb535cc58c8d Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/jasperlake/romstage/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/42453/1 diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index d9063b0..dbfb9b5 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -113,6 +113,9 @@ ARRAY_SIZE(config->PchHdaAudioLinkSndwEnable), "copy buffer overflow!"); memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, sizeof(config->PchHdaAudioLinkSndwEnable)); + + /* Setting this option to skip CPU replacement check */ + m_cfg->SkipCpuReplacementCheck = 1; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/42453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63fcdab3686322406cf7c24fc26cbb535cc58c8d Gerrit-Change-Number: 42453 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2020