coreboot-gerrit June 2020

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Change in coreboot[master]: drivers/mrc_cache: Avoid unused variable assignment
by Paul Menzel (Code Review) 26 Jul '20

26 Jul '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42798 ) Change subject: drivers/mrc_cache: Avoid unused variable assignment ...................................................................... drivers/mrc_cache: Avoid unused variable assignment Fix the scan-build warning below: CC romstage/drivers/mrc_cache/mrc_cache.o src/drivers/mrc_cache/mrc_cache.c:450:26: warning: Value stored to 'flash' during its initialization is never read const struct spi_flash *flash = boot_device_spi_flash(); ^~~~~ ~~~~~~~~~~~~~~~~~~~~~~~ 1 warning generated. The function can return early before the value is read. Fix this, by getting rid of the variable, as the value is only read once. Change-Id: I3c94b123f4994eed9d7568b63971fd5b1d94bc09 Found-by: scan-build (clang-tools-9 1:9.0.1-12) Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/drivers/mrc_cache/mrc_cache.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/42798/1 diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 3a005db..d567a20 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -447,15 +447,13 @@ /* Apply protection to a range of flash */ static int nvm_protect(const struct region *r) { - const struct spi_flash *flash = boot_device_spi_flash(); - if (!CONFIG(MRC_SETTINGS_PROTECT)) return 0; if (!CONFIG(BOOT_DEVICE_SPI_FLASH)) return 0; - return spi_flash_ctrlr_protect_region(flash, r, WRITE_PROTECT); + return spi_flash_ctrlr_protect_region(boot_device_spi_flash(), r, WRITE_PROTECT); } /* Protect mrc region with a Protected Range Register */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c94b123f4994eed9d7568b63971fd5b1d94bc09 Gerrit-Change-Number: 42798 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: mb/asus/p2b: Enable hardware monitor access via ISA bus
by Keith Hui (Code Review) 26 Jul '20

26 Jul '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41561 ) Change subject: mb/asus/p2b: Enable hardware monitor access via ISA bus ...................................................................... mb/asus/p2b: Enable hardware monitor access via ISA bus Setup a 8-byte I/O range at 0x290-0x297 on PIIX4's generic device 9 which activates a chip select when this range is accessed. On the P2B family this connects to the W83781D hardware monitor, allowing access to it over the ISA bus, just like vendor firmware. TEST=lm-sensors can detect chip and get readings over ISA. Change-Id: Iaed1df7230359e94c580c305f4769c8bb4f5fce0 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A src/mainboard/asus/p2b/mainboard.c 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/41561/1 diff --git a/src/mainboard/asus/p2b/mainboard.c b/src/mainboard/asus/p2b/mainboard.c new file mode 100644 index 0000000..ffdc78a --- /dev/null +++ b/src/mainboard/asus/p2b/mainboard.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <southbridge/intel/i82371eb/i82371eb.h> + +/** + * Mainboard specific enables. + * + * @param chip_info Ignored + */ +static void mainboard_init(void *chip_info) +{ + const pci_devfn_t px43 = PCI_DEV(0, 4, 3); + u32 reg; + /* + * Setup an 8-byte generic I/O decode block at device 9. + * This will be for W83781D hardware monitor. + * Port 0x290 mask 0x007 + * + * This should enable access to W83781D over the ISA bus. + */ + reg = pci_s_read_config32(px43, 0x60); /* DEVRESB */ + reg |= (0x290 | (0xe7 << 16)); + pci_s_write_config32(px43, 0x60, reg); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/41561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaed1df7230359e94c580c305f4769c8bb4f5fce0 Gerrit-Change-Number: 41561 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: sb/intel/i82371eb: Add #defines for DEVRESx registers
by Keith Hui (Code Review) 26 Jul '20

26 Jul '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41638 ) Change subject: sb/intel/i82371eb: Add #defines for DEVRESx registers ...................................................................... sb/intel/i82371eb: Add #defines for DEVRESx registers Change [41561] uses DEVRESB. [41561] https://review.coreboot.org/c/coreboot/+/41561 Change-Id: Id13dde5ce2239064b9b18de7ca516525158ae268 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/i82371eb.h 1 file changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/41638/1 diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 449161e..f0572ca 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -91,10 +91,20 @@ #define GPO3 0x37 /* Power management (ACPI) PCI registers */ -#define PMBA 0x40 /* Power management base address */ -#define DEFAULT_PMBASE 0xe400 +#define PMBA 0x40 /* Power management base address */ +#define DEFAULT_PMBASE 0xe400 #define PM_IO_BASE DEFAULT_PMBASE -#define PMREGMISC 0x80 /* Miscellaneous power management */ +#define DEVRESA 0X5c /* Device resource A */ +#define DEVRESB 0X60 /* Device resource B */ +#define DEVRESC 0X64 /* Device resource C */ +#define DEVRESD 0x50 /* Device resource D */ +#define DEVRESE 0x68 /* Device resource E */ +#define DEVRESF 0x6c /* Device resource F */ +#define DEVRESG 0x70 /* Device resource G */ +#define DEVRESH 0x74 /* Device resource H */ +#define DEVRESI 0x78 /* Device resource I */ +#define DEVRESJ 0x7c /* Device resource J */ +#define PMREGMISC 0x80 /* Miscellaneous power management */ #define PMIOSE (1 << 0) /* PM I/O Space Enable */ /* Bit definitions */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id13dde5ce2239064b9b18de7ca516525158ae268 Gerrit-Change-Number: 41638 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: sb/intel/i82371eb: Clean up PM register #defines
by Keith Hui (Code Review) 26 Jul '20

26 Jul '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41637 ) Change subject: sb/intel/i82371eb: Clean up PM register #defines ...................................................................... sb/intel/i82371eb: Clean up PM register #defines Remove EIO define. It is unused and means something else, elsewhere in the tree. Move PMIOSE bit definition next to PMREGMISC, where it actually belongs. Clarify in comments which PM register defines are in PCI config space are which are in I/O space. Change-Id: Ic7f2267d013403c0a519c2ee1786bd3c7f5a9708 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/i82371eb.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/41637/1 diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index a08be0d..449161e 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -43,7 +43,7 @@ #define SMBUS_IO_BASE 0x0f00 #define SMBHSTCFG 0xd2 /* SMBus host configuration */ -/* Power management (ACPI) */ +/* Power management (ACPI) I/O ports, offset from PM_IO_BASE below */ #define PMSTS 0x00 /* Power Management Status */ #define PMEN 0x02 /* Power Management Resume Enable */ #define PWRBTN_EN (1<<8) @@ -90,10 +90,12 @@ #define GPO2 0x36 #define GPO3 0x37 +/* Power management (ACPI) PCI registers */ #define PMBA 0x40 /* Power management base address */ #define DEFAULT_PMBASE 0xe400 #define PM_IO_BASE DEFAULT_PMBASE #define PMREGMISC 0x80 /* Miscellaneous power management */ +#define PMIOSE (1 << 0) /* PM I/O Space Enable */ /* Bit definitions */ #define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */ @@ -109,7 +111,5 @@ #define SSDE0 (1 << 2) /* Secondary Drive 0 UDMA/33 */ #define SSDE1 (1 << 3) /* Secondary Drive 1 UDMA/33 */ #define ISA (1 << 0) /* Select ISA */ -#define EIO (0 << 0) /* Select EIO */ -#define PMIOSE (1 << 0) /* PM I/O Space Enable */ #endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7f2267d013403c0a519c2ee1786bd3c7f5a9708 Gerrit-Change-Number: 41637 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: util/amdfwtool: Add support for EFS SPI values for F17h and F15h
by Matt Papageorge (Code Review) 26 Jul '20

26 Jul '20

Matt Papageorge has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42566 ) Change subject: util/amdfwtool: Add support for EFS SPI values for F17h and F15h ...................................................................... util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morpheus. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge(a)amd.corp-partner.google.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 100 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/42566/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index a5e5110..0241ba2 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -215,7 +215,14 @@ printf("-q | --anywhere Use any 64-byte aligned addr for Directory\n"); printf("-R | --sharedmem Location of PSP/FW shared memory\n"); printf("-P | --sharedmem-size Maximum size of the PSP/FW shared memory area\n"); + printf("-C | --soc-family <HEX_VAL> Specify SOC Family\n"); + printf("-D | --soc-model-min <HEX_VAL> Specify minimum SOC Model support\n"); + printf("-E | --soc-model-max <HEX_VAL> Specify maximum SOC Model support\n"); printf("-h | --help show this help\n"); + printf("\Embedded Firmware Structure options:\n"); + printf("--spi-speed <HEX_VAL> SPI speed to place in EFS Table\n"); + printf("--spi-read-mode <HEX_VAL> SPI read mode to place in EFS Table\n"); + printf("--spi-micron-flag <HEX_VAL> SPI Micron override flag to place in EFS Table\n"); } typedef enum _amd_bios_type { @@ -413,7 +420,26 @@ uint32_t bios0_entry; /* todo: add way to select correct entry */ uint32_t bios1_entry; uint32_t bios2_entry; - uint32_t reserved[0x2c]; /* 0x24 - 0x4f */ + uint32_t second_gen_efs; + uint32_t bios3_entry; + uint32_t reserved_2Ch; + uint32_t promontory_fw_ptr; + uint32_t lp_promontory_fw_ptr; + uint32_t reserved_38h; + uint32_t reserved_3Ch; + uint8_t spi_readmode_f15_mod_60_6f; + uint8_t fast_speed_new_f15_mod_60_6f; + uint8_t reserved_42h; + uint8_t spi_readmode_f17_mod_00_2f; + uint8_t spi_fastspeed_f17_mod_00_2f; + uint8_t qpr_dummy_cycle_f17_mod_00_2f; + uint8_t reserved_46h; + uint8_t spi_readmode_f17_mod_30_3f; + uint8_t spi_fastspeed_f17_mod_30_3f; + uint8_t micron_detect_f17_mod_30_3f; + uint8_t reserved_4Ah; + uint8_t reserved_4Bh; + uint32_t reserved_4Ch; } __attribute__((packed, aligned(16))) embedded_firmware; typedef struct _psp_directory_header { @@ -1038,8 +1064,18 @@ fill_dir_header(biosdir, count, cookie); } -// Unused values: CDE -static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:"; + +enum { + /* begin after ASCII characters */ + LONGOPT_FAMILY = 256, + LONGOPT_MODEL = 257, + LONGOPT_SPI_READ_MODE = 258, + LONGOPT_SPI_SPEED = 259, + LONGOPT_SPI_MICRON_FLAG = 260, +}; + +// Use non-ASCII values for additional input parameters +static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C:D:E:"; static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1086,6 +1122,10 @@ {"mp2-config", required_argument, 0, 'X' }, {"apob-nv-base", required_argument, 0, 'F' }, {"apob-nv-size", required_argument, 0, 'H' }, + /* Embedded Firmware Structure items*/ + {"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE }, + {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, + {"spi-micron-flag", required_argument, 0, LONGOPT_SPI_MICRON_FLAG }, /* other */ {"output", required_argument, 0, 'o' }, {"flashsize", required_argument, 0, 'f' }, @@ -1093,6 +1133,9 @@ {"anywhere", no_argument, 0, 'q' }, {"sharedmem", required_argument, 0, 'R' }, {"sharedmem-size", required_argument, 0, 'P' }, + {"soc-family", required_argument, 0, 'C' }, + {"soc-model-min", required_argument, 0, 'D' }, + {"soc-model-max", required_argument, 0, 'E' }, {"help", no_argument, 0, 'h' }, {NULL, 0, 0, 0 } }; @@ -1200,6 +1243,13 @@ bool any_location = 0; uint32_t romsig_offset; uint32_t rom_base_address; + uint8_t soc_family = 0; + uint8_t soc_model_min = 0; + uint8_t soc_model_max = 0; + uint8_t efs_spi_readmode = 0xff; + uint8_t efs_spi_speed = 0xff; + uint8_t efs_spi_micron_flag = 0xff; + int multi = 0; while (1) { @@ -1394,6 +1444,30 @@ register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); sub = instance = 0; break; + case 'C': + soc_family = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; + case 'D': + soc_model_min = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; + case 'E': + soc_model_max = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; + case LONGOPT_SPI_READ_MODE: + efs_spi_readmode = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; + case LONGOPT_SPI_SPEED: + efs_spi_speed = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; + case LONGOPT_SPI_MICRON_FLAG: + efs_spi_micron_flag = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; case 'o': output = optarg; break; @@ -1455,6 +1529,11 @@ retval = 1; } + if (soc_model_min > soc_model_max) { + printf("Error: Invalid SOC model range.\n\n"); + retval = 1; + } + if (retval) { usage(); return retval; @@ -1512,6 +1591,24 @@ amd_romsig->gec_entry = 0; amd_romsig->xhci_entry = 0; + if (soc_family == 0x15 && soc_model_min >= 0x60 && soc_model_max <= 0x6f) { + amd_romsig->second_gen_efs = 0; + amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode; + amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed; + } + if (soc_family == 0x17 && soc_model_min >= 0x0 && soc_model_max <= 0x2f) { + amd_romsig->second_gen_efs = 0; + amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; + amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; + amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = efs_spi_micron_flag; + } + if (soc_family == 0x17 && soc_model_min >= 0x30 && soc_model_max <= 0x3f) { + amd_romsig->second_gen_efs = 1; + amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; + amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; + amd_romsig->micron_detect_f17_mod_30_3f = efs_spi_micron_flag; + } + integrate_firmwares(&ctx, amd_romsig, amd_fw_table); ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Gerrit-Change-Number: 42566 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu,soc/intel: Drop select SMP
by Kyösti Mälkki (Code Review) 26 Jul '20

26 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42091 ) Change subject: cpu,soc/intel: Drop select SMP ...................................................................... cpu,soc/intel: Drop select SMP Implicitly selected with MAX_CPUS != 1. Change-Id: I4ac3e30e9f96cd52244b4bae73bafce0564d41e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M 3rdparty/vboot M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_6ex/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f4x/Kconfig M src/cpu/qemu-x86/Kconfig M src/mainboard/asus/p2b/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 24 files changed, 1 insertion(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/42091/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index c531000..59f874d 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit c531000f851418520b6873f65c202d21f141eb84 +Subproject commit 59f874d20aa1be0aab52aaa0e93cdea92df0080e diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index a82198a..fbdfd55 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -10,7 +10,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SMP select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 79dda28..0a29d69 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -4,7 +4,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SMP select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 1ba8894..095fee5 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -4,7 +4,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SMP select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index a76a95d..84049a0 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -9,7 +9,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SMP select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index e312605..3806ce8 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -9,7 +9,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SMP select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 3af5272..ed2dce8 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -4,7 +4,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SMP select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index e3d327c..25c1447 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -4,7 +4,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SMP select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index dcf9441..0c92479 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -4,7 +4,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SMP select SUPPORT_CPU_UCODE_IN_CBFS select SMM_ASEG select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 9a5e2a1..fbb00fa 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -4,7 +4,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SMP select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_HYPERTHREADING diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 4ef60b5..9398d18 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -4,5 +4,4 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 21ada02..3136162 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -6,7 +6,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SMP select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index f21de71..f8fca08 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -7,7 +7,6 @@ select SDRAMPWR_4DIMM select HAVE_MP_TABLE select IOAPIC - select SMP config BOARD_SPECIFIC_OPTIONS def_bool y diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 9323aed..c60b711 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -31,7 +31,6 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select IOAPIC select PCR_COMMON_IOSF_1_0 - select SMP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS # Audio options diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 1fd9c40..f0c85a6 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -26,7 +26,6 @@ select PCIEXP_COMMON_CLOCK select REG_SCRIPT select RTC - select SMP select SPI_FLASH select SSE2 select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index a437db2..1c1de65 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -30,7 +30,6 @@ select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_RESET - select SMP select SPI_FLASH select SSE2 select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 67f7563..9ea7a47 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -28,7 +28,6 @@ select REG_SCRIPT select PARALLEL_MP select RTC - select SMP select SPI_FLASH select SSE2 select TSC_SYNC_MFENCE diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dfc90cd..99a8c38 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -83,7 +83,6 @@ select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select REG_SCRIPT - select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index df0823f..a9b981a 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -25,7 +25,6 @@ select CACHE_MRC_SETTINGS select PARALLEL_MP select PCR_COMMON_IOSF_1_0 - select SMP select INTEL_DESCRIPTOR_MODE_CAPABLE select COMMON_FADT select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 52092ba..4b95ef8 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -33,7 +33,6 @@ select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 select REG_SCRIPT - select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 21dba0e..da072eb 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -34,7 +34,6 @@ select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 select REG_SCRIPT - select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 27c1084..cdd5ed9 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -47,7 +47,6 @@ select PLATFORM_USES_FSP2_0 select REG_SCRIPT select SA_ENABLE_DPR - select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index fbf56b4..e811cfa 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -33,7 +33,6 @@ select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 select REG_SCRIPT - select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 8e39b77..9617f37 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -38,7 +38,6 @@ select POSTCAR_STAGE select IOAPIC select PARALLEL_MP - select SMP select INTEL_DESCRIPTOR_MODE_CAPABLE select COMMON_FADT select SOC_INTEL_COMMON_BLOCK -- To view, visit https://review.coreboot.org/c/coreboot/+/42091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ac3e30e9f96cd52244b4bae73bafce0564d41e0 Gerrit-Change-Number: 42091 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: mb/x/acpi_tables: Do minor cleanup on includes
by Kyösti Mälkki (Code Review) 26 Jul '20

26 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42865 ) Change subject: mb/x/acpi_tables: Do minor cleanup on includes ...................................................................... mb/x/acpi_tables: Do minor cleanup on includes Change-Id: I7a6ddf95d085490d52e00ade7bac23e8c8849427 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/intel/harcuvar/acpi_tables.c M src/mainboard/ocp/tiogapass/acpi_tables.c M src/mainboard/scaleway/tagada/acpi_tables.c 3 files changed, 1 insertion(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/42865/1 diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index cfe0caa..5040b0b 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -10,8 +10,6 @@ #include <soc/acpi.h> #include <soc/nvs.h> -extern const unsigned char AmlCode[]; - void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c index f6947a2..300e8f6 100644 --- a/src/mainboard/ocp/tiogapass/acpi_tables.c +++ b/src/mainboard/ocp/tiogapass/acpi_tables.c @@ -1,10 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> -#include <intelblocks/acpi.h> -#include <soc/acpi.h> - -extern const unsigned char AmlCode[]; void acpi_create_gnvs(struct global_nvs *gnvs) { diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index cfe0caa..a251d22 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -1,17 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> -#include <device/device.h> -#include <cpu/x86/msr.h> - -#include <intelblocks/acpi.h> -#include <soc/acpi.h> #include <soc/nvs.h> -extern const unsigned char AmlCode[]; - void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); -- To view, visit https://review.coreboot.org/c/coreboot/+/42865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a6ddf95d085490d52e00ade7bac23e8c8849427 Gerrit-Change-Number: 42865 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: src: Drop unused <cpu/x86/smm.h> include
by HAOUAS Elyes (Code Review) 26 Jul '20

26 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42392 ) Change subject: src: Drop unused <cpu/x86/smm.h> include ...................................................................... src: Drop unused <cpu/x86/smm.h> include Change-Id: Id96ddad974a1460a6e6580cee1e45c863761af06 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/smm/cpu_svrstr.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/skylake/romstage/romstage.c 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/42392/1 diff --git a/src/cpu/intel/smm/cpu_svrstr.c b/src/cpu/intel/smm/cpu_svrstr.c index d7e161f..1e63dd2 100644 --- a/src/cpu/intel/smm/cpu_svrstr.c +++ b/src/cpu/intel/smm/cpu_svrstr.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/x86/mp.h> -#include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> #define SMBASE_MSR 0xc20 diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 7979bfd..67aacd9 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -4,7 +4,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> -#include <cpu/x86/smm.h> #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/pmc.h> diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 99f444a..9ae854d 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -4,7 +4,6 @@ #include <arch/symbols.h> #include <assert.h> #include <cpu/x86/msr.h> -#include <cpu/x86/smm.h> #include <cbmem.h> #include <console/console.h> #include <device/pci_def.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/42392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id96ddad974a1460a6e6580cee1e45c863761af06 Gerrit-Change-Number: 42392 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: src: Remove unused 'include <cpu/intel/common/common.h>
by HAOUAS Elyes (Code Review) 26 Jul '20

26 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42394 ) Change subject: src: Remove unused 'include <cpu/intel/common/common.h> ...................................................................... src: Remove unused 'include <cpu/intel/common/common.h> Change-Id: I4d749a32aa50fa2f005e8496983013977742a99b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c 4 files changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/42394/1 diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 6cb11fe..7230213 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -10,7 +10,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <cpu/intel/smm_reloc.h> -#include <cpu/intel/common/common.h> + #include "chip.h" static void init_timer(void) diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 927bebb..8c462f1 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -8,7 +8,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -#include <cpu/intel/common/common.h> #define HIGHEST_CLEVEL 3 static void configure_c_states(void) diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 43d4599..16c6866 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -8,7 +8,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -#include <cpu/intel/common/common.h> #define HIGHEST_CLEVEL 3 static void configure_c_states(void) diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index b81eca4..e2755f8 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -8,7 +8,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -#include <cpu/intel/common/common.h> #define HIGHEST_CLEVEL 3 static void configure_c_states(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/42394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d749a32aa50fa2f005e8496983013977742a99b Gerrit-Change-Number: 42394 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: nb/intel/ironlake/raminit.c: initialize 'reply.command'
by HAOUAS Elyes (Code Review) 25 Jul '20

25 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42461 ) Change subject: nb/intel/ironlake/raminit.c: initialize 'reply.command' ...................................................................... nb/intel/ironlake/raminit.c: initialize 'reply.command' This to silent a bug found using gcc-10. src/northbridge/intel/ironlake/raminit.c: In function 'setup_heci_uma': src/northbridge/intel/ironlake/raminit.c:1805:11: error: 'reply.command' may be used uninitialized in this function [-Werror=maybe-uninitialized] 1805 | if (reply.command != (MKHI_SET_UMA | (1 << 7))) | ~~~~~^~~~~~~~ cc1: all warnings being treated as errors Change-Id: I0d13de549b6d428ac3675ee3f91eb5e42aeb25e8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/42461/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index e85163f..714cc4b 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1781,6 +1781,10 @@ u8 field2; u8 unk3[0x48 - 4 - 1]; } __packed reply; + + /*FIXME: We should not initialize 'reply.command' */ + reply.command = 0; + struct uma_message { u8 group_id; u8 cmd; @@ -1801,7 +1805,6 @@ reply_size = sizeof(reply); if (recv_heci_message(info, (u32 *) & reply, &reply_size) == -1) return; - if (reply.command != (MKHI_SET_UMA | (1 << 7))) die("HECI init failed\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d13de549b6d428ac3675ee3f91eb5e42aeb25e8 Gerrit-Change-Number: 42461 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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