coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

1 participants
2826 discussions

Change in coreboot[master]: [WIP] arch/x86: Combine bootblock linker scripts
by Kyösti Mälkki (Code Review) 28 Jul '20

28 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40786 ) Change subject: [WIP] arch/x86: Combine bootblock linker scripts ...................................................................... [WIP] arch/x86: Combine bootblock linker scripts Change-Id: Ie8629a89fa47a28db63ecc33c631b29ac5a77448 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- D src/arch/x86/id.ld M src/arch/x86/memlayout.ld D src/cpu/intel/fit/fit.ld D src/cpu/x86/16bit/entry16.ld M src/cpu/x86/16bit/reset16.ld 5 files changed, 22 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/40786/1 diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld deleted file mode 100644 index 4bfc007..0000000 --- a/src/arch/x86/id.ld +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -SECTIONS { - . = (CONFIG_X86_RESET_VECTOR - CONFIG_ID_SECTION_OFFSET) + 0x10 - (__id_end - __id_start); - .id (.): { - KEEP(*(.id)) - } -} diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 5e1ef24..707a0fe 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -51,10 +51,5 @@ #if ENV_BOOTBLOCK /* Bootblock specific scripts which provide more SECTION directives. */ -#include <cpu/x86/16bit/entry16.ld> #include <cpu/x86/16bit/reset16.ld> -#include <arch/x86/id.ld> -#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) -#include <cpu/intel/fit/fit.ld> -#endif #endif /* ENV_BOOTBLOCK */ diff --git a/src/cpu/intel/fit/fit.ld b/src/cpu/intel/fit/fit.ld deleted file mode 100644 index 424b8ce..0000000 --- a/src/cpu/intel/fit/fit.ld +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -SECTIONS { - . = 0xffffffc0; - .fit_pointer (.): { - KEEP(*(.fit_pointer)) - } -} diff --git a/src/cpu/x86/16bit/entry16.ld b/src/cpu/x86/16bit/entry16.ld deleted file mode 100644 index 7d23883..0000000 --- a/src/cpu/x86/16bit/entry16.ld +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -gdtptr16_offset = gdtptr16 & 0xffff; -nullidt_offset = nullidt & 0xffff; - -/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with - * Startup IPI message without RAM. - */ -#if CONFIG(SIPI_VECTOR_IN_ROM) -_bogus = ASSERT((_start16bit & 0xfff) == 0, "Symbol _start16bit is not at 4 KiB boundary"); -ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff; -#endif diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index e6a33b6..5da3213 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -1,13 +1,34 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -/* _RESET_VECTOR: typically the top of the ROM */ +gdtptr16_offset = gdtptr16 & 0xffff; +nullidt_offset = nullidt & 0xffff; + +/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with + * Startup IPI message without RAM. + */ +#if CONFIG(SIPI_VECTOR_IN_ROM) +_bogus = ASSERT((_start16bit & 0xfff) == 0, "Symbol _start16bit is not at 4 KiB boundary"); +ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff; +#endif SECTIONS { /* Trigger an error if I have an unuseable start address */ _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); + . = (CONFIG_X86_RESET_VECTOR - CONFIG_ID_SECTION_OFFSET) + 0x10 - (__id_end - __id_start); + .id (.): { + KEEP(*(.id)) + } + +#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) + . = 0xffffffc0; + .fit_pointer (.): { + KEEP(*(.fit_pointer)) + } +#endif + . = CONFIG_X86_RESET_VECTOR; .reset . : { *(.reset); -- To view, visit https://review.coreboot.org/c/coreboot/+/40786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8629a89fa47a28db63ecc33c631b29ac5a77448 Gerrit-Change-Number: 40786 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: Revert "arch|cpu/x86: Add Kconfig option for x86 reset vector"
by Kyösti Mälkki (Code Review) 28 Jul '20

28 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42348 ) Change subject: Revert "arch|cpu/x86: Add Kconfig option for x86 reset vector" ...................................................................... Revert "arch|cpu/x86: Add Kconfig option for x86 reset vector" This partially reverts commit 67910db907fb3d5feacdbfaa40952a88f673795a. The symbol X86_RESET_VECTOR continues to live, for the time being, under soc/amd/picasso. Change-Id: Ib6b2cc2b17133b3207758c72a54abe80fc6356b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Kconfig M src/arch/x86/id.ld M src/arch/x86/memlayout.ld M src/cpu/x86/16bit/reset16.ld 4 files changed, 9 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/42348/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 18c1ed3..35f63ac 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -73,16 +73,6 @@ default n depends on ARCH_X86 && SMP -config X86_RESET_VECTOR - hex - depends on ARCH_X86 - default 0xfffffff0 - help - Specify the location of the x86 reset vector. In traditional devices - this must match the architectural reset vector to produce a bootable - image. Nontraditional designs may use this to position the reset - vector into its desired location. - config RESET_VECTOR_IN_RAM bool depends on ARCH_X86 diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld index ea8d7e9..b69a8dc 100644 --- a/src/arch/x86/id.ld +++ b/src/arch/x86/id.ld @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ SECTIONS { - . = (CONFIG_X86_RESET_VECTOR - CONFIG_ID_SECTION_OFFSET) + 0x10 - (__id_end - __id_start); + . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; .id (.): { KEEP(*(.id)) } diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 12974ca..6f7ac89 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -29,7 +29,7 @@ #include "car.ld" #elif ENV_BOOTBLOCK - BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10, + BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE) #include "car.ld" diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index b90dd04..e00e0b4 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -1,13 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* _RESET_VECTOR: typically the top of the ROM */ +/* + * _ROMTOP : The top of the ROM used where we + * need to put the reset vector. + */ SECTIONS { /* Trigger an error if I have an unuseable start address */ - _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; - _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); - - . = CONFIG_X86_RESET_VECTOR; + _bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); + _ROMTOP = 0xfffffff0; + . = _ROMTOP; .reset . : { *(.reset); . = 15; -- To view, visit https://review.coreboot.org/c/coreboot/+/42348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6b2cc2b17133b3207758c72a54abe80fc6356b5 Gerrit-Change-Number: 42348 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: soc/amd/common: Use ACPIMMIO_GPIO0_BASE in ASL
by Kyösti Mälkki (Code Review) 28 Jul '20

28 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42828 ) Change subject: soc/amd/common: Use ACPIMMIO_GPIO0_BASE in ASL ...................................................................... soc/amd/common: Use ACPIMMIO_GPIO0_BASE in ASL Change-Id: Ia18ee7dcfae3992eb4ecf52c3ebbd8e6daef756a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/acpi/sb_fch.asl M src/soc/amd/stoneyridge/acpi/sb_fch.asl 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/42828/1 diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 00774fd..007df8d 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -34,7 +34,7 @@ ActiveLow, Exclusive, , , IRQR) { 0 } - Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300) } CreateDWordField (Local0, IRQR._INT, IRQN) If (PMOD) { @@ -44,7 +44,7 @@ } If (IRQN == 0x1f) { Return (ResourceTemplate() { - Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300) }) } Else { Return (Local0) diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index 28e29c6..c999b67 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -30,7 +30,7 @@ { Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) { 7 } - Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300) }) Method (_STA, 0x0, NotSerialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/42828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia18ee7dcfae3992eb4ecf52c3ebbd8e6daef756a Gerrit-Change-Number: 42828 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: ACPI S3: Clean up resume path
by Kyösti Mälkki (Code Review) 28 Jul '20

28 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42498 ) Change subject: ACPI S3: Clean up resume path ...................................................................... ACPI S3: Clean up resume path Remove the obscure path in source code, where ACPI S3 resume was prohibited and acpi_resume() would return and continue to BS_WRITE_TABLES. The condition when ACPI S3 would be prohibited needs to be checked early in romstage already. For the time being, there has been little interest to have CMOS option to disable ACPI S3 resume feature. Change-Id: If5105912759427f94f84d46d1a3141aa75cbd6ef Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/acpi_s3.c M src/include/acpi/acpi.h M src/lib/hardwaremain.c 3 files changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/42498/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index d4c697e..fef04ac 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -58,11 +58,6 @@ static void acpi_jump_to_wakeup(void *vector) { - if (!acpi_s3_resume_allowed()) { - printk(BIOS_WARNING, "ACPI: S3 resume not allowed.\n"); - return; - } - /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); @@ -77,7 +72,7 @@ { } -void acpi_resume(void *wake_vec) +void __noreturn acpi_resume(void *wake_vec) { if (CONFIG(HAVE_SMI_HANDLER)) { void *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS); @@ -95,4 +90,6 @@ post_code(POST_OS_RESUME); acpi_jump_to_wakeup(wake_vec); + + die("Failed the jump to wakeup vector\n"); } diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index cd99899..316a191 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -984,7 +984,7 @@ acpi_hest_esd_t *esd, u16 type, void *data, u16 len); /* For ACPI S3 support. */ -void acpi_resume(void *wake_vec); +void __noreturn acpi_resume(void *wake_vec); void mainboard_suspend_resume(void); void *acpi_find_wakeup_vector(void); diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 4276027..ba02807 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -169,7 +169,9 @@ if (CONFIG(HAVE_ACPI_RESUME)) { arch_bootstate_coreboot_exit(); acpi_resume(wake_vector); + /* We will not come back. */ } + die("Failed OS resume\n"); return BS_WRITE_TABLES; } -- To view, visit https://review.coreboot.org/c/coreboot/+/42498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5105912759427f94f84d46d1a3141aa75cbd6ef Gerrit-Change-Number: 42498 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: mb/google/zork: Enable psp_verstage
by Martin Roth (Code Review) 27 Jul '20

27 Jul '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42226 ) Change subject: mb/google/zork: Enable psp_verstage ...................................................................... mb/google/zork: Enable psp_verstage Finally enable psp_verstage for zork. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5 --- M src/mainboard/google/zork/Kconfig A src/mainboard/google/zork/memlayout.ld 2 files changed, 35 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42226/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 9a2e373..aca5640 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -88,8 +88,6 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH - select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE config VBOOT_VBNV_OFFSET hex @@ -122,6 +120,21 @@ depends on USE_OEM_BIN default "" +#TODO: Change these to get the postition from the FMAP file +config PICASSO_FW_A_POSITION + hex + default 0xFF031040 + depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + help + Location of the AMD firmware in the RW_A region. + +config PICASSO_FW_B_POSITION + hex + default 0xFF3CF040 + depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + help + Location of the AMD firmware in the RW_B region + config VARIANT_HAS_FW_CONFIG bool help @@ -134,4 +147,21 @@ help Which board version did FW_CONFIG become valid in CBI. +config VBOOT_STARTS_BEFORE_BOOTBLOCK + bool "PSP verstage" + depends on HAVE_PRE_BOOTBLOCK_VBOOT_SUPPORT + default y if VBOOT + help + Firmware verification happens before the main processor is brought + online. + +config VBOOT_STARTS_IN_BOOTBLOCK + bool "X86 verstage (in bootblock)" + depends on VBOOT && ! VBOOT_STARTS_BEFORE_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + help + Firmware verification happens during the end of or right after the + bootblock. This implies that a static VBOOT2_WORK() buffer must be + allocated in memlayout. + endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/memlayout.ld b/src/mainboard/google/zork/memlayout.ld new file mode 100644 index 0000000..5493e0d --- /dev/null +++ b/src/mainboard/google/zork/memlayout.ld @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/memlayout.ld> -- To view, visit https://review.coreboot.org/c/coreboot/+/42226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5 Gerrit-Change-Number: 42226 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: mb/google/volteer: Create Mudada variant
by Kane Chen (Code Review) 27 Jul '20

27 Jul '20

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42301 ) Change subject: mb/google/volteer: Create Mudada variant ...................................................................... mb/google/volteer: Create Mudada variant Create the Mudada variant of the volteer. BUG=b:158797761 BRANCH=volteer TEST=emerge-volteer coreboot Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I59ce4720e0ffeeeb2c9440bb300686def80211ea --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/mudada/Makefile.inc A src/mainboard/google/volteer/variants/mudada/gpio.c A src/mainboard/google/volteer/variants/mudada/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/mudada/include/variant/ec.h A src/mainboard/google/volteer/variants/mudada/include/variant/gpio.h A src/mainboard/google/volteer/variants/mudada/memory.c A src/mainboard/google/volteer/variants/mudada/memory/Makefile.inc A src/mainboard/google/volteer/variants/mudada/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/mudada/memory/mem_list_variant.txt A src/mainboard/google/volteer/variants/mudada/overridetree.cb 12 files changed, 650 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/42301/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 99a08a3..4092c5a 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -68,6 +68,7 @@ string default "Halvor" if BOARD_GOOGLE_HALVOR default "Malefor" if BOARD_GOOGLE_MALEFOR + default "Mudada" if BOARD_GOOGLE_MUDADA default "Ripto" if BOARD_GOOGLE_RIPTO default "Terrador" if BOARD_GOOGLE_TERRADOR default "Trondo" if BOARD_GOOGLE_TRONDO @@ -100,6 +101,7 @@ string default "halvor" if BOARD_GOOGLE_HALVOR default "malefor" if BOARD_GOOGLE_MALEFOR + default "mudada" if BOARD_GOOGLE_MUDADA default "ripto" if BOARD_GOOGLE_RIPTO default "terrador" if BOARD_GOOGLE_TERRADOR default "trondo" if BOARD_GOOGLE_TRONDO diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 6920aaf..a680735 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -8,6 +8,10 @@ bool "-> Malefor" select BOARD_GOOGLE_BASEBOARD_VOLTEER +config BOARD_GOOGLE_MUDADA + bool "-> Mudada" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + config BOARD_GOOGLE_RIPTO bool "-> Ripto" select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/mudada/Makefile.inc b/src/mainboard/google/volteer/variants/mudada/Makefile.inc new file mode 100644 index 0000000..343c7db --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/mudada/gpio.c b/src/mainboard/google/volteer/variants/mudada/gpio.c new file mode 100644 index 0000000..0e33926 --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/gpio.c @@ -0,0 +1,438 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { + /* A0 thru A6 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_CLK ==> ESPI_CLK */ + /* A6 : ESPI_RESET# ==> NC(TP764) */ + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A9 : I2S2_TXD ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_A9, NONE, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A11 : PMC_I2C_SDA ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A11, 1, DEEP), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A14 : USB_OC1# ==> USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_OC2# ==> USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B0 : CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : CPU_GP2 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B4 : CPU_GP3 ==> NC */ + PAD_NC(GPP_B4, NONE), + /* B5 : ISH_I2C0_CVF_SDA == NC */ + PAD_NC(GPP_B5, NONE), + /* B6 : ISH_I2C0_CVF_SCL == NC */ + PAD_NC(GPP_B6, NONE), + /* B7 : ISH_12C1_SDA ==> NC */ + PAD_NC(GPP_B7, NONE), + /* B8 : ISH_I2C1_SCL ==> NC */ + PAD_NC(GPP_B8, NONE), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B12 : SLP_S0# ==> SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR ==> GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> NC */ + PAD_NC(GPP_B19, NONE), + /* B20 : GSPI1_CLK ==> NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : GSPI1_MISO ==> NC */ + PAD_NC(GPP_B21, NONE), + /* B22 : GSPI1_MOSI ==> NC */ + PAD_NC(GPP_B22, NONE), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_NC(GPP_B23, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> NOT USED */ + PAD_NC(GPP_C1, NONE), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, NONE), + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_NC(GPP_C5, NONE), + /* C6 : SML1CLK ==> EC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C6, NONE, PLTRST, LEVEL, INVERT), + /* C7 : SML1DATA ==> NC */ + PAD_NC(GPP_C7, NONE), + /* C8 : UART0_RXD ==> UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C11 : UART0_CTS# ==> NC */ + PAD_NC(GPP_C11, NONE), + /* C12 : UART1_RXD ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_C12, NONE, DEEP), + /* C13 : UART1_TXD ==> NC */ + PAD_NC(GPP_C13, NONE), + /* C14 : UART1_RTS# ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_C14, NONE, DEEP), + /* C15 : UART1_CTS# ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_C15, NONE, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> NC */ + PAD_NC(GPP_C20, NONE), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> NC */ + PAD_NC(GPP_C22, NONE), + /* C23 : UART2_CTS# ==> NC */ + PAD_NC(GPP_C23, NONE), + + /* D0 : ISH_GP0 ==> NC */ + PAD_NC(GPP_D0, NONE), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC(GPP_D1, NONE), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC(GPP_D2, NONE), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D4 : IMGCLKOUT0 ==> NC */ + PAD_NC(GPP_D4, NONE), + /* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : SRCCLKREQ1# ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D7 : SRCCLKREQ2# ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF7), + /* D11 : ISH_SPI_MISO ==> NC */ + PAD_NC(GPP_D11, NONE), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D15 : ISH_UART0_RTS# ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_D15, NONE, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* D18 : ISH_GP5 ==> NC */ + PAD_NC(GPP_D18, NONE), + /* D19 : I2S_MCLK1 ==> I2S_MCLK1 */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* E0 : SATAXPCIE0 ==> USB_A1_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), + /* E1 : SPI1_IO2 ==> NC */ + PAD_NC(GPP_E1, NONE), + /* E2 : SPI1_IO3 ==> NC */ + PAD_NC(GPP_E2, NONE), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E5 : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ + PAD_NC(GPP_E6, NONE), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF6), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : SPI1_MISO_IO1 ==> NC */ + PAD_NC(GPP_E12, NONE), + /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF6), + /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> NC */ + PAD_NC(GPP_E17, NONE), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */ + PAD_NC(GPP_E23, NONE), + + /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP ==> NCV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* F2 : I2S2_TXD ==> CNV_RGI_DT_STRAP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : I2S2_RXD ==> CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, NONE), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F9 : Reserved ==> NC */ + PAD_NC(GPP_F9, NONE), + /* F10 : GPPF10_STRAP */ + PAD_NC(GPP_F10, DN_20K), + /* F11 : GPPF11_THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F14 : GSXDIN ==> NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : GSXCLK ==> NC */ + PAD_NC(GPP_F16, NONE), + /* F17 : WWAN_RF_DISABLE_ODL == NC */ + PAD_NC(GPP_F17, NONE), + /* F18 : THC1_SPI2_INT# ==> NC */ + PAD_NC(GPP_F18, NONE), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EXT_PWR_GATE# ==> EXT_PWR_GATE_L */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EXT_PWR_GATE2# ==> EXT_PWR_GATE2_L */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : V1P05_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, NONE), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, NONE), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, NONE), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : I2C2_SDA ==> PCH_I2C2_MISC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C2_SCL ==> PCH_I2C2_MISC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : I2C3_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : I2C3_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + /* H8 : I2C4_SDA ==> PCB_ID0 */ + PAD_CFG_GPI(GPP_H8, NONE, DEEP), + /* H9 : I2C4_SCL ==> PCB_ID1 */ + PAD_CFG_GPI(GPP_H9, NONE, DEEP), + /* H10 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H10, NONE), + /* H11 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H11, NONE), + /* H12 : M2_SKT2_CFG0 ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H14 : M2_SKT2_CFG2 # ==> NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : M2_SKT2_CFG3 # ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : IMGCLKOUT1 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : IMGCLKOUT4 ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD0: BATLOW# ==> BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4: SLP_S3# ==> SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SLP_S4# ==> SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SLP_A# ==> SLP_A_L */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: GPD7_STRAP */ + PAD_CFG_GPI(GPD7, DN_20K, DEEP), + /* GPD8: SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: SLP_S5# ==> SLP_S5_L */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: LANPHYC ==> NC */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/mudada/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/mudada/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..726e381 --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/include/variant/acpi/dptf.asl @@ -0,0 +1,7 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/volteer/variants/mudada/include/variant/ec.h b/src/mainboard/google/volteer/variants/mudada/include/variant/ec.h new file mode 100644 index 0000000..6e12175 --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/include/variant/ec.h @@ -0,0 +1,12 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/mudada/include/variant/gpio.h b/src/mainboard/google/volteer/variants/mudada/include/variant/gpio.h new file mode 100644 index 0000000..c7e4605 --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/include/variant/gpio.h @@ -0,0 +1,12 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/volteer/variants/mudada/memory.c b/src/mainboard/google/volteer/variants/mudada/memory.c new file mode 100644 index 0000000..d0bfcb5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/memory.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +static const struct lpddr4x_cfg malefor_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ + { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ + { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct lpddr4x_cfg *variant_memory_params(void) +{ + return &malefor_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/mudada/memory/Makefile.inc b/src/mainboard/google/volteer/variants/mudada/memory/Makefile.inc new file mode 100644 index 0000000..7aa547b --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += spd-2.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/mudada/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/mudada/memory/dram_id.generated.txt new file mode 100644 index 0000000..b5bd3ef --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/memory/dram_id.generated.txt @@ -0,0 +1,5 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +H9HCNNNBKMMLXR-NEE 0 (0000) +H9HCNNNCPMMLXR-NEE 2 (0010) diff --git a/src/mainboard/google/volteer/variants/mudada/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/mudada/memory/mem_list_variant.txt new file mode 100644 index 0000000..b99b811 --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/memory/mem_list_variant.txt @@ -0,0 +1,4 @@ +MT53E512M32D2NP-046 WT:E +MT53E1G32D2NP-046 WT:A +H9HCNNNBKMMLXR-NEE +H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/mudada/overridetree.cb b/src/mainboard/google/volteer/variants/mudada/overridetree.cb new file mode 100644 index 0000000..9e5ef4b --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/overridetree.cb @@ -0,0 +1,92 @@ +chip soc/intel/tigerlake + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98357_ALC5682I_I2S + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S + end + end + end + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO MAX98357_ALC5682I_I2S + end + end + chip drivers/intel/soundwire + device generic 0 on + probe AUDIO MAX98373_ALC5682_SNDW + chip drivers/soundwire/alc5682 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 1 ID 3 + register "desc" = ""Left Speaker Amp"" + device generic 1.3 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 1 ID 7 + register "desc" = ""Right Speaker Amp"" + device generic 1.7 on end + end + end + end + end + device pci 1f.2 hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/con + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 on end + end + chip drivers/intel/pmc_mux/con + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end # PMC + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/42301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59ce4720e0ffeeeb2c9440bb300686def80211ea Gerrit-Change-Number: 42301 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

10 76

Change in coreboot[master]: src/soc: Use macro
by HAOUAS Elyes (Code Review) 27 Jul '20

27 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42718 ) Change subject: src/soc: Use macro ...................................................................... src/soc: Use macro Use defined macro for space_id. Change-Id: I5be96a420a204050e065b36efecffc7cb5e3a560 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c 12 files changed, 59 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/42718/1 diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 595e6a2..5bdaf2c 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -150,7 +150,7 @@ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 13acf86..6fbe17f 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -169,7 +169,7 @@ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - fadt->reset_reg.space_id = 1; + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; @@ -177,42 +177,42 @@ fadt->reset_reg.addrh = 0; fadt->reset_value = 6; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; - fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1b_evt_blk.bit_width = 0; fadt->x_pm1b_evt_blk.bit_offset = 0; fadt->x_pm1b_evt_blk.access_size = 0; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1b_cnt_blk.bit_width = 0; fadt->x_pm1b_cnt_blk.bit_offset = 0; fadt->x_pm1b_cnt_blk.access_size = 0; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2A_CNT_BLK; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; @@ -225,14 +225,14 @@ * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which * seems to work fine on Linux 5.0 and Windows 10. */ - fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; fadt->x_gpe0_blk.addrh = 0x0; - fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.access_size = 0; diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 53379a0..43b9735 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -173,7 +173,7 @@ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - fadt->reset_reg.space_id = 1; + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; @@ -181,42 +181,42 @@ fadt->reset_reg.addrh = 0; fadt->reset_value = 6; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; - fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1b_evt_blk.bit_width = 0; fadt->x_pm1b_evt_blk.bit_offset = 0; fadt->x_pm1b_evt_blk.access_size = 0; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1b_cnt_blk.bit_width = 0; fadt->x_pm1b_cnt_blk.bit_offset = 0; fadt->x_pm1b_cnt_blk.access_size = 0; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2A_CNT_BLK; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; @@ -229,14 +229,14 @@ * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which * seems to work fine on Linux 5.0 and Windows 10. */ - fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; fadt->x_gpe0_blk.addrh = 0x0; - fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.access_size = 0; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 0d83c01..cd15aa9 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -224,7 +224,7 @@ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - fadt->reset_reg.space_id = 1; + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; @@ -232,42 +232,42 @@ fadt->reset_reg.addrh = 0; fadt->reset_value = 6; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; - fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1b_evt_blk.bit_width = 0; fadt->x_pm1b_evt_blk.bit_offset = 0; fadt->x_pm1b_evt_blk.access_size = 0; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1b_cnt_blk.bit_width = 0; fadt->x_pm1b_cnt_blk.bit_offset = 0; fadt->x_pm1b_cnt_blk.access_size = 0; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; @@ -288,7 +288,7 @@ fadt->x_gpe0_blk.addrh = 0; - fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.access_size = 0; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index c041eb0..d14130f 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -166,7 +166,7 @@ fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->pm_tmr_len = 4; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 4e4906c..58dbcda 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -126,26 +126,26 @@ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - fadt->reset_reg.space_id = 1; + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.addrl = RST_CNT; fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_value = RST_CPU | SYS_RST; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; /* * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. @@ -160,7 +160,7 @@ fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0; - fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; } unsigned long southbridge_write_acpi_tables(const struct device *device, diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 796e770..e14a5aa 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -162,7 +162,7 @@ fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->pm_tmr_len = 4; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 88ec5fe..63c8fb0 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -163,7 +163,7 @@ fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->pm_tmr_len = 4; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = 0; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 6ff836a..3636d45 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -271,7 +271,7 @@ if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; - fadt->reset_reg.space_id = 1; + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; @@ -279,42 +279,42 @@ fadt->reset_reg.addrh = 0; fadt->reset_value = 6; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; - fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1b_evt_blk.bit_width = 0; fadt->x_pm1b_evt_blk.bit_offset = 0; fadt->x_pm1b_evt_blk.access_size = 0; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1b_cnt_blk.bit_width = 0; fadt->x_pm1b_cnt_blk.bit_offset = 0; fadt->x_pm1b_cnt_blk.access_size = 0; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; @@ -334,7 +334,7 @@ fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0; - fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.access_size = 0; diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 0991134..edeb55e 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -163,7 +163,7 @@ fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->pm_tmr_len = 4; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index abaa453..99c58e7 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -302,25 +302,25 @@ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_RESET_REGISTER | ACPI_FADT_PLATFORM_CLOCK; - fadt->reset_reg.space_id = 1; + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.addrl = RST_CNT; fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_value = RST_CPU | SYS_RST; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 3da2025..128122c 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -375,7 +375,7 @@ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - fadt->reset_reg.space_id = 1; + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; @@ -383,42 +383,42 @@ fadt->reset_reg.addrh = 0; fadt->reset_value = 6; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; - fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1b_evt_blk.bit_width = 0; fadt->x_pm1b_evt_blk.bit_offset = 0; fadt->x_pm1b_evt_blk.access_size = 0; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1b_cnt_blk.bit_width = 0; fadt->x_pm1b_cnt_blk.bit_offset = 0; fadt->x_pm1b_cnt_blk.access_size = 0; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; @@ -432,7 +432,7 @@ fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0; - fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.access_size = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/42718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be96a420a204050e065b36efecffc7cb5e3a560 Gerrit-Change-Number: 42718 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: [WIP]mb/google/volteer: Disable CPU PCIE in FSP
by Shaunak Saha (Code Review) 26 Jul '20

26 Jul '20

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42557 ) Change subject: [WIP]mb/google/volteer: Disable CPU PCIE in FSP ...................................................................... [WIP]mb/google/volteer: Disable CPU PCIE in FSP Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46 --- M src/soc/intel/tigerlake/romstage/fsp_params.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42557/1 diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index f7956c8..b18cb53 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -196,6 +196,8 @@ /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + + m_cfg->CpuPcieRpEnableMask = 0; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/42557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46 Gerrit-Change-Number: 42557 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

7 27

Change in coreboot[master]: cpu/intel/car/romstage.c: Remove unused <bootblock_common.h>
by HAOUAS Elyes (Code Review) 26 Jul '20

26 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42350 ) Change subject: cpu/intel/car/romstage.c: Remove unused <bootblock_common.h> ...................................................................... cpu/intel/car/romstage.c: Remove unused <bootblock_common.h> Change-Id: Ib47497cf8576063d42bc4a1dd2cc2e0fc56868d3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/car/romstage.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/42350/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index a955d8c..4b4a4ab 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -2,7 +2,6 @@ #include <arch/cpu.h> #include <arch/romstage.h> -#include <bootblock_common.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <arch/symbols.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/42350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib47497cf8576063d42bc4a1dd2cc2e0fc56868d3 Gerrit-Change-Number: 42350 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/amd/common/block/psp/psp_smm.c: Add missing <string.h>
by HAOUAS Elyes (Code Review) 26 Jul '20

26 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42342 ) Change subject: soc/amd/common/block/psp/psp_smm.c: Add missing <string.h> ...................................................................... soc/amd/common/block/psp/psp_smm.c: Add missing <string.h> Change-Id: Idc1d72e92c97cd5139ae7439aadb575ef011129a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/common/block/psp/psp_smm.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/42342/1 diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index b0f9a41..e30897a 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -8,6 +8,8 @@ #include <console/console.h> #include <amdblocks/psp.h> #include <soc/iomap.h> +#include <string.h> + #include "psp_def.h" #define C2P_BUFFER_MAXSIZE 0xc00 /* Core-to-PSP buffer */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc1d72e92c97cd5139ae7439aadb575ef011129a Gerrit-Change-Number: 42342 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 6

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2020