Change in coreboot[master]: mb/supermicro/x11-lga1151: 3/5 Rewrite pad config using intelp2m
by Maxim Polyakov (Code Review) 25 Jul '20
by Maxim Polyakov (Code Review) 25 Jul '20
25 Jul '20
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42918 )
Change subject: mb/supermicro/x11-lga1151: 3/5 Rewrite pad config using intelp2m
......................................................................
mb/supermicro/x11-lga1151: 3/5 Rewrite pad config using intelp2m
Fixes some bit fields to convert to target macros PAD_CFG_*() macros.
Change-Id: I291f5f0f34505c466b610aa4049c8cc35937d140
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
2 files changed, 54 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/42918/1
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
index 53b1630..d8a1210 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
@@ -71,7 +71,7 @@
/* GPP_A12 - GPIO */
/* PAD_CFG_GPO(GPP_A12, 1, PLTRST), */
_PAD_CFG_STRUCT(GPP_A12,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | 1, 0),
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
/* GPP_A13 - SUSWARN# */
/* PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), */
@@ -158,7 +158,7 @@
/* GPP_B6 - GPIO */
/* PAD_NC(GPP_B6, NONE), */
_PAD_CFG_STRUCT(GPP_B6,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B7 - GPIO */
/* PAD_NC(GPP_B7, NONE), */
@@ -300,7 +300,7 @@
/* GPP_C14 - GPIO */
/* PAD_NC(GPP_C14, NONE), */
_PAD_CFG_STRUCT(GPP_C14,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C15 - GPIO */
/* PAD_NC(GPP_C15, NONE), */
@@ -346,12 +346,12 @@
/* GPP_C23 - GPIO */
/* PAD_NC(GPP_C23, NONE), */
_PAD_CFG_STRUCT(GPP_C23,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D0 - GPIO */
/* PAD_NC(GPP_D0, NONE), */
_PAD_CFG_STRUCT(GPP_D0,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D1 - GPIO */
/* PAD_CFG_GPO(GPP_D1, 1, DEEP), */
@@ -563,7 +563,8 @@
/* GPP_F5 - GPIO */
/* PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), */
_PAD_CFG_STRUCT(GPP_F5,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_TRIG(LEVEL) |
+ PAD_BUF(TX_DISABLE), 0),
/* GPP_F6 - GPIO */
/* PAD_CFG_GPO(GPP_F6, 1, PLTRST), */
@@ -898,12 +899,12 @@
/* GPD0 - GPIO */
/* PAD_NC(GPD0, NONE), */
_PAD_CFG_STRUCT(GPD0,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD1 - GPIO */
/* PAD_NC(GPD1, NONE), */
_PAD_CFG_STRUCT(GPD1,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD2 - LAN_WAKE# */
/* PAD_CFG_NF(GPD2, NONE, PWROK, NF1), */
@@ -933,7 +934,7 @@
/* GPD7 - GPIO */
/* PAD_NC(GPD7, NONE), */
_PAD_CFG_STRUCT(GPD7,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD8 - SUSCLK */
/* PAD_CFG_NF(GPD8, NONE, PWROK, NF1), */
@@ -943,17 +944,17 @@
/* GPD9 - GPIO */
/* PAD_NC(GPD9, NONE), */
_PAD_CFG_STRUCT(GPD9,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD10 - GPIO */
/* PAD_NC(GPD10, NONE), */
_PAD_CFG_STRUCT(GPD10,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD11 - GPIO */
/* PAD_NC(GPD11, NONE), */
_PAD_CFG_STRUCT(GPD11,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_I0 - DDPB_HPD0 */
/* PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), */
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
index 4659418..eee6dee 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
@@ -73,7 +73,7 @@
/* GPP_A12 - GPIO */
/* PAD_NC(GPP_A12, NONE), */
_PAD_CFG_STRUCT(GPP_A12,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_A13 - SUSWARN#/SUSPWRDNACK */
/* PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), */
@@ -133,13 +133,13 @@
/* GPP_B0 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_B0, 1, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_B0,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_B1 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_B1, 1, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_B1,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_B2 - GPIO */
@@ -165,7 +165,7 @@
/* GPP_B6 - GPIO */
/* PAD_NC(GPP_B6, NONE), */
_PAD_CFG_STRUCT(GPP_B6,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B7 - GPIO */
/* PAD_NC(GPP_B7, NONE), */
@@ -190,7 +190,7 @@
/* GPP_B11 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_B11,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_B12 - SLP_S0# */
@@ -236,7 +236,7 @@
/* GPP_B20 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_B20, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_B20,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_B21 - GPIO */
@@ -284,7 +284,7 @@
/* GPP_C5 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_C5, 1, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_C5,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_C6 - SML1CLK (RESERVED) */
@@ -333,7 +333,7 @@
/* GPP_C14 - GPIO */
/* PAD_NC(GPP_C14, NONE), */
_PAD_CFG_STRUCT(GPP_C14,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C15 - GPIO */
/* PAD_NC(GPP_C15, NONE), */
@@ -374,24 +374,24 @@
/* PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_C22,
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE),
- PAD_PULL(20K_PU) | PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_PULL(20K_PU)),
/* GPP_C23 - GPIO */
/* PAD_NC(GPP_C23, NONE), */
_PAD_CFG_STRUCT(GPP_C23,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPIO Group GPP_D */
/* GPP_D0 - GPIO */
/* PAD_NC(GPP_D0, NONE), */
_PAD_CFG_STRUCT(GPP_D0,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D1 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_D1,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_D2 - GPIO */
@@ -408,7 +408,7 @@
/* GPP_D4 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_D4,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE),
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_D5 - GPIO */
@@ -479,13 +479,13 @@
/* GPP_D18 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_D18,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_D19 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_D19,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_D20 - GPIO */
@@ -496,7 +496,7 @@
/* GPP_D21 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_D21,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_D22 - GPIO */
@@ -608,25 +608,25 @@
/* GPP_F5 - GPIO */
/* PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), */
_PAD_CFG_STRUCT(GPP_F5,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) |
+ PAD_BUF(TX_DISABLE), 0),
/* GPP_F6 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_F6,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_F7 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_F7,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_F8 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_F8,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_F9 - GPIO */
@@ -703,7 +703,7 @@
/* GPP_F23 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, PWROK, NONE), */
_PAD_CFG_STRUCT(GPP_F23,
- PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_G */
@@ -842,7 +842,7 @@
/* GPP_H0 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_H0,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H1 - GPIO */
@@ -854,13 +854,13 @@
/* GPP_H2 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_H2,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H3 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H3, 1, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_H3,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H4 - GPIO */
@@ -872,31 +872,31 @@
/* GPP_H5 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H5, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H5,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H6 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H6, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H6,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H7 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H7, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H7,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H8 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H8, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H8,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H9 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H9, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H9,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H10 - SML2CLK */
@@ -947,31 +947,31 @@
/* GPP_H19 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H19, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H19,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H20 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H20, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H20,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H21 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H21, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H21,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H22 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H22, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H22,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H23 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H23, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H23,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_I */
@@ -1036,12 +1036,12 @@
/* GPD0 - GPIO */
/* PAD_NC(GPD0, NONE), */
_PAD_CFG_STRUCT(GPD0,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD1 - GPIO */
/* PAD_NC(GPD1, NONE), */
_PAD_CFG_STRUCT(GPD1,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD2 - LAN_WAKE# */
/* PAD_CFG_NF(GPD2, NONE, PWROK, NF1), */
@@ -1071,7 +1071,7 @@
/* GPD7 - GPIO */
/* PAD_NC(GPD7, NONE), */
_PAD_CFG_STRUCT(GPD7,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD8 - SUSCLK */
/* PAD_CFG_NF(GPD8, NONE, PWROK, NF1), */
@@ -1081,17 +1081,17 @@
/* GPD9 - GPIO */
/* PAD_NC(GPD9, NONE), */
_PAD_CFG_STRUCT(GPD9,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD10 - GPIO */
/* PAD_NC(GPD10, NONE), */
_PAD_CFG_STRUCT(GPD10,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD11 - GPIO */
/* PAD_NC(GPD11, NONE), */
_PAD_CFG_STRUCT(GPD11,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
};
/* Early pad configuration in romstage. */
--
To view, visit https://review.coreboot.org/c/coreboot/+/42918
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I291f5f0f34505c466b610aa4049c8cc35937d140
Gerrit-Change-Number: 42918
Gerrit-PatchSet: 1
Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-MessageType: newchange
3
16
Change in coreboot[master]: mb/supermicro/x11-lga1151: 2/5 Rewrite pad config using intelp2m
by Maxim Polyakov (Code Review) 25 Jul '20
by Maxim Polyakov (Code Review) 25 Jul '20
25 Jul '20
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42917 )
Change subject: mb/supermicro/x11-lga1151: 2/5 Rewrite pad config using intelp2m
......................................................................
mb/supermicro/x11-lga1151: 2/5 Rewrite pad config using intelp2m
This patch excludes bit fields that must be ignored (1,2) in order
to convert current macros to target PAD_CFG_*() macros. The following
commands were used for this:
./intelp2m -ii -adv -ign -t 1 -p snr -file ../../src/mainboard/
supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
/intelp2m -ii -adv -ign -t 1 -p snr -file ../../src/mainboard/
supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
(1) implement reserved 3h as setting 0h for Pad Reset Config;
(2) ignore RX Level/Edge Configuration (bit 26:25) and RX/TX Buffer
Disable (bit 9:8) for the native function, because it does not affect
the pad in this mode.
Change-Id: Icdf366a8d416598cec5afcb9a0fae6bf7ecd7ba0
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
2 files changed, 282 insertions(+), 443 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/42917/1
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
index 92c877f..53b1630 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
@@ -11,62 +11,62 @@
/* GPP_A0 - RCIN# */
/* PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A0,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A1 - LAD0 */
/* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A1,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A2 - LAD1 */
/* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A2,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A3 - LAD2 */
/* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A3,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A4 - LAD3 */
/* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A4,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A5 - LFRAME# */
/* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A5,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A6 - SERIRQ */
/* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A6,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A7 - PIRQA# */
/* PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A7,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A8 - CLKRUN# */
/* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A8,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A9 - CLKOUT_LPC0 */
/* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A9,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A10 - CLKOUT_LPC1 */
/* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A10,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A11 - PME# */
/* PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A11,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A12 - GPIO */
/* PAD_CFG_GPO(GPP_A12, 1, PLTRST), */
@@ -76,22 +76,22 @@
/* GPP_A13 - SUSWARN# */
/* PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A13,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A14 - SUS_STAT# */
/* PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A14,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A15 - SUS_ACK# */
/* PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A15,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A16 - CLKOUT_48 */
/* PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A16,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A17 - GPIO */
/* PAD_NC(GPP_A17, NONE), */
@@ -148,37 +148,37 @@
/* GPP_B4 - GPIO */
/* PAD_NC(GPP_B4, NONE), */
_PAD_CFG_STRUCT(GPP_B4,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B5 - GPIO */
/* PAD_NC(GPP_B5, NONE), */
_PAD_CFG_STRUCT(GPP_B5,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B6 - GPIO */
/* PAD_NC(GPP_B6, NONE), */
_PAD_CFG_STRUCT(GPP_B6,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B7 - GPIO */
/* PAD_NC(GPP_B7, NONE), */
_PAD_CFG_STRUCT(GPP_B7,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B8 - GPIO */
/* PAD_NC(GPP_B8, NONE), */
_PAD_CFG_STRUCT(GPP_B8,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B9 - GPIO */
/* PAD_NC(GPP_B9, NONE), */
_PAD_CFG_STRUCT(GPP_B9,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B10 - GPIO */
/* PAD_NC(GPP_B10, NONE), */
_PAD_CFG_STRUCT(GPP_B10,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B11 - GPIO */
/* PAD_CFG_GPO(GPP_B11, 0, DEEP), */
@@ -188,17 +188,17 @@
/* GPP_B12 - SLP_S0# */
/* PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_B12,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B13 - PLTRST# */
/* PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_B13,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B14 - SPKR */
/* PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), */
_PAD_CFG_STRUCT(GPP_B14,
- PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST), 0),
/* GPP_B15 - GPIO */
/* PAD_NC(GPP_B15, NONE), */
@@ -243,7 +243,7 @@
/* GPP_B23 - PCHHOT# */
/* PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), */
_PAD_CFG_STRUCT(GPP_B23,
- PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF2) | PAD_RESET(DEEP), 0),
/* GPP_C0 - RESERVED */
@@ -270,7 +270,7 @@
/* GPP_C8 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_C8,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_C9 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), */
@@ -280,7 +280,7 @@
/* GPP_C10 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_C10,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_C11 - GPIO */
/* PAD_NC(GPP_C11, NONE), */
@@ -300,7 +300,7 @@
/* GPP_C14 - GPIO */
/* PAD_NC(GPP_C14, NONE), */
_PAD_CFG_STRUCT(GPP_C14,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C15 - GPIO */
/* PAD_NC(GPP_C15, NONE), */
@@ -340,18 +340,18 @@
/* GPP_C22 - GPIO */
/* PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_C22,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE),
PAD_PULL(20K_PU)),
/* GPP_C23 - GPIO */
/* PAD_NC(GPP_C23, NONE), */
_PAD_CFG_STRUCT(GPP_C23,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D0 - GPIO */
/* PAD_NC(GPP_D0, NONE), */
_PAD_CFG_STRUCT(GPP_D0,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D1 - GPIO */
/* PAD_CFG_GPO(GPP_D1, 1, DEEP), */
@@ -361,7 +361,7 @@
/* GPP_D2 - GPIO */
/* PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), */
_PAD_CFG_STRUCT(GPP_D2,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE),
PAD_PULL(20K_PU)),
/* GPP_D3 - GPIO */
@@ -462,7 +462,7 @@
/* GPP_D22 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PWROK, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_D22,
- PAD_FUNC(GPIO) | (3 << 30) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_D23 - GPIO */
/* PAD_NC(GPP_D23, NONE), */
@@ -472,7 +472,7 @@
/* GPP_E0 - SATAXPCIE0 */
/* PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E0,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E1 - GPIO */
/* PAD_NC(GPP_E1, NONE), */
@@ -502,7 +502,7 @@
/* GPP_E6 - GPIO */
/* PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), */
_PAD_CFG_STRUCT(GPP_E6,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1),
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE),
PAD_PULL(20K_PU)),
/* GPP_E7 - GPIO */
@@ -513,27 +513,27 @@
/* GPP_E8 - SATA_LED# */
/* PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E8,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E9 - USB_OC0# */
/* PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E9,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E10 - USB_OC1# */
/* PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E10,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E11 - USB_OC2# */
/* PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E11,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E12 - USB_OC3# */
/* PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E12,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F0 - GPIO */
/* PAD_NC(GPP_F0, NONE), */
@@ -563,7 +563,7 @@
/* GPP_F5 - GPIO */
/* PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), */
_PAD_CFG_STRUCT(GPP_F5,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0),
/* GPP_F6 - GPIO */
/* PAD_CFG_GPO(GPP_F6, 1, PLTRST), */
@@ -583,27 +583,27 @@
/* GPP_F9 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_F9,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_F10 - SATA_SCLOCK */
/* PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F10,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F11 - SATA_SLOAD */
/* PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F11,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F12 - SATA_SDATAOUT1 */
/* PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F12,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F13 - SATA_SDATAOUT2 */
/* PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F13,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F14 - GPIO */
/* PAD_NC(GPP_F14, NONE), */
@@ -613,12 +613,12 @@
/* GPP_F15 - USB_OC4# */
/* PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F15,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F16 - USB_OC5# */
/* PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F16,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F17 - GPIO */
/* PAD_NC(GPP_F17, NONE), */
@@ -653,7 +653,7 @@
/* GPP_F23 - GPIO */
/* PAD_CFG_GPO(GPP_F23, 0, PWROK), */
_PAD_CFG_STRUCT(GPP_F23,
- PAD_FUNC(GPIO) | (3 << 30) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
/* GPP_G0 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI), */
@@ -668,12 +668,12 @@
/* GPP_G2 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_G2,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_G3 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_G3,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_G4 - GPIO */
/* PAD_NC(GPP_G4, NONE), */
@@ -728,7 +728,7 @@
/* GPP_G14 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_G14,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_G15 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, ACPI), */
@@ -748,12 +748,12 @@
/* GPP_G18 - NMI# */
/* PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_G18,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_G19 - SMI# */
/* PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_G19,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_G20 - GPIO */
/* PAD_NC(GPP_G20, NONE), */
@@ -783,7 +783,7 @@
/* GPP_H1 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_H1,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_H2 - GPIO */
/* PAD_CFG_GPO(GPP_H2, 1, DEEP), */
@@ -793,12 +793,12 @@
/* GPP_H3 - SRCCLKREQ9# */
/* PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H3,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H4 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_H4,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_H5 - GPIO */
/* PAD_CFG_GPO(GPP_H5, 1, PLTRST), */
@@ -828,12 +828,12 @@
/* GPP_H10 - SML2CLK */
/* PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H10,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H11 - SML2DATA */
/* PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H11,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H12 - GPIO */
/* PAD_NC(GPP_H12, NONE), */
@@ -843,12 +843,12 @@
/* GPP_H13 - SML3CLK */
/* PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H13,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H14 - SML3DATA */
/* PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H14,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H15 - GPIO */
/* PAD_NC(GPP_H15, NONE), */
@@ -858,12 +858,12 @@
/* GPP_H16 - SML4CLK */
/* PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H16,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H17 - SML4DATA */
/* PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H17,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H18 - GPIO */
/* PAD_NC(GPP_H18, NONE), */
@@ -908,37 +908,37 @@
/* GPD2 - LAN_WAKE# */
/* PAD_CFG_NF(GPD2, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD2,
- PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1), 0),
/* GPD3 - PWRBTN# */
/* PAD_CFG_NF(GPD3, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD3,
- PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1), 0),
/* GPD4 - SLP_S3# */
/* PAD_CFG_NF(GPD4, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD4,
- PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1), 0),
/* GPD5 - SLP_S4# */
/* PAD_CFG_NF(GPD5, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD5,
- PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1), 0),
/* GPD6 - SLP_A# */
/* PAD_CFG_NF(GPD6, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD6,
- PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1), 0),
/* GPD7 - GPIO */
/* PAD_NC(GPD7, NONE), */
_PAD_CFG_STRUCT(GPD7,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD8 - SUSCLK */
/* PAD_CFG_NF(GPD8, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD8,
- PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1), 0),
/* GPD9 - GPIO */
/* PAD_NC(GPD9, NONE), */
@@ -958,22 +958,22 @@
/* GPP_I0 - DDPB_HPD0 */
/* PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I0,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I1 - DDPC_HPD1 */
/* PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I1,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I2 - DDPD_HPD2 */
/* PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I2,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I3 - DDPE_HPD3 */
/* PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), */
_PAD_CFG_STRUCT(GPP_I3,
- PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST), 0),
/* GPP_I4 - GPIO */
/* PAD_NC(GPP_I4, NONE), */
@@ -983,32 +983,32 @@
/* GPP_I5 - DDPB_CTRLCLK */
/* PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I5,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I6 - DDPB_CTRLDATA */
/* PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I6,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I7 - DDPC_CTRLCLK */
/* PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I7,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I8 - DDPC_CTRLDATA */
/* PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I8,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I9 - DDPD_CTRLCLK */
/* PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I9,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I10 - DDPD_CTRLDATA */
/* PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I10,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
};
@@ -1020,47 +1020,47 @@
/* GPP_A1 - LAD0 */
/* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A1,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A2 - LAD1 */
/* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A2,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A3 - LAD2 */
/* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A3,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A4 - LAD3 */
/* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A4,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A5 - LFRAME# */
/* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A5,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A6 - SERIRQ */
/* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A6,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A8 - CLKRUN# */
/* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A8,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A9 - CLKOUT_LPC0 */
/* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A9,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A10 - CLKOUT_LPC1 */
/* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A10,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
};
#endif /* _GPIO_X11SSH_TF_H */
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
index 34960bf..4659418 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
@@ -13,110 +13,92 @@
/* GPP_A0 - RCIN# */
/* PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A0,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A1 - LAD0 */
/* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A1,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A2 - LAD1 */
/* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A2,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A3 - LAD2 */
/* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A3,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A4 - LAD3 */
/* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A4,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A5 - LFRAME# */
/* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A5,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A6 - SERIRQ */
/* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A6,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A7 - PIRQA# */
/* PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A7,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A8 - CLKRUN# */
/* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A8,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A9 - CLKOUT_LPC0 */
/* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A9,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A10 - CLKOUT_LPC1 */
/* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A10,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A11 - PME# */
/* PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A11,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A12 - GPIO */
/* PAD_NC(GPP_A12, NONE), */
_PAD_CFG_STRUCT(GPP_A12,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_A13 - SUSWARN#/SUSPWRDNACK */
/* PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A13,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A14 - SUS_STAT# */
/* PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A14,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A15 - SUS_ACK# */
/* PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A15,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A16 - CLKOUT_48 */
/* PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A16,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A17 - GPIO */
/* PAD_NC(GPP_A17, NONE), */
_PAD_CFG_STRUCT(GPP_A17,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_A18 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, PLTRST, OFF, DRIVER), */
@@ -129,222 +111,191 @@
/* GPP_A20 - GPIO */
/* PAD_NC(GPP_A20, NONE), */
_PAD_CFG_STRUCT(GPP_A20,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_A21 - GPIO */
/* PAD_NC(GPP_A21, NONE), */
_PAD_CFG_STRUCT(GPP_A21,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_A22 - GPIO */
/* PAD_NC(GPP_A22, NONE), */
_PAD_CFG_STRUCT(GPP_A22,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_A23 - GPIO */
/* PAD_NC(GPP_A23, NONE), */
_PAD_CFG_STRUCT(GPP_A23,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPIO Group GPP_B */
/* GPP_B0 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_B0, 1, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_B0,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_B1 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_B1, 1, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_B1,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_B2 - GPIO */
/* PAD_NC(GPP_B2, NONE), */
_PAD_CFG_STRUCT(GPP_B2,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B3 - GPIO */
/* PAD_NC(GPP_B3, NONE), */
_PAD_CFG_STRUCT(GPP_B3,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B4 - GPIO */
/* PAD_NC(GPP_B4, NONE), */
_PAD_CFG_STRUCT(GPP_B4,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B5 - GPIO */
/* PAD_NC(GPP_B5, NONE), */
_PAD_CFG_STRUCT(GPP_B5,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B6 - GPIO */
/* PAD_NC(GPP_B6, NONE), */
_PAD_CFG_STRUCT(GPP_B6,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B7 - GPIO */
/* PAD_NC(GPP_B7, NONE), */
_PAD_CFG_STRUCT(GPP_B7,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B8 - GPIO */
/* PAD_NC(GPP_B8, NONE), */
_PAD_CFG_STRUCT(GPP_B8,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B9 - GPIO */
/* PAD_NC(GPP_B9, NONE), */
_PAD_CFG_STRUCT(GPP_B9,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B10 - GPIO */
/* PAD_NC(GPP_B10, NONE), */
_PAD_CFG_STRUCT(GPP_B10,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B11 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_B11,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE),
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_B12 - SLP_S0# */
/* PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_B12,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B13 - PLTRST# */
/* PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_B13,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B14 - SPKR */
/* PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), */
_PAD_CFG_STRUCT(GPP_B14,
- PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST), 0),
/* GPP_B15 - GPIO */
/* PAD_NC(GPP_B15, NONE), */
_PAD_CFG_STRUCT(GPP_B15,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B16 - GPIO */
/* PAD_NC(GPP_B16, NONE), */
_PAD_CFG_STRUCT(GPP_B16,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B17 - GPIO */
/* PAD_NC(GPP_B17, NONE), */
_PAD_CFG_STRUCT(GPP_B17,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B18 - GPIO */
/* PAD_NC(GPP_B18, NONE), */
_PAD_CFG_STRUCT(GPP_B18,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B19 - GPIO */
/* PAD_NC(GPP_B19, NONE), */
_PAD_CFG_STRUCT(GPP_B19,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B20 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_B20, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_B20,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_B21 - GPIO */
/* PAD_NC(GPP_B21, NONE), */
_PAD_CFG_STRUCT(GPP_B21,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B22 - GPIO */
/* PAD_NC(GPP_B22, NONE), */
_PAD_CFG_STRUCT(GPP_B22,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B23 - PCHHOT# */
/* PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), */
_PAD_CFG_STRUCT(GPP_B23,
- PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF2) | PAD_RESET(DEEP), 0),
/* GPIO Group GPP_C */
/* GPP_C0 - SMBCLK (RESERVED) */
/* PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), */
//_PAD_CFG_STRUCT(GPP_C0,
- // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- // PAD_CFG_OWN_GPIO(DRIVER)),
+ // PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C1 - SMBDATA (RESERVED) */
/* PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), */
//_PAD_CFG_STRUCT(GPP_C1,
- // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- // PAD_CFG_OWN_GPIO(DRIVER)),
+ // PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C2 - GPIO */
/* PAD_NC(GPP_C2, NONE), */
_PAD_CFG_STRUCT(GPP_C2,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C3 - SML0CLK (RESERVED) */
/* PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), */
//_PAD_CFG_STRUCT(GPP_C3,
- // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- // PAD_CFG_OWN_GPIO(DRIVER)),
+ // PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C4 - SML0DATA (RESERVED) */
/* PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), */
//_PAD_CFG_STRUCT(GPP_C4,
- // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- // PAD_CFG_OWN_GPIO(DRIVER)),
+ // PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C5 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_C5, 1, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_C5,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_C6 - SML1CLK (RESERVED) */
/* PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), */
//_PAD_CFG_STRUCT(GPP_C6,
- // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- // PAD_CFG_OWN_GPIO(DRIVER)),
+ // PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C7 - SML1DATA (RESERVED) */
/* PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), */
//_PAD_CFG_STRUCT(GPP_C7,
- // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- // PAD_CFG_OWN_GPIO(DRIVER)),
+ // PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C8 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, DRIVER), */
@@ -367,68 +318,57 @@
/* GPP_C11 - GPIO */
/* PAD_NC(GPP_C11, NONE), */
_PAD_CFG_STRUCT(GPP_C11,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C12 - GPIO */
/* PAD_NC(GPP_C12, NONE), */
_PAD_CFG_STRUCT(GPP_C12,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C13 - GPIO */
/* PAD_NC(GPP_C13, NONE), */
_PAD_CFG_STRUCT(GPP_C13,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C14 - GPIO */
/* PAD_NC(GPP_C14, NONE), */
_PAD_CFG_STRUCT(GPP_C14,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C15 - GPIO */
/* PAD_NC(GPP_C15, NONE), */
_PAD_CFG_STRUCT(GPP_C15,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C16 - GPIO */
/* PAD_NC(GPP_C16, NONE), */
_PAD_CFG_STRUCT(GPP_C16,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C17 - GPIO */
/* PAD_NC(GPP_C17, NONE), */
_PAD_CFG_STRUCT(GPP_C17,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C18 - GPIO */
/* PAD_NC(GPP_C18, NONE), */
_PAD_CFG_STRUCT(GPP_C18,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C19 - GPIO */
/* PAD_NC(GPP_C19, NONE), */
_PAD_CFG_STRUCT(GPP_C19,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C20 - GPIO */
/* PAD_NC(GPP_C20, NONE), */
_PAD_CFG_STRUCT(GPP_C20,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C21 - GPIO */
/* PAD_NC(GPP_C21, NONE), */
_PAD_CFG_STRUCT(GPP_C21,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C22 - GPIO */
/* PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), */
@@ -439,21 +379,19 @@
/* GPP_C23 - GPIO */
/* PAD_NC(GPP_C23, NONE), */
_PAD_CFG_STRUCT(GPP_C23,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPIO Group GPP_D */
/* GPP_D0 - GPIO */
/* PAD_NC(GPP_D0, NONE), */
_PAD_CFG_STRUCT(GPP_D0,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D1 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_D1,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_D2 - GPIO */
@@ -465,166 +403,144 @@
/* GPP_D3 - GPIO */
/* PAD_NC(GPP_D3, NONE), */
_PAD_CFG_STRUCT(GPP_D3,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D4 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_D4,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE),
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_D5 - GPIO */
/* PAD_NC(GPP_D5, NONE), */
_PAD_CFG_STRUCT(GPP_D5,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D6 - GPIO */
/* PAD_NC(GPP_D6, NONE), */
_PAD_CFG_STRUCT(GPP_D6,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D7 - GPIO */
/* PAD_NC(GPP_D7, NONE), */
_PAD_CFG_STRUCT(GPP_D7,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D8 - GPIO */
/* PAD_NC(GPP_D8, NONE), */
_PAD_CFG_STRUCT(GPP_D8,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D9 - GPIO */
/* PAD_NC(GPP_D9, NONE), */
_PAD_CFG_STRUCT(GPP_D9,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D10 - GPIO */
/* PAD_NC(GPP_D10, NONE), */
_PAD_CFG_STRUCT(GPP_D10,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D11 - GPIO */
/* PAD_NC(GPP_D11, NONE), */
_PAD_CFG_STRUCT(GPP_D11,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D12 - GPIO */
/* PAD_NC(GPP_D12, NONE), */
_PAD_CFG_STRUCT(GPP_D12,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D13 - GPIO */
/* PAD_NC(GPP_D13, NONE), */
_PAD_CFG_STRUCT(GPP_D13,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D14 - GPIO */
/* PAD_NC(GPP_D14, NONE), */
_PAD_CFG_STRUCT(GPP_D14,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D15 - GPIO */
/* PAD_NC(GPP_D15, NONE), */
_PAD_CFG_STRUCT(GPP_D15,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D16 - GPIO */
/* PAD_NC(GPP_D16, NONE), */
_PAD_CFG_STRUCT(GPP_D16,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D17 - GPIO */
/* PAD_NC(GPP_D17, NONE), */
_PAD_CFG_STRUCT(GPP_D17,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D18 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_D18,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_D19 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_D19,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_D20 - GPIO */
/* PAD_NC(GPP_D20, NONE), */
_PAD_CFG_STRUCT(GPP_D20,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D21 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_D21,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE),
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_D22 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PWROK, OFF, DRIVER), */
_PAD_CFG_STRUCT(GPP_D22,
- PAD_FUNC(GPIO) | (3 << 30) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_D23 - GPIO */
/* PAD_NC(GPP_D23, NONE), */
_PAD_CFG_STRUCT(GPP_D23,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPIO Group GPP_E */
/* GPP_E0 - GPIO */
/* PAD_NC(GPP_E0, NONE), */
_PAD_CFG_STRUCT(GPP_E0,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_E1 - GPIO */
/* PAD_NC(GPP_E1, NONE), */
_PAD_CFG_STRUCT(GPP_E1,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_E2 - GPIO */
/* PAD_NC(GPP_E2, NONE), */
_PAD_CFG_STRUCT(GPP_E2,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_E3 - GPIO */
/* PAD_NC(GPP_E3, NONE), */
_PAD_CFG_STRUCT(GPP_E3,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_E4 - GPIO */
/* PAD_NC(GPP_E4, NONE), */
_PAD_CFG_STRUCT(GPP_E4,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_E5 - GPIO */
/* PAD_NC(GPP_E5, NONE), */
_PAD_CFG_STRUCT(GPP_E5,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_E6 - GPIO */
/* PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), */
@@ -635,70 +551,59 @@
/* GPP_E7 - GPIO */
/* PAD_NC(GPP_E7, NONE), */
_PAD_CFG_STRUCT(GPP_E7,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_E8 - SATA_LED# */
/* PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E8,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E9 - USB_OC0# */
/* PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E9,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E10 - USB_OC1# */
/* PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E10,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E11 - USB_OC2# */
/* PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E11,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E12 - USB_OC3# */
/* PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E12,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPIO Group GPP_F */
/* GPP_F0 - GPIO */
/* PAD_NC(GPP_F0, NONE), */
_PAD_CFG_STRUCT(GPP_F0,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_F1 - GPIO */
/* PAD_NC(GPP_F1, NONE), */
_PAD_CFG_STRUCT(GPP_F1,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_F2 - GPIO */
/* PAD_NC(GPP_F2, NONE), */
_PAD_CFG_STRUCT(GPP_F2,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_F3 - GPIO */
/* PAD_NC(GPP_F3, NONE), */
_PAD_CFG_STRUCT(GPP_F3,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_F4 - GPIO */
/* PAD_NC(GPP_F4, NONE), */
_PAD_CFG_STRUCT(GPP_F4,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_F5 - GPIO */
/* PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), */
@@ -709,19 +614,19 @@
/* GPP_F6 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_F6,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_F7 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_F7,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_F8 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_F8,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_F9 - GPIO */
@@ -733,85 +638,72 @@
/* GPP_F10 - SATA_SCLOCK */
/* PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F10,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F11 - SATA_SLOAD */
/* PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F11,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F12 - SATA_SDATAOUT1 */
/* PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F12,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F13 - SATA_SDATAOUT2 */
/* PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F13,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F14 - GPIO */
/* PAD_NC(GPP_F14, NONE), */
_PAD_CFG_STRUCT(GPP_F14,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_F15 - USB_OC4# */
/* PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F15,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F16 - USB_OC5# */
/* PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F16,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F17 - GPIO */
/* PAD_NC(GPP_F17, NONE), */
_PAD_CFG_STRUCT(GPP_F17,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_F18 - GPIO */
/* PAD_NC(GPP_F18, NONE), */
_PAD_CFG_STRUCT(GPP_F18,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_F19 - GPIO */
/* PAD_NC(GPP_F19, NONE), */
_PAD_CFG_STRUCT(GPP_F19,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_F20 - GPIO */
/* PAD_NC(GPP_F20, NONE), */
_PAD_CFG_STRUCT(GPP_F20,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_F21 - GPIO */
/* PAD_NC(GPP_F21, NONE), */
_PAD_CFG_STRUCT(GPP_F21,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_F22 - GPIO */
/* PAD_NC(GPP_F22, NONE), */
_PAD_CFG_STRUCT(GPP_F22,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_F23 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, PWROK, NONE), */
_PAD_CFG_STRUCT(GPP_F23,
- PAD_FUNC(GPIO) | (3 << 30) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE),
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_G */
@@ -843,50 +735,42 @@
/* GPP_G4 - GPIO */
/* PAD_NC(GPP_G4, NONE), */
_PAD_CFG_STRUCT(GPP_G4,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_G5 - GPIO */
/* PAD_NC(GPP_G5, NONE), */
_PAD_CFG_STRUCT(GPP_G5,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_G6 - GPIO */
/* PAD_NC(GPP_G6, NONE), */
_PAD_CFG_STRUCT(GPP_G6,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_G7 - GPIO */
/* PAD_NC(GPP_G7, NONE), */
_PAD_CFG_STRUCT(GPP_G7,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_G8 - GPIO */
/* PAD_NC(GPP_G8, NONE), */
_PAD_CFG_STRUCT(GPP_G8,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_G9 - GPIO */
/* PAD_NC(GPP_G9, NONE), */
_PAD_CFG_STRUCT(GPP_G9,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_G10 - GPIO */
/* PAD_NC(GPP_G10, NONE), */
_PAD_CFG_STRUCT(GPP_G10,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_G11 - GPIO */
/* PAD_NC(GPP_G11, NONE), */
_PAD_CFG_STRUCT(GPP_G11,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_G12 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, DRIVER), */
@@ -921,20 +805,17 @@
/* GPP_G17 - GPIO */
/* PAD_NC(GPP_G17, NONE), */
_PAD_CFG_STRUCT(GPP_G17,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_G18 - NMI# */
/* PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_G18,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_G19 - SMI# */
/* PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_G19,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_G20 - GPIO */
/* PAD_NC(GPP_G20, NONE), */
@@ -954,153 +835,143 @@
/* GPP_G23 - GPIO */
/* PAD_NC(GPP_G23, NONE), */
_PAD_CFG_STRUCT(GPP_G23,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPIO Group GPP_H */
/* GPP_H0 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_H0,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H1 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, DRIVER), */
_PAD_CFG_STRUCT(GPP_H1,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H2 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_H2,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H3 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H3, 1, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_H3,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H4 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, DRIVER), */
_PAD_CFG_STRUCT(GPP_H4,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H5 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H5, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H5,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H6 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H6, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H6,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H7 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H7, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H7,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H8 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H8, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H8,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H9 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H9, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H9,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H10 - SML2CLK */
/* PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H10,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H11 - SML2DATA */
/* PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H11,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H12 - GPIO */
/* PAD_NC(GPP_H12, NONE), */
_PAD_CFG_STRUCT(GPP_H12,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_H13 - SML3CLK */
/* PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H13,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H14 - SML3DATA */
/* PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H14,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H15 - GPIO */
/* PAD_NC(GPP_H15, NONE), */
_PAD_CFG_STRUCT(GPP_H15,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_H16 - SML4CLK */
/* PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H16,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H17 - SML4DATA */
/* PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H17,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H18 - GPIO */
/* PAD_NC(GPP_H18, NONE), */
_PAD_CFG_STRUCT(GPP_H18,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_H19 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H19, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H19,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H20 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H20, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H20,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H21 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H21, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H21,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H22 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H22, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H22,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPP_H23 - GPIO */
/* PAD_CFG_GPO_GPIO_DRIVER(GPP_H23, 1, PLTRST, NONE), */
_PAD_CFG_STRUCT(GPP_H23,
- PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1,
PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_I */
@@ -1108,142 +979,119 @@
/* GPP_I0 - DDPB_HPD0 */
/* PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I0,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I1 - DDPC_HPD1 */
/* PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I1,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I2 - DDPD_HPD2 */
/* PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I2,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I3 - DDPE_HPD3 */
/* PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), */
_PAD_CFG_STRUCT(GPP_I3,
- PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST), 0),
/* GPP_I4 - GPIO */
/* PAD_NC(GPP_I4, NONE), */
_PAD_CFG_STRUCT(GPP_I4,
- PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_I5 - DDPB_CTRLCLK */
/* PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I5,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I6 - DDPB_CTRLDATA */
/* PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I6,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I7 - DDPC_CTRLCLK */
/* PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I7,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I8 - DDPC_CTRLDATA */
/* PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I8,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I9 - DDPD_CTRLCLK */
/* PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I9,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I10 - DDPD_CTRLDATA */
/* PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I10,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPIO Group GPD */
/* GPD0 - GPIO */
/* PAD_NC(GPD0, NONE), */
_PAD_CFG_STRUCT(GPD0,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD1 - GPIO */
/* PAD_NC(GPD1, NONE), */
_PAD_CFG_STRUCT(GPD1,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD2 - LAN_WAKE# */
/* PAD_CFG_NF(GPD2, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD2,
- PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1), 0),
/* GPD3 - PWRBTN# */
/* PAD_CFG_NF(GPD3, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD3,
- PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1), 0),
/* GPD4 - SLP_S3# */
/* PAD_CFG_NF(GPD4, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD4,
- PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1), 0),
/* GPD5 - SLP_S4# */
/* PAD_CFG_NF(GPD5, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD5,
- PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1), 0),
/* GPD6 - SLP_A# */
/* PAD_CFG_NF(GPD6, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD6,
- PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1), 0),
/* GPD7 - GPIO */
/* PAD_NC(GPD7, NONE), */
_PAD_CFG_STRUCT(GPD7,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD8 - SUSCLK */
/* PAD_CFG_NF(GPD8, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD8,
- PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1), 0),
/* GPD9 - GPIO */
/* PAD_NC(GPD9, NONE), */
_PAD_CFG_STRUCT(GPD9,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD10 - GPIO */
/* PAD_NC(GPD10, NONE), */
_PAD_CFG_STRUCT(GPD10,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD11 - GPIO */
/* PAD_NC(GPD11, NONE), */
_PAD_CFG_STRUCT(GPD11,
- PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
};
/* Early pad configuration in romstage. */
@@ -1254,58 +1102,49 @@
/* GPP_A1 - LAD0 */
/* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A1,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A2 - LAD1 */
/* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A2,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A3 - LAD2 */
/* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A3,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A4 - LAD3 */
/* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A4,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A5 - LFRAME# */
/* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A5,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A8 - CLKRUN# */
/* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A8,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A9 - CLKOUT_LPC0 */
/* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A9,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A10 - CLKOUT_LPC1 */
/* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A10,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* Serial interrupt */
/* GPP_A6 - SERIRQ */
/* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A6,
- PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
- PAD_CFG_OWN_GPIO(DRIVER)),
+ PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
};
#endif /* _GPIO_X11SSM_F_H */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icdf366a8d416598cec5afcb9a0fae6bf7ecd7ba0
Gerrit-Change-Number: 42917
Gerrit-PatchSet: 1
Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-MessageType: newchange
3
18
Change in coreboot[master]: [TEST] mb/supermicro/x11-lga1151-series: rewrite gpio.h using intelp2m
by Maxim Polyakov (Code Review) 24 Jul '20
by Maxim Polyakov (Code Review) 24 Jul '20
24 Jul '20
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35679 )
Change subject: [TEST] mb/supermicro/x11-lga1151-series: rewrite gpio.h using intelp2m
......................................................................
[TEST] mb/supermicro/x11-lga1151-series: rewrite gpio.h using intelp2m
gpio.h was generated using the Intel Pad 2 Macro utility (intelp2m) [1]
Please review and test coreboot image with this patch
[1] https://review.coreboot.org/c/coreboot/+/35643
These changes are not tested on real hardware.
Change-Id: Idad7536854d4b1ae7dcf7934e81de438478fe059
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
1 file changed, 213 insertions(+), 213 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/35679/1
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
index a5eed6b..5320298 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
@@ -21,210 +21,210 @@
#ifndef __ACPI__
static const struct pad_config gpio_table[] = {
-/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000),
-/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000),
-/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000),
-/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000),
-/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000),
-/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000),
-/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000),
-/* PIRQA# */ _PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x00000000),
-/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000),
-/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000),
-/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000),
-/* PME# */ _PAD_CFG_STRUCT(GPP_A11, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x80080201, 0x00000000),
-/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000000),
-/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000000),
-/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x00000000),
-/* CLKOUT_48 */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000000),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000000),
-/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000000),
-/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000000),
-/* SPKR */ _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000000),
-/* PCHHOT# */ _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000000),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000000),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000000),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x84000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x84000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x42040102, 0x00003000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x42020102, 0x00003000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000),
-/* SATAXPCIE0 */ _PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x82020102, 0x00003000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000000),
-/* SATA_LED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000000),
-/* USB_OC0# */ _PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x00000000),
-/* USB_OC1# */ _PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x00000000),
-/* USB_OC2# */ _PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x00000000),
-/* USB_OC3# */ _PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F5, 0x80100102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000000),
-/* SATA_SCLOCK */ _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000000),
-/* SATA_SLOAD */ _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000000),
-/* SATA_SDATAOUT1 */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000000),
-/* SATA_SDATAOUT2 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000000),
-/* USB_OC4# */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x00000000),
-/* USB_OC5# */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G14, 0x84000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000000),
-/* NMI# */ _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000000),
-/* SMI# */ _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H1, 0x84000103, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000000),
-/* SRCCLKREQ9# */ _PAD_CFG_STRUCT(GPP_H3, 0x44000602, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H4, 0x84000103, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000000),
-/* SML2CLK */ _PAD_CFG_STRUCT(GPP_H10, 0x44000702, 0x00000000),
-/* SML2DATA */ _PAD_CFG_STRUCT(GPP_H11, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000000),
-/* SML3CLK */ _PAD_CFG_STRUCT(GPP_H13, 0x44000702, 0x00000000),
-/* SML3DATA */ _PAD_CFG_STRUCT(GPP_H14, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000000),
-/* SML4CLK */ _PAD_CFG_STRUCT(GPP_H16, 0x44000702, 0x00000000),
-/* SML4DATA */ _PAD_CFG_STRUCT(GPP_H17, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000000),
-/* LAN_WAKE# */ _PAD_CFG_STRUCT(GPD2, 0x04000702, 0x00000000),
-/* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x04000702, 0x00000000),
-/* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000000),
-/* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000000),
-/* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000000),
-/* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000000),
-/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000000),
-/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000000),
-/* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000000),
-/* DDPE_HPD3 */ _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000000),
-/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000000),
-/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000000),
-/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000000),
-/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000000),
-/* DDPD_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000000),
-/* DDPD_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000000),
+ PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* RCIN# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD0 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A2, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD1 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A3, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD2 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A4, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD3 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LFRAME# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SERIRQ */
+ PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* PIRQA# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKRUN# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A9, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKOUT_LPC0 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKOUT_LPC1 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A11, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* PME# */
+ PAD_CFG_GPO(GPP_A12, 1, PLTRST), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SUSWARN# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SUS_STAT# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A15, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SUS_ACK# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A16, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKOUT_48 */
+ PAD_NC(GPP_A17, NONE), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00) /* RESERVED */
+ PAD_NC(GPP_A20, NONE), /* GPIO */
+ PAD_NC(GPP_A21, NONE), /* GPIO */
+ PAD_NC(GPP_A22, NONE), /* GPIO */
+ PAD_NC(GPP_A23, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_B0, 1, DEEP), /* GPIO */
+ PAD_CFG_GPO(GPP_B1, 1, DEEP), /* GPIO */
+ PAD_NC(GPP_B2, NONE), /* GPIO */
+ PAD_NC(GPP_B3, NONE), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SLP_S0# */
+ PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* PLTRST# */
+ PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, PLTRST, NF1, TX_RX_DISABLE, OFF), /* SPKR */
+ PAD_NC(GPP_B15, NONE), /* GPIO */
+ PAD_NC(GPP_B16, NONE), /* GPIO */
+ PAD_NC(GPP_B17, NONE), /* GPIO */
+ PAD_NC(GPP_B18, NONE), /* GPIO */
+ PAD_NC(GPP_B19, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_B20, 1, PLTRST), /* GPIO */
+ PAD_NC(GPP_B21, NONE), /* GPIO */
+ PAD_NC(GPP_B22, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, DEEP, NF2, TX_RX_DISABLE, LEVEL), /* PCHHOT# */
+ _PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00) /* RESERVED */
+ _PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00) /* RESERVED */
+ PAD_NC(GPP_C2, NONE), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00) /* RESERVED */
+ _PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00) /* RESERVED */
+ PAD_CFG_GPO(GPP_C5, 1, DEEP), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00) /* RESERVED */
+ _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00) /* RESERVED */
+ PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF), /* GPIO */
+ PAD_NC(GPP_C11, NONE), /* GPIO */
+ PAD_NC(GPP_C12, NONE), /* GPIO */
+ PAD_NC(GPP_C13, NONE), /* GPIO */
+ PAD_NC(GPP_C14, NONE), /* GPIO */
+ PAD_NC(GPP_C15, NONE), /* GPIO */
+ PAD_NC(GPP_C16, NONE), /* GPIO */
+ PAD_NC(GPP_C17, NONE), /* GPIO */
+ PAD_NC(GPP_C18, NONE), /* GPIO */
+ PAD_NC(GPP_C19, NONE), /* GPIO */
+ PAD_NC(GPP_C20, NONE), /* GPIO */
+ PAD_NC(GPP_C21, NONE), /* GPIO */
+ PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), /* GPIO */
+ PAD_NC(GPP_C23, NONE), /* GPIO */
+ PAD_NC(GPP_D0, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_D1, 1, DEEP), /* GPIO */
+ PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), /* GPIO */
+ PAD_NC(GPP_D3, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* GPIO */
+ PAD_NC(GPP_D5, NONE), /* GPIO */
+ PAD_NC(GPP_D6, NONE), /* GPIO */
+ PAD_NC(GPP_D7, NONE), /* GPIO */
+ PAD_NC(GPP_D8, NONE), /* GPIO */
+ PAD_NC(GPP_D9, NONE), /* GPIO */
+ PAD_NC(GPP_D10, NONE), /* GPIO */
+ PAD_NC(GPP_D11, NONE), /* GPIO */
+ PAD_NC(GPP_D12, NONE), /* GPIO */
+ PAD_NC(GPP_D13, NONE), /* GPIO */
+ PAD_NC(GPP_D14, NONE), /* GPIO */
+ PAD_NC(GPP_D15, NONE), /* GPIO */
+ PAD_NC(GPP_D16, NONE), /* GPIO */
+ PAD_NC(GPP_D17, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_D18, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_D19, 1, PLTRST), /* GPIO */
+ PAD_NC(GPP_D20, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_D22, NONE, PWROK, OFF), /* GPIO */
+ PAD_NC(GPP_D23, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_E0, NONE, DEEP, NF1, TX_DISABLE, OFF), /* SATAXPCIE0 */
+ PAD_NC(GPP_E1, NONE), /* GPIO */
+ PAD_NC(GPP_E2, NONE), /* GPIO */
+ PAD_NC(GPP_E3, NONE), /* GPIO */
+ PAD_NC(GPP_E4, NONE), /* GPIO */
+ PAD_NC(GPP_E5, NONE), /* GPIO */
+ PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), /* GPIO */
+ PAD_NC(GPP_E7, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SATA_LED# */
+ PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC0# */
+ PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC1# */
+ PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC2# */
+ PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC3# */
+ PAD_NC(GPP_F0, NONE), /* GPIO */
+ PAD_NC(GPP_F1, NONE), /* GPIO */
+ PAD_NC(GPP_F2, NONE), /* GPIO */
+ PAD_NC(GPP_F3, NONE), /* GPIO */
+ PAD_NC(GPP_F4, NONE), /* GPIO */
+ PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_F6, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_F8, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SATA_SCLOCK */
+ PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SATA_SLOAD */
+ PAD_CFG_NF_BUF_TRIG(GPP_F12, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SATA_SDATAOUT1 */
+ PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SATA_SDATAOUT2 */
+ PAD_NC(GPP_F14, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC4# */
+ PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC5# */
+ PAD_NC(GPP_F17, NONE), /* GPIO */
+ PAD_NC(GPP_F18, NONE), /* GPIO */
+ PAD_NC(GPP_F19, NONE), /* GPIO */
+ PAD_NC(GPP_F20, NONE), /* GPIO */
+ PAD_NC(GPP_F21, NONE), /* GPIO */
+ PAD_NC(GPP_F22, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_F23, 0, PWROK), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G0, NONE, DEEP, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G1, NONE, DEEP, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G2, NONE, DEEP, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G3, NONE, DEEP, OFF), /* GPIO */
+ PAD_NC(GPP_G4, NONE), /* GPIO */
+ PAD_NC(GPP_G5, NONE), /* GPIO */
+ PAD_NC(GPP_G6, NONE), /* GPIO */
+ PAD_NC(GPP_G7, NONE), /* GPIO */
+ PAD_NC(GPP_G8, NONE), /* GPIO */
+ PAD_NC(GPP_G9, NONE), /* GPIO */
+ PAD_NC(GPP_G10, NONE), /* GPIO */
+ PAD_NC(GPP_G11, NONE), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G12, NONE, PLTRST, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G13, NONE, PLTRST, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G14, NONE, PLTRST, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G15, NONE, PLTRST, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G16, NONE, PLTRST, OFF), /* GPIO */
+ PAD_NC(GPP_G17, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* NMI# */
+ PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SMI# */
+ PAD_NC(GPP_G20, NONE), /* GPIO */
+ PAD_NC(GPP_G21, NONE), /* GPIO */
+ PAD_NC(GPP_G22, NONE), /* GPIO */
+ PAD_NC(GPP_G23, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_H0, 1, DEEP), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ PAD_CFG_GPO(GPP_H2, 1, DEEP), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_H3, NONE, DEEP, NF1, RX_DISABLE, OFF), /* SRCCLKREQ9# */
+ _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ PAD_CFG_GPO(GPP_H5, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H6, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H7, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H8, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H9, 1, PLTRST), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_H10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML2CLK */
+ PAD_CFG_NF_BUF_TRIG(GPP_H11, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML2DATA */
+ PAD_NC(GPP_H12, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_H13, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML3CLK */
+ PAD_CFG_NF_BUF_TRIG(GPP_H14, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML3DATA */
+ PAD_NC(GPP_H15, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_H16, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML4CLK */
+ PAD_CFG_NF_BUF_TRIG(GPP_H17, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML4DATA */
+ PAD_NC(GPP_H18, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_H19, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H20, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H21, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H22, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H23, 1, PLTRST), /* GPIO */
+ PAD_NC(GPD0, NONE), /* GPIO */
+ PAD_NC(GPD1, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPD2, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* LAN_WAKE# */
+ PAD_CFG_NF_BUF_TRIG(GPD3, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* PWRBTN# */
+ PAD_CFG_NF_BUF_TRIG(GPD4, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* SLP_S3# */
+ PAD_CFG_NF_BUF_TRIG(GPD5, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* SLP_S4# */
+ PAD_CFG_NF_BUF_TRIG(GPD6, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* SLP_A# */
+ _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPD8, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* SUSCLK */
+ PAD_NC(GPD9, NONE), /* GPIO */
+ PAD_NC(GPD10, NONE), /* GPIO */
+ PAD_NC(GPD11, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPB_HPD0 */
+ PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPC_HPD1 */
+ PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPD_HPD2 */
+ PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, PLTRST, NF1, TX_RX_DISABLE, OFF), /* DDPE_HPD3 */
+ PAD_NC(GPP_I4, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_I5, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPB_CTRLCLK */
+ PAD_CFG_NF_BUF_TRIG(GPP_I6, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPB_CTRLDATA */
+ PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPC_CTRLCLK */
+ PAD_CFG_NF_BUF_TRIG(GPP_I8, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPC_CTRLDATA */
+ PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPD_CTRLCLK */
+ PAD_CFG_NF_BUF_TRIG(GPP_I10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPD_CTRLDATA */
};
@@ -233,15 +233,15 @@
static const struct pad_config early_gpio_table[] = {
/* LPC */
-/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000),
-/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000),
-/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000),
-/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000),
-/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000),
-/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000),
-/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000),
-/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000),
-/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000),
+ PAD_CFG_NF_BUF_TRIG(GPP_A1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD0 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A2, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD1 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A3, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD2 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A4, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD3 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LFRAME# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SERIRQ */
+ PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKRUN# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A9, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKOUT_LPC0 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKOUT_LPC1 */
};
#endif /* __ACPI__ */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idad7536854d4b1ae7dcf7934e81de438478fe059
Gerrit-Change-Number: 35679
Gerrit-PatchSet: 1
Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-MessageType: newchange
3
24
Change in coreboot[master]: assert.h: Do not use __FILE__ nor __LINE__ on timeless builds
by Angel Pons (Code Review) 24 Jul '20
by Angel Pons (Code Review) 24 Jul '20
24 Jul '20
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42196 )
Change subject: assert.h: Do not use __FILE__ nor __LINE__ on timeless builds
......................................................................
assert.h: Do not use __FILE__ nor __LINE__ on timeless builds
When refactoring, one can move code around quite a bit while preserving
reproducibility, unless there is an assert-style macro somewhere... As
these macros use __FILE__ and __LINE__, just moving them is enough to
change the resulting binary, making timeless builds rather useless.
To improve reproducibility, do not use __FILE__ nor __LINE__ inside the
assert-style macros. Instead, use hardcoded values. Plus, mention that
timeless builds lack such information in place of the file name, so that
grepping for the printed string directs one towards this commit. And for
the immutable line number, we can use 404: line number not found :-)
Change-Id: Id42d7121b6864759c042f8e4e438ee77a8ac0b41
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/include/assert.h
1 file changed, 33 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/42196/1
diff --git a/src/include/assert.h b/src/include/assert.h
index f656d81..da8906d 100644
--- a/src/include/assert.h
+++ b/src/include/assert.h
@@ -4,6 +4,7 @@
#define __ASSERT_H__
#include <arch/hlt.h>
+#include <build.h>
#include <console/console.h>
/* TODO: Fix vendorcode headers to not define macros coreboot uses or to be more
@@ -12,31 +13,43 @@
#undef ASSERT
#endif
+/* Do not use filenames nor line numbers on timeless builds, to preserve reproducibility */
+#if COREBOOT_VERSION_TIMESTAMP == 0
+#define __ASSERT_FILE__ "(filenames not available on timeless builds)"
+#define __ASSERT_LINE__ 404
+#else
+#define __ASSERT_FILE__ __FILE__
+#define __ASSERT_LINE__ __LINE__
+#endif
+
/* GCC and CAR versions */
-#define ASSERT(x) { \
- if (!(x)) { \
- printk(BIOS_EMERG, "ASSERTION ERROR: file '%s'" \
- ", line %d\n", __FILE__, __LINE__); \
- if (CONFIG(FATAL_ASSERTS)) \
- hlt(); \
- } \
+#define ASSERT(x) { \
+ if (!(x)) { \
+ printk(BIOS_EMERG, \
+ "ASSERTION ERROR: file '%s', line %d\n", \
+ __ASSERT_FILE__, __ASSERT_LINE__); \
+ if (CONFIG(FATAL_ASSERTS)) \
+ hlt(); \
+ } \
}
-#define ASSERT_MSG(x, msg) { \
- if (!(x)) { \
- printk(BIOS_EMERG, "ASSERTION ERROR: file '%s'" \
- ", line %d\n", __FILE__, __LINE__); \
- printk(BIOS_EMERG, "%s", msg); \
- if (CONFIG(FATAL_ASSERTS)) \
- hlt(); \
- } \
+#define ASSERT_MSG(x, msg) { \
+ if (!(x)) { \
+ printk(BIOS_EMERG, \
+ "ASSERTION ERROR: file '%s', line %d\n", \
+ __ASSERT_FILE__, __ASSERT_LINE__); \
+ printk(BIOS_EMERG, "%s", msg); \
+ if (CONFIG(FATAL_ASSERTS)) \
+ hlt(); \
+ } \
}
-#define BUG() { \
- printk(BIOS_EMERG, "ERROR: BUG ENCOUNTERED at file '%s'"\
- ", line %d\n", __FILE__, __LINE__); \
- if (CONFIG(FATAL_ASSERTS)) \
- hlt(); \
+#define BUG() { \
+ printk(BIOS_EMERG, \
+ "ERROR: BUG ENCOUNTERED at file '%s', line %d\n", \
+ __ASSERT_FILE__, __ASSERT_LINE__); \
+ if (CONFIG(FATAL_ASSERTS)) \
+ hlt(); \
}
#define assert(statement) ASSERT(statement)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id42d7121b6864759c042f8e4e438ee77a8ac0b41
Gerrit-Change-Number: 42196
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: newchange
5
14
Change in coreboot[master]: mb/supermicro/x11-lga1151: 1/5 Rewrite pad config using intelp2m
by Maxim Polyakov (Code Review) 24 Jul '20
by Maxim Polyakov (Code Review) 24 Jul '20
24 Jul '20
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: mb/supermicro/x11-lga1151: 1/5 Rewrite pad config using intelp2m
......................................................................
mb/supermicro/x11-lga1151: 1/5 Rewrite pad config using intelp2m
Use the intelp2m utility [1,2] with -adv options to convert the pad
configuration format with the raw values of the DW0 and DW1 registers
to the format with the bit fiends macros: PAD_FUNC(), PAD_RESET(),
PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to
generate the target macro in the comments, so that it is easier to
understand what result we should get:
./intelp2m -ii -adv -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
./intelp2m -ii -adv -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
[1] https://github.com/maxpoliak/pch-pads-parser
[2] https://review.coreboot.org/c/coreboot/+/35643
Tested with BUILD_TIMELESS=1
Change-Id: I209ecdca75a0e62233d3726942c75ea06acc40a2
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
2 files changed, 2,319 insertions(+), 431 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42916/1
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
index bc2d5ce..92c877f 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
@@ -6,228 +6,1061 @@
#include <soc/gpe.h>
#include <soc/gpio.h>
+/* Pad configuration was generated automatically using intelp2m utility */
static const struct pad_config gpio_table[] = {
-/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000),
-/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000),
-/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000),
-/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000),
-/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000),
-/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000),
-/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000),
-/* PIRQA# */ _PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x00000000),
-/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000),
-/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000),
-/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000),
-/* PME# */ _PAD_CFG_STRUCT(GPP_A11, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x80080201, 0x00000000),
-/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000000),
-/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000000),
-/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x00000000),
-/* CLKOUT_48 */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000000),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000000),
-/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000000),
-/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000000),
-/* SPKR */ _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000000),
-/* PCHHOT# */ _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000000),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000000),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000000),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x84000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x84000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x42040102, 0x00003000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x42020102, 0x00003000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0xc4000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000),
-/* SATAXPCIE0 */ _PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x82020102, 0x00003000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000000),
-/* SATA_LED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000000),
-/* USB_OC0# */ _PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x00000000),
-/* USB_OC1# */ _PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x00000000),
-/* USB_OC2# */ _PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x00000000),
-/* USB_OC3# */ _PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F5, 0x80100102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000000),
-/* SATA_SCLOCK */ _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000000),
-/* SATA_SLOAD */ _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000000),
-/* SATA_SDATAOUT1 */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000000),
-/* SATA_SDATAOUT2 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000000),
-/* USB_OC4# */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x00000000),
-/* USB_OC5# */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0xc4000200, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G14, 0x84000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000000),
-/* NMI# */ _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000000),
-/* SMI# */ _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H1, 0x84000103, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000000),
-/* SRCCLKREQ9# */ _PAD_CFG_STRUCT(GPP_H3, 0x44000602, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H4, 0x84000103, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000000),
-/* SML2CLK */ _PAD_CFG_STRUCT(GPP_H10, 0x44000702, 0x00000000),
-/* SML2DATA */ _PAD_CFG_STRUCT(GPP_H11, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000000),
-/* SML3CLK */ _PAD_CFG_STRUCT(GPP_H13, 0x44000702, 0x00000000),
-/* SML3DATA */ _PAD_CFG_STRUCT(GPP_H14, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000000),
-/* SML4CLK */ _PAD_CFG_STRUCT(GPP_H16, 0x44000702, 0x00000000),
-/* SML4DATA */ _PAD_CFG_STRUCT(GPP_H17, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000000),
-/* LAN_WAKE# */ _PAD_CFG_STRUCT(GPD2, 0x04000702, 0x00000000),
-/* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x04000702, 0x00000000),
-/* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000000),
-/* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000000),
-/* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000000),
-/* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000000),
-/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000000),
-/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000000),
-/* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000000),
-/* DDPE_HPD3 */ _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000000),
-/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000000),
-/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000000),
-/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000000),
-/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000000),
-/* DDPD_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000000),
-/* DDPD_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000000),
+ /* GPP_A0 - RCIN# */
+ /* PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A0,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_A1 - LAD0 */
+ /* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A1,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_A2 - LAD1 */
+ /* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A2,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A3 - LAD2 */
+ /* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A3,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_A4 - LAD3 */
+ /* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A4,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A5 - LFRAME# */
+ /* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A5,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A6 - SERIRQ */
+ /* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A6,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A7 - PIRQA# */
+ /* PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A7,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_A8 - CLKRUN# */
+ /* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A8,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A9 - CLKOUT_LPC0 */
+ /* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A9,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A10 - CLKOUT_LPC1 */
+ /* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A10,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A11 - PME# */
+ /* PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A11,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_A12 - GPIO */
+ /* PAD_CFG_GPO(GPP_A12, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_A12,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_A13 - SUSWARN# */
+ /* PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A13,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A14 - SUS_STAT# */
+ /* PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A14,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A15 - SUS_ACK# */
+ /* PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A15,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_A16 - CLKOUT_48 */
+ /* PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A16,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A17 - GPIO */
+ /* PAD_NC(GPP_A17, NONE), */
+ _PAD_CFG_STRUCT(GPP_A17,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A18 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, PLTRST, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_A18,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+
+ /* GPP_A19 - RESERVED */
+
+ /* GPP_A20 - GPIO */
+ /* PAD_NC(GPP_A20, NONE), */
+ _PAD_CFG_STRUCT(GPP_A20,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A21 - GPIO */
+ /* PAD_NC(GPP_A21, NONE), */
+ _PAD_CFG_STRUCT(GPP_A21,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A22 - GPIO */
+ /* PAD_NC(GPP_A22, NONE), */
+ _PAD_CFG_STRUCT(GPP_A22,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A23 - GPIO */
+ /* PAD_NC(GPP_A23, NONE), */
+ _PAD_CFG_STRUCT(GPP_A23,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_B0 - GPIO */
+ /* PAD_CFG_GPO(GPP_B0, 1, DEEP), */
+ _PAD_CFG_STRUCT(GPP_B0,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_B1 - GPIO */
+ /* PAD_CFG_GPO(GPP_B1, 1, DEEP), */
+ _PAD_CFG_STRUCT(GPP_B1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_B2 - GPIO */
+ /* PAD_NC(GPP_B2, NONE), */
+ _PAD_CFG_STRUCT(GPP_B2,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_B3 - GPIO */
+ /* PAD_NC(GPP_B3, NONE), */
+ _PAD_CFG_STRUCT(GPP_B3,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_B4 - GPIO */
+ /* PAD_NC(GPP_B4, NONE), */
+ _PAD_CFG_STRUCT(GPP_B4,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+
+ /* GPP_B5 - GPIO */
+ /* PAD_NC(GPP_B5, NONE), */
+ _PAD_CFG_STRUCT(GPP_B5,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+
+ /* GPP_B6 - GPIO */
+ /* PAD_NC(GPP_B6, NONE), */
+ _PAD_CFG_STRUCT(GPP_B6,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+
+ /* GPP_B7 - GPIO */
+ /* PAD_NC(GPP_B7, NONE), */
+ _PAD_CFG_STRUCT(GPP_B7,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+
+ /* GPP_B8 - GPIO */
+ /* PAD_NC(GPP_B8, NONE), */
+ _PAD_CFG_STRUCT(GPP_B8,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+
+ /* GPP_B9 - GPIO */
+ /* PAD_NC(GPP_B9, NONE), */
+ _PAD_CFG_STRUCT(GPP_B9,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+
+ /* GPP_B10 - GPIO */
+ /* PAD_NC(GPP_B10, NONE), */
+ _PAD_CFG_STRUCT(GPP_B10,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+
+ /* GPP_B11 - GPIO */
+ /* PAD_CFG_GPO(GPP_B11, 0, DEEP), */
+ _PAD_CFG_STRUCT(GPP_B11,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+
+ /* GPP_B12 - SLP_S0# */
+ /* PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_B12,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_B13 - PLTRST# */
+ /* PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_B13,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_B14 - SPKR */
+ /* PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), */
+ _PAD_CFG_STRUCT(GPP_B14,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_B15 - GPIO */
+ /* PAD_NC(GPP_B15, NONE), */
+ _PAD_CFG_STRUCT(GPP_B15,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_B16 - GPIO */
+ /* PAD_NC(GPP_B16, NONE), */
+ _PAD_CFG_STRUCT(GPP_B16,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_B17 - GPIO */
+ /* PAD_NC(GPP_B17, NONE), */
+ _PAD_CFG_STRUCT(GPP_B17,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_B18 - GPIO */
+ /* PAD_NC(GPP_B18, NONE), */
+ _PAD_CFG_STRUCT(GPP_B18,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_B19 - GPIO */
+ /* PAD_NC(GPP_B19, NONE), */
+ _PAD_CFG_STRUCT(GPP_B19,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_B20 - GPIO */
+ /* PAD_CFG_GPO(GPP_B20, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_B20,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_B21 - GPIO */
+ /* PAD_NC(GPP_B21, NONE), */
+ _PAD_CFG_STRUCT(GPP_B21,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_B22 - GPIO */
+ /* PAD_NC(GPP_B22, NONE), */
+ _PAD_CFG_STRUCT(GPP_B22,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_B23 - PCHHOT# */
+ /* PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), */
+ _PAD_CFG_STRUCT(GPP_B23,
+ PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_C0 - RESERVED */
+
+ /* GPP_C1 - RESERVED */
+
+ /* GPP_C2 - GPIO */
+ /* PAD_NC(GPP_C2, NONE), */
+ _PAD_CFG_STRUCT(GPP_C2,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_C3 - RESERVED */
+
+ /* GPP_C4 - RESERVED */
+
+ /* GPP_C5 - GPIO */
+ /* PAD_CFG_GPO(GPP_C5, 1, DEEP), */
+ _PAD_CFG_STRUCT(GPP_C5,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_C6 - RESERVED */
+
+ /* GPP_C7 - RESERVED */
+
+ /* GPP_C8 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_C8,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_C9 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_C9,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+
+ /* GPP_C10 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_C10,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_C11 - GPIO */
+ /* PAD_NC(GPP_C11, NONE), */
+ _PAD_CFG_STRUCT(GPP_C11,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_C12 - GPIO */
+ /* PAD_NC(GPP_C12, NONE), */
+ _PAD_CFG_STRUCT(GPP_C12,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_C13 - GPIO */
+ /* PAD_NC(GPP_C13, NONE), */
+ _PAD_CFG_STRUCT(GPP_C13,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_C14 - GPIO */
+ /* PAD_NC(GPP_C14, NONE), */
+ _PAD_CFG_STRUCT(GPP_C14,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_C15 - GPIO */
+ /* PAD_NC(GPP_C15, NONE), */
+ _PAD_CFG_STRUCT(GPP_C15,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_C16 - GPIO */
+ /* PAD_NC(GPP_C16, NONE), */
+ _PAD_CFG_STRUCT(GPP_C16,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_C17 - GPIO */
+ /* PAD_NC(GPP_C17, NONE), */
+ _PAD_CFG_STRUCT(GPP_C17,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_C18 - GPIO */
+ /* PAD_NC(GPP_C18, NONE), */
+ _PAD_CFG_STRUCT(GPP_C18,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_C19 - GPIO */
+ /* PAD_NC(GPP_C19, NONE), */
+ _PAD_CFG_STRUCT(GPP_C19,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_C20 - GPIO */
+ /* PAD_NC(GPP_C20, NONE), */
+ _PAD_CFG_STRUCT(GPP_C20,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_C21 - GPIO */
+ /* PAD_NC(GPP_C21, NONE), */
+ _PAD_CFG_STRUCT(GPP_C21,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_C22 - GPIO */
+ /* PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), */
+ _PAD_CFG_STRUCT(GPP_C22,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1),
+ PAD_PULL(20K_PU)),
+
+ /* GPP_C23 - GPIO */
+ /* PAD_NC(GPP_C23, NONE), */
+ _PAD_CFG_STRUCT(GPP_C23,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D0 - GPIO */
+ /* PAD_NC(GPP_D0, NONE), */
+ _PAD_CFG_STRUCT(GPP_D0,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D1 - GPIO */
+ /* PAD_CFG_GPO(GPP_D1, 1, DEEP), */
+ _PAD_CFG_STRUCT(GPP_D1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_D2 - GPIO */
+ /* PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), */
+ _PAD_CFG_STRUCT(GPP_D2,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1),
+ PAD_PULL(20K_PU)),
+
+ /* GPP_D3 - GPIO */
+ /* PAD_NC(GPP_D3, NONE), */
+ _PAD_CFG_STRUCT(GPP_D3,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D4 - GPIO */
+ /* PAD_CFG_GPO(GPP_D4, 0, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_D4,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+
+ /* GPP_D5 - GPIO */
+ /* PAD_NC(GPP_D5, NONE), */
+ _PAD_CFG_STRUCT(GPP_D5,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D6 - GPIO */
+ /* PAD_NC(GPP_D6, NONE), */
+ _PAD_CFG_STRUCT(GPP_D6,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D7 - GPIO */
+ /* PAD_NC(GPP_D7, NONE), */
+ _PAD_CFG_STRUCT(GPP_D7,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D8 - GPIO */
+ /* PAD_NC(GPP_D8, NONE), */
+ _PAD_CFG_STRUCT(GPP_D8,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D9 - GPIO */
+ /* PAD_NC(GPP_D9, NONE), */
+ _PAD_CFG_STRUCT(GPP_D9,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D10 - GPIO */
+ /* PAD_NC(GPP_D10, NONE), */
+ _PAD_CFG_STRUCT(GPP_D10,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D11 - GPIO */
+ /* PAD_NC(GPP_D11, NONE), */
+ _PAD_CFG_STRUCT(GPP_D11,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D12 - GPIO */
+ /* PAD_NC(GPP_D12, NONE), */
+ _PAD_CFG_STRUCT(GPP_D12,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D13 - GPIO */
+ /* PAD_NC(GPP_D13, NONE), */
+ _PAD_CFG_STRUCT(GPP_D13,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D14 - GPIO */
+ /* PAD_NC(GPP_D14, NONE), */
+ _PAD_CFG_STRUCT(GPP_D14,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D15 - GPIO */
+ /* PAD_NC(GPP_D15, NONE), */
+ _PAD_CFG_STRUCT(GPP_D15,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D16 - GPIO */
+ /* PAD_NC(GPP_D16, NONE), */
+ _PAD_CFG_STRUCT(GPP_D16,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D17 - GPIO */
+ /* PAD_NC(GPP_D17, NONE), */
+ _PAD_CFG_STRUCT(GPP_D17,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D18 - GPIO */
+ /* PAD_CFG_GPO(GPP_D18, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_D18,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_D19 - GPIO */
+ /* PAD_CFG_GPO(GPP_D19, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_D19,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_D20 - GPIO */
+ /* PAD_NC(GPP_D20, NONE), */
+ _PAD_CFG_STRUCT(GPP_D20,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_D21 - GPIO */
+ /* PAD_CFG_GPO(GPP_D21, 0, DEEP), */
+ _PAD_CFG_STRUCT(GPP_D21,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+
+ /* GPP_D22 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PWROK, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_D22,
+ PAD_FUNC(GPIO) | (3 << 30) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_D23 - GPIO */
+ /* PAD_NC(GPP_D23, NONE), */
+ _PAD_CFG_STRUCT(GPP_D23,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_E0 - SATAXPCIE0 */
+ /* PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_E0,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_E1 - GPIO */
+ /* PAD_NC(GPP_E1, NONE), */
+ _PAD_CFG_STRUCT(GPP_E1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_E2 - GPIO */
+ /* PAD_NC(GPP_E2, NONE), */
+ _PAD_CFG_STRUCT(GPP_E2,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_E3 - GPIO */
+ /* PAD_NC(GPP_E3, NONE), */
+ _PAD_CFG_STRUCT(GPP_E3,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_E4 - GPIO */
+ /* PAD_NC(GPP_E4, NONE), */
+ _PAD_CFG_STRUCT(GPP_E4,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_E5 - GPIO */
+ /* PAD_NC(GPP_E5, NONE), */
+ _PAD_CFG_STRUCT(GPP_E5,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_E6 - GPIO */
+ /* PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), */
+ _PAD_CFG_STRUCT(GPP_E6,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1),
+ PAD_PULL(20K_PU)),
+
+ /* GPP_E7 - GPIO */
+ /* PAD_NC(GPP_E7, NONE), */
+ _PAD_CFG_STRUCT(GPP_E7,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_E8 - SATA_LED# */
+ /* PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_E8,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_E9 - USB_OC0# */
+ /* PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_E9,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_E10 - USB_OC1# */
+ /* PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_E10,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_E11 - USB_OC2# */
+ /* PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_E11,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_E12 - USB_OC3# */
+ /* PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_E12,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_F0 - GPIO */
+ /* PAD_NC(GPP_F0, NONE), */
+ _PAD_CFG_STRUCT(GPP_F0,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F1 - GPIO */
+ /* PAD_NC(GPP_F1, NONE), */
+ _PAD_CFG_STRUCT(GPP_F1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F2 - GPIO */
+ /* PAD_NC(GPP_F2, NONE), */
+ _PAD_CFG_STRUCT(GPP_F2,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F3 - GPIO */
+ /* PAD_NC(GPP_F3, NONE), */
+ _PAD_CFG_STRUCT(GPP_F3,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F4 - GPIO */
+ /* PAD_NC(GPP_F4, NONE), */
+ _PAD_CFG_STRUCT(GPP_F4,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F5 - GPIO */
+ /* PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_F5,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_F6 - GPIO */
+ /* PAD_CFG_GPO(GPP_F6, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_F6,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_F7 - GPIO */
+ /* PAD_CFG_GPO(GPP_F7, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_F7,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_F8 - GPIO */
+ /* PAD_CFG_GPO(GPP_F8, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_F8,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_F9 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_F9,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_F10 - SATA_SCLOCK */
+ /* PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_F10,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F11 - SATA_SLOAD */
+ /* PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_F11,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F12 - SATA_SDATAOUT1 */
+ /* PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_F12,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F13 - SATA_SDATAOUT2 */
+ /* PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_F13,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F14 - GPIO */
+ /* PAD_NC(GPP_F14, NONE), */
+ _PAD_CFG_STRUCT(GPP_F14,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F15 - USB_OC4# */
+ /* PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_F15,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_F16 - USB_OC5# */
+ /* PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_F16,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_F17 - GPIO */
+ /* PAD_NC(GPP_F17, NONE), */
+ _PAD_CFG_STRUCT(GPP_F17,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F18 - GPIO */
+ /* PAD_NC(GPP_F18, NONE), */
+ _PAD_CFG_STRUCT(GPP_F18,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F19 - GPIO */
+ /* PAD_NC(GPP_F19, NONE), */
+ _PAD_CFG_STRUCT(GPP_F19,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F20 - GPIO */
+ /* PAD_NC(GPP_F20, NONE), */
+ _PAD_CFG_STRUCT(GPP_F20,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F21 - GPIO */
+ /* PAD_NC(GPP_F21, NONE), */
+ _PAD_CFG_STRUCT(GPP_F21,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F22 - GPIO */
+ /* PAD_NC(GPP_F22, NONE), */
+ _PAD_CFG_STRUCT(GPP_F22,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_F23 - GPIO */
+ /* PAD_CFG_GPO(GPP_F23, 0, PWROK), */
+ _PAD_CFG_STRUCT(GPP_F23,
+ PAD_FUNC(GPIO) | (3 << 30) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+
+ /* GPP_G0 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_G0,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+
+ /* GPP_G1 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_G1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+
+ /* GPP_G2 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_G2,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_G3 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_G3,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_G4 - GPIO */
+ /* PAD_NC(GPP_G4, NONE), */
+ _PAD_CFG_STRUCT(GPP_G4,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G5 - GPIO */
+ /* PAD_NC(GPP_G5, NONE), */
+ _PAD_CFG_STRUCT(GPP_G5,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G6 - GPIO */
+ /* PAD_NC(GPP_G6, NONE), */
+ _PAD_CFG_STRUCT(GPP_G6,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G7 - GPIO */
+ /* PAD_NC(GPP_G7, NONE), */
+ _PAD_CFG_STRUCT(GPP_G7,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G8 - GPIO */
+ /* PAD_NC(GPP_G8, NONE), */
+ _PAD_CFG_STRUCT(GPP_G8,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G9 - GPIO */
+ /* PAD_NC(GPP_G9, NONE), */
+ _PAD_CFG_STRUCT(GPP_G9,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G10 - GPIO */
+ /* PAD_NC(GPP_G10, NONE), */
+ _PAD_CFG_STRUCT(GPP_G10,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G11 - GPIO */
+ /* PAD_NC(GPP_G11, NONE), */
+ _PAD_CFG_STRUCT(GPP_G11,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G12 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_G12,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+
+ /* GPP_G13 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_G13,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+
+ /* GPP_G14 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_G14,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_G15 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_G15,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+
+ /* GPP_G16 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_G16,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+
+ /* GPP_G17 - GPIO */
+ /* PAD_NC(GPP_G17, NONE), */
+ _PAD_CFG_STRUCT(GPP_G17,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G18 - NMI# */
+ /* PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_G18,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G19 - SMI# */
+ /* PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_G19,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G20 - GPIO */
+ /* PAD_NC(GPP_G20, NONE), */
+ _PAD_CFG_STRUCT(GPP_G20,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G21 - GPIO */
+ /* PAD_NC(GPP_G21, NONE), */
+ _PAD_CFG_STRUCT(GPP_G21,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G22 - GPIO */
+ /* PAD_NC(GPP_G22, NONE), */
+ _PAD_CFG_STRUCT(GPP_G22,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G23 - GPIO */
+ /* PAD_NC(GPP_G23, NONE), */
+ _PAD_CFG_STRUCT(GPP_G23,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_H0 - GPIO */
+ /* PAD_CFG_GPO(GPP_H0, 1, DEEP), */
+ _PAD_CFG_STRUCT(GPP_H0,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_H1 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_H1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),
+
+ /* GPP_H2 - GPIO */
+ /* PAD_CFG_GPO(GPP_H2, 1, DEEP), */
+ _PAD_CFG_STRUCT(GPP_H2,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_H3 - SRCCLKREQ9# */
+ /* PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_H3,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_H4 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, ACPI), */
+ _PAD_CFG_STRUCT(GPP_H4,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),
+
+ /* GPP_H5 - GPIO */
+ /* PAD_CFG_GPO(GPP_H5, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_H5,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_H6 - GPIO */
+ /* PAD_CFG_GPO(GPP_H6, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_H6,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_H7 - GPIO */
+ /* PAD_CFG_GPO(GPP_H7, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_H7,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_H8 - GPIO */
+ /* PAD_CFG_GPO(GPP_H8, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_H8,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_H9 - GPIO */
+ /* PAD_CFG_GPO(GPP_H9, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_H9,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_H10 - SML2CLK */
+ /* PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_H10,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_H11 - SML2DATA */
+ /* PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_H11,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_H12 - GPIO */
+ /* PAD_NC(GPP_H12, NONE), */
+ _PAD_CFG_STRUCT(GPP_H12,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_H13 - SML3CLK */
+ /* PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_H13,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_H14 - SML3DATA */
+ /* PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_H14,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_H15 - GPIO */
+ /* PAD_NC(GPP_H15, NONE), */
+ _PAD_CFG_STRUCT(GPP_H15,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_H16 - SML4CLK */
+ /* PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_H16,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_H17 - SML4DATA */
+ /* PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_H17,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_H18 - GPIO */
+ /* PAD_NC(GPP_H18, NONE), */
+ _PAD_CFG_STRUCT(GPP_H18,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_H19 - GPIO */
+ /* PAD_CFG_GPO(GPP_H19, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_H19,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_H20 - GPIO */
+ /* PAD_CFG_GPO(GPP_H20, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_H20,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_H21 - GPIO */
+ /* PAD_CFG_GPO(GPP_H21, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_H21,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_H22 - GPIO */
+ /* PAD_CFG_GPO(GPP_H22, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_H22,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPP_H23 - GPIO */
+ /* PAD_CFG_GPO(GPP_H23, 1, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_H23,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
+
+ /* GPD0 - GPIO */
+ /* PAD_NC(GPD0, NONE), */
+ _PAD_CFG_STRUCT(GPD0,
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPD1 - GPIO */
+ /* PAD_NC(GPD1, NONE), */
+ _PAD_CFG_STRUCT(GPD1,
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPD2 - LAN_WAKE# */
+ /* PAD_CFG_NF(GPD2, NONE, PWROK, NF1), */
+ _PAD_CFG_STRUCT(GPD2,
+ PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPD3 - PWRBTN# */
+ /* PAD_CFG_NF(GPD3, NONE, PWROK, NF1), */
+ _PAD_CFG_STRUCT(GPD3,
+ PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPD4 - SLP_S3# */
+ /* PAD_CFG_NF(GPD4, NONE, PWROK, NF1), */
+ _PAD_CFG_STRUCT(GPD4,
+ PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPD5 - SLP_S4# */
+ /* PAD_CFG_NF(GPD5, NONE, PWROK, NF1), */
+ _PAD_CFG_STRUCT(GPD5,
+ PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPD6 - SLP_A# */
+ /* PAD_CFG_NF(GPD6, NONE, PWROK, NF1), */
+ _PAD_CFG_STRUCT(GPD6,
+ PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPD7 - GPIO */
+ /* PAD_NC(GPD7, NONE), */
+ _PAD_CFG_STRUCT(GPD7,
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
+
+ /* GPD8 - SUSCLK */
+ /* PAD_CFG_NF(GPD8, NONE, PWROK, NF1), */
+ _PAD_CFG_STRUCT(GPD8,
+ PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPD9 - GPIO */
+ /* PAD_NC(GPD9, NONE), */
+ _PAD_CFG_STRUCT(GPD9,
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPD10 - GPIO */
+ /* PAD_NC(GPD10, NONE), */
+ _PAD_CFG_STRUCT(GPD10,
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPD11 - GPIO */
+ /* PAD_NC(GPD11, NONE), */
+ _PAD_CFG_STRUCT(GPD11,
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_I0 - DDPB_HPD0 */
+ /* PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I0,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_I1 - DDPC_HPD1 */
+ /* PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I1,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_I2 - DDPD_HPD2 */
+ /* PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I2,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_I3 - DDPE_HPD3 */
+ /* PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), */
+ _PAD_CFG_STRUCT(GPP_I3,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_I4 - GPIO */
+ /* PAD_NC(GPP_I4, NONE), */
+ _PAD_CFG_STRUCT(GPP_I4,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_I5 - DDPB_CTRLCLK */
+ /* PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I5,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_I6 - DDPB_CTRLDATA */
+ /* PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I6,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_I7 - DDPC_CTRLCLK */
+ /* PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I7,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_I8 - DDPC_CTRLDATA */
+ /* PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I8,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_I9 - DDPD_CTRLCLK */
+ /* PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I9,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_I10 - DDPD_CTRLDATA */
+ /* PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I10,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
};
/*** XXX TODO XXX */
/* Early pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = {
-/* LPC */
+ /* LPC */
-/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000),
-/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000),
-/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000),
-/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000),
-/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000),
-/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000),
-/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000),
-/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000),
-/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000),
+ /* GPP_A1 - LAD0 */
+ /* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A1,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_A2 - LAD1 */
+ /* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A2,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A3 - LAD2 */
+ /* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A3,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+
+ /* GPP_A4 - LAD3 */
+ /* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A4,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A5 - LFRAME# */
+ /* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A5,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A6 - SERIRQ */
+ /* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A6,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A8 - CLKRUN# */
+ /* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A8,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A9 - CLKOUT_LPC0 */
+ /* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A9,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_A10 - CLKOUT_LPC1 */
+ /* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A10,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
};
#endif /* _GPIO_X11SSH_TF_H */
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
index 0c47a9d..34960bf 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
@@ -6,251 +6,1306 @@
#include <soc/gpe.h>
#include <soc/gpio.h>
+/* Pad configuration was generated automatically using intelp2m utility */
static const struct pad_config gpio_table[] = {
/* GPIO Group GPP_A */
- _PAD_CFG_STRUCT(GPP_A0, 0x44000700, 0x00000010), /* RCIN# */
- _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */
- _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */
- _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */
- _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */
- _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */
- _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */
- _PAD_CFG_STRUCT(GPP_A7, 0x44000700, 0x00000010), /* PIRQA# */
- _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */
- _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */
- _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */
- _PAD_CFG_STRUCT(GPP_A11, 0x44000700, 0x00000010), /* PME# */
- _PAD_CFG_STRUCT(GPP_A12, 0x84000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000010), /* SUSWARN#/SUSPWRDNACK */
- _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000010), /* SUS_STAT# */
- _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x00000010), /* SUS_ACK# */
- _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000010), /* CLKOUT_48 */
- _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000010), /* GPIO */
- /* reserved */
- //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffffff), /* ISH_GP1 */
- _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000010), /* GPIO */
+
+ /* GPP_A0 - RCIN# */
+ /* PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A0,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A1 - LAD0 */
+ /* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A1,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A2 - LAD1 */
+ /* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A2,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A3 - LAD2 */
+ /* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A3,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A4 - LAD3 */
+ /* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A4,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A5 - LFRAME# */
+ /* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A5,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A6 - SERIRQ */
+ /* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A6,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A7 - PIRQA# */
+ /* PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A7,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A8 - CLKRUN# */
+ /* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A8,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A9 - CLKOUT_LPC0 */
+ /* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A9,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A10 - CLKOUT_LPC1 */
+ /* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A10,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A11 - PME# */
+ /* PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A11,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A12 - GPIO */
+ /* PAD_NC(GPP_A12, NONE), */
+ _PAD_CFG_STRUCT(GPP_A12,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A13 - SUSWARN#/SUSPWRDNACK */
+ /* PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A13,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A14 - SUS_STAT# */
+ /* PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A14,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A15 - SUS_ACK# */
+ /* PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A15,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A16 - CLKOUT_48 */
+ /* PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A16,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A17 - GPIO */
+ /* PAD_NC(GPP_A17, NONE), */
+ _PAD_CFG_STRUCT(GPP_A17,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A18 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, PLTRST, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_A18,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A19 - ISH_GP1 (RESERVED) */
+
+ /* GPP_A20 - GPIO */
+ /* PAD_NC(GPP_A20, NONE), */
+ _PAD_CFG_STRUCT(GPP_A20,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A21 - GPIO */
+ /* PAD_NC(GPP_A21, NONE), */
+ _PAD_CFG_STRUCT(GPP_A21,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A22 - GPIO */
+ /* PAD_NC(GPP_A22, NONE), */
+ _PAD_CFG_STRUCT(GPP_A22,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A23 - GPIO */
+ /* PAD_NC(GPP_A23, NONE), */
+ _PAD_CFG_STRUCT(GPP_A23,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_B */
- _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000010), /* SLP_S0# */
- _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000010), /* PLTRST# */
- _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000010), /* SPKR */
- _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000010), /* PCHHOT# */
+
+ /* GPP_B0 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_B0, 1, DEEP, NONE), */
+ _PAD_CFG_STRUCT(GPP_B0,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B1 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_B1, 1, DEEP, NONE), */
+ _PAD_CFG_STRUCT(GPP_B1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B2 - GPIO */
+ /* PAD_NC(GPP_B2, NONE), */
+ _PAD_CFG_STRUCT(GPP_B2,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B3 - GPIO */
+ /* PAD_NC(GPP_B3, NONE), */
+ _PAD_CFG_STRUCT(GPP_B3,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B4 - GPIO */
+ /* PAD_NC(GPP_B4, NONE), */
+ _PAD_CFG_STRUCT(GPP_B4,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B5 - GPIO */
+ /* PAD_NC(GPP_B5, NONE), */
+ _PAD_CFG_STRUCT(GPP_B5,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B6 - GPIO */
+ /* PAD_NC(GPP_B6, NONE), */
+ _PAD_CFG_STRUCT(GPP_B6,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B7 - GPIO */
+ /* PAD_NC(GPP_B7, NONE), */
+ _PAD_CFG_STRUCT(GPP_B7,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B8 - GPIO */
+ /* PAD_NC(GPP_B8, NONE), */
+ _PAD_CFG_STRUCT(GPP_B8,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B9 - GPIO */
+ /* PAD_NC(GPP_B9, NONE), */
+ _PAD_CFG_STRUCT(GPP_B9,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B10 - GPIO */
+ /* PAD_NC(GPP_B10, NONE), */
+ _PAD_CFG_STRUCT(GPP_B10,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B11 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE), */
+ _PAD_CFG_STRUCT(GPP_B11,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B12 - SLP_S0# */
+ /* PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_B12,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B13 - PLTRST# */
+ /* PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_B13,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B14 - SPKR */
+ /* PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), */
+ _PAD_CFG_STRUCT(GPP_B14,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B15 - GPIO */
+ /* PAD_NC(GPP_B15, NONE), */
+ _PAD_CFG_STRUCT(GPP_B15,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B16 - GPIO */
+ /* PAD_NC(GPP_B16, NONE), */
+ _PAD_CFG_STRUCT(GPP_B16,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B17 - GPIO */
+ /* PAD_NC(GPP_B17, NONE), */
+ _PAD_CFG_STRUCT(GPP_B17,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B18 - GPIO */
+ /* PAD_NC(GPP_B18, NONE), */
+ _PAD_CFG_STRUCT(GPP_B18,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B19 - GPIO */
+ /* PAD_NC(GPP_B19, NONE), */
+ _PAD_CFG_STRUCT(GPP_B19,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B20 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_B20, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_B20,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B21 - GPIO */
+ /* PAD_NC(GPP_B21, NONE), */
+ _PAD_CFG_STRUCT(GPP_B21,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B22 - GPIO */
+ /* PAD_NC(GPP_B22, NONE), */
+ _PAD_CFG_STRUCT(GPP_B22,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_B23 - PCHHOT# */
+ /* PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), */
+ _PAD_CFG_STRUCT(GPP_B23,
+ PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_C */
- /* reserved */
- //_PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x00000010), /* SMBCLK */
- //_PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x00000010), /* SMBDATA */
- _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000010), /* GPIO */
- /* reserved */
- //_PAD_CFG_STRUCT(GPP_C3, 0x44000700, 0x00000010), /* SML0CLK */
- //_PAD_CFG_STRUCT(GPP_C4, 0x44000700, 0x00000010), /* SML0DATA */
- _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000010), /* GPIO */
- /* reserved */
- //_PAD_CFG_STRUCT(GPP_C6, 0x44000700, 0x00000010), /* SML1CLK */
- //_PAD_CFG_STRUCT(GPP_C7, 0x44000700, 0x00000010), /* SML1DATA */
- _PAD_CFG_STRUCT(GPP_C8, 0x84000100, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_C10, 0x84000100, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_C22, 0x42040100, 0x00003010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000010), /* GPIO */
+
+ /* GPP_C0 - SMBCLK (RESERVED) */
+ /* PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), */
+ //_PAD_CFG_STRUCT(GPP_C0,
+ // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ // PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C1 - SMBDATA (RESERVED) */
+ /* PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), */
+ //_PAD_CFG_STRUCT(GPP_C1,
+ // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ // PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C2 - GPIO */
+ /* PAD_NC(GPP_C2, NONE), */
+ _PAD_CFG_STRUCT(GPP_C2,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C3 - SML0CLK (RESERVED) */
+ /* PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), */
+ //_PAD_CFG_STRUCT(GPP_C3,
+ // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ // PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C4 - SML0DATA (RESERVED) */
+ /* PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), */
+ //_PAD_CFG_STRUCT(GPP_C4,
+ // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ // PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C5 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_C5, 1, DEEP, NONE), */
+ _PAD_CFG_STRUCT(GPP_C5,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C6 - SML1CLK (RESERVED) */
+ /* PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), */
+ //_PAD_CFG_STRUCT(GPP_C6,
+ // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ // PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C7 - SML1DATA (RESERVED) */
+ /* PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), */
+ //_PAD_CFG_STRUCT(GPP_C7,
+ // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ // PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C8 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_C8,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C9 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_C9,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C10 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_C10,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C11 - GPIO */
+ /* PAD_NC(GPP_C11, NONE), */
+ _PAD_CFG_STRUCT(GPP_C11,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C12 - GPIO */
+ /* PAD_NC(GPP_C12, NONE), */
+ _PAD_CFG_STRUCT(GPP_C12,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C13 - GPIO */
+ /* PAD_NC(GPP_C13, NONE), */
+ _PAD_CFG_STRUCT(GPP_C13,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C14 - GPIO */
+ /* PAD_NC(GPP_C14, NONE), */
+ _PAD_CFG_STRUCT(GPP_C14,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C15 - GPIO */
+ /* PAD_NC(GPP_C15, NONE), */
+ _PAD_CFG_STRUCT(GPP_C15,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C16 - GPIO */
+ /* PAD_NC(GPP_C16, NONE), */
+ _PAD_CFG_STRUCT(GPP_C16,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C17 - GPIO */
+ /* PAD_NC(GPP_C17, NONE), */
+ _PAD_CFG_STRUCT(GPP_C17,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C18 - GPIO */
+ /* PAD_NC(GPP_C18, NONE), */
+ _PAD_CFG_STRUCT(GPP_C18,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C19 - GPIO */
+ /* PAD_NC(GPP_C19, NONE), */
+ _PAD_CFG_STRUCT(GPP_C19,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C20 - GPIO */
+ /* PAD_NC(GPP_C20, NONE), */
+ _PAD_CFG_STRUCT(GPP_C20,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C21 - GPIO */
+ /* PAD_NC(GPP_C21, NONE), */
+ _PAD_CFG_STRUCT(GPP_C21,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C22 - GPIO */
+ /* PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), */
+ _PAD_CFG_STRUCT(GPP_C22,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE),
+ PAD_PULL(20K_PU) | PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_C23 - GPIO */
+ /* PAD_NC(GPP_C23, NONE), */
+ _PAD_CFG_STRUCT(GPP_C23,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_D */
- _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D2, 0x42020100, 0x00003000), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D22, 0xc4000100, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000010), /* GPIO */
+
+ /* GPP_D0 - GPIO */
+ /* PAD_NC(GPP_D0, NONE), */
+ _PAD_CFG_STRUCT(GPP_D0,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D1 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), */
+ _PAD_CFG_STRUCT(GPP_D1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D2 - GPIO */
+ /* PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), */
+ _PAD_CFG_STRUCT(GPP_D2,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE),
+ PAD_PULL(20K_PU)),
+
+ /* GPP_D3 - GPIO */
+ /* PAD_NC(GPP_D3, NONE), */
+ _PAD_CFG_STRUCT(GPP_D3,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D4 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_D4,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D5 - GPIO */
+ /* PAD_NC(GPP_D5, NONE), */
+ _PAD_CFG_STRUCT(GPP_D5,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D6 - GPIO */
+ /* PAD_NC(GPP_D6, NONE), */
+ _PAD_CFG_STRUCT(GPP_D6,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D7 - GPIO */
+ /* PAD_NC(GPP_D7, NONE), */
+ _PAD_CFG_STRUCT(GPP_D7,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D8 - GPIO */
+ /* PAD_NC(GPP_D8, NONE), */
+ _PAD_CFG_STRUCT(GPP_D8,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D9 - GPIO */
+ /* PAD_NC(GPP_D9, NONE), */
+ _PAD_CFG_STRUCT(GPP_D9,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D10 - GPIO */
+ /* PAD_NC(GPP_D10, NONE), */
+ _PAD_CFG_STRUCT(GPP_D10,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D11 - GPIO */
+ /* PAD_NC(GPP_D11, NONE), */
+ _PAD_CFG_STRUCT(GPP_D11,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D12 - GPIO */
+ /* PAD_NC(GPP_D12, NONE), */
+ _PAD_CFG_STRUCT(GPP_D12,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D13 - GPIO */
+ /* PAD_NC(GPP_D13, NONE), */
+ _PAD_CFG_STRUCT(GPP_D13,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D14 - GPIO */
+ /* PAD_NC(GPP_D14, NONE), */
+ _PAD_CFG_STRUCT(GPP_D14,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D15 - GPIO */
+ /* PAD_NC(GPP_D15, NONE), */
+ _PAD_CFG_STRUCT(GPP_D15,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D16 - GPIO */
+ /* PAD_NC(GPP_D16, NONE), */
+ _PAD_CFG_STRUCT(GPP_D16,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D17 - GPIO */
+ /* PAD_NC(GPP_D17, NONE), */
+ _PAD_CFG_STRUCT(GPP_D17,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D18 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_D18,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D19 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_D19,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D20 - GPIO */
+ /* PAD_NC(GPP_D20, NONE), */
+ _PAD_CFG_STRUCT(GPP_D20,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D21 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE), */
+ _PAD_CFG_STRUCT(GPP_D21,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D22 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PWROK, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_D22,
+ PAD_FUNC(GPIO) | (3 << 30) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_D23 - GPIO */
+ /* PAD_NC(GPP_D23, NONE), */
+ _PAD_CFG_STRUCT(GPP_D23,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_E */
- _PAD_CFG_STRUCT(GPP_E0, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_E6, 0x82020100, 0x00003000), /* GPIO */
- _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000010), /* SATA_LED# */
- _PAD_CFG_STRUCT(GPP_E9, 0x44000700, 0x00000010), /* USB_OC0# */
- _PAD_CFG_STRUCT(GPP_E10, 0x44000700, 0x00000010), /* USB_OC1# */
- _PAD_CFG_STRUCT(GPP_E11, 0x44000700, 0x00000010), /* USB_OC2# */
- _PAD_CFG_STRUCT(GPP_E12, 0x44000700, 0x00000010), /* USB_OC3# */
+
+ /* GPP_E0 - GPIO */
+ /* PAD_NC(GPP_E0, NONE), */
+ _PAD_CFG_STRUCT(GPP_E0,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_E1 - GPIO */
+ /* PAD_NC(GPP_E1, NONE), */
+ _PAD_CFG_STRUCT(GPP_E1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_E2 - GPIO */
+ /* PAD_NC(GPP_E2, NONE), */
+ _PAD_CFG_STRUCT(GPP_E2,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_E3 - GPIO */
+ /* PAD_NC(GPP_E3, NONE), */
+ _PAD_CFG_STRUCT(GPP_E3,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_E4 - GPIO */
+ /* PAD_NC(GPP_E4, NONE), */
+ _PAD_CFG_STRUCT(GPP_E4,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_E5 - GPIO */
+ /* PAD_NC(GPP_E5, NONE), */
+ _PAD_CFG_STRUCT(GPP_E5,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_E6 - GPIO */
+ /* PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), */
+ _PAD_CFG_STRUCT(GPP_E6,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE),
+ PAD_PULL(20K_PU)),
+
+ /* GPP_E7 - GPIO */
+ /* PAD_NC(GPP_E7, NONE), */
+ _PAD_CFG_STRUCT(GPP_E7,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_E8 - SATA_LED# */
+ /* PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_E8,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_E9 - USB_OC0# */
+ /* PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_E9,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_E10 - USB_OC1# */
+ /* PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_E10,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_E11 - USB_OC2# */
+ /* PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_E11,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_E12 - USB_OC3# */
+ /* PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_E12,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_F */
- _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F5, 0x80100100, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F9, 0x84000100, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000010), /* SATA_SCLOCK */
- _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000010), /* SATA_SLOAD */
- _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000010), /* SATA_SDATAOUT1 */
- _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000010), /* SATA_SDATAOUT2 */
- _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x00000010), /* USB_OC4# */
- _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x00000010), /* USB_OC5# */
- _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_F23, 0xc4000200, 0x00000010), /* GPIO */
+
+ /* GPP_F0 - GPIO */
+ /* PAD_NC(GPP_F0, NONE), */
+ _PAD_CFG_STRUCT(GPP_F0,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F1 - GPIO */
+ /* PAD_NC(GPP_F1, NONE), */
+ _PAD_CFG_STRUCT(GPP_F1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F2 - GPIO */
+ /* PAD_NC(GPP_F2, NONE), */
+ _PAD_CFG_STRUCT(GPP_F2,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F3 - GPIO */
+ /* PAD_NC(GPP_F3, NONE), */
+ _PAD_CFG_STRUCT(GPP_F3,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F4 - GPIO */
+ /* PAD_NC(GPP_F4, NONE), */
+ _PAD_CFG_STRUCT(GPP_F4,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F5 - GPIO */
+ /* PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), */
+ _PAD_CFG_STRUCT(GPP_F5,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F6 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_F6,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F7 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_F7,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F8 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_F8,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F9 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_F9,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F10 - SATA_SCLOCK */
+ /* PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_F10,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F11 - SATA_SLOAD */
+ /* PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_F11,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F12 - SATA_SDATAOUT1 */
+ /* PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_F12,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F13 - SATA_SDATAOUT2 */
+ /* PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_F13,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F14 - GPIO */
+ /* PAD_NC(GPP_F14, NONE), */
+ _PAD_CFG_STRUCT(GPP_F14,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F15 - USB_OC4# */
+ /* PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_F15,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F16 - USB_OC5# */
+ /* PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_F16,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F17 - GPIO */
+ /* PAD_NC(GPP_F17, NONE), */
+ _PAD_CFG_STRUCT(GPP_F17,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F18 - GPIO */
+ /* PAD_NC(GPP_F18, NONE), */
+ _PAD_CFG_STRUCT(GPP_F18,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F19 - GPIO */
+ /* PAD_NC(GPP_F19, NONE), */
+ _PAD_CFG_STRUCT(GPP_F19,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F20 - GPIO */
+ /* PAD_NC(GPP_F20, NONE), */
+ _PAD_CFG_STRUCT(GPP_F20,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F21 - GPIO */
+ /* PAD_NC(GPP_F21, NONE), */
+ _PAD_CFG_STRUCT(GPP_F21,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F22 - GPIO */
+ /* PAD_NC(GPP_F22, NONE), */
+ _PAD_CFG_STRUCT(GPP_F22,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_F23 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, PWROK, NONE), */
+ _PAD_CFG_STRUCT(GPP_F23,
+ PAD_FUNC(GPIO) | (3 << 30) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_G */
- _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G2, 0x44000100, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G14, 0x84000100, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000010), /* NMI# */
- _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000010), /* SMI# */
- _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), /* GPIO */
- _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000010), /* GPIO */
+
+ /* GPP_G0 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_G0,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G1 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_G1,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G2 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_G2,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G3 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_G3,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G4 - GPIO */
+ /* PAD_NC(GPP_G4, NONE), */
+ _PAD_CFG_STRUCT(GPP_G4,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G5 - GPIO */
+ /* PAD_NC(GPP_G5, NONE), */
+ _PAD_CFG_STRUCT(GPP_G5,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G6 - GPIO */
+ /* PAD_NC(GPP_G6, NONE), */
+ _PAD_CFG_STRUCT(GPP_G6,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G7 - GPIO */
+ /* PAD_NC(GPP_G7, NONE), */
+ _PAD_CFG_STRUCT(GPP_G7,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G8 - GPIO */
+ /* PAD_NC(GPP_G8, NONE), */
+ _PAD_CFG_STRUCT(GPP_G8,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G9 - GPIO */
+ /* PAD_NC(GPP_G9, NONE), */
+ _PAD_CFG_STRUCT(GPP_G9,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G10 - GPIO */
+ /* PAD_NC(GPP_G10, NONE), */
+ _PAD_CFG_STRUCT(GPP_G10,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G11 - GPIO */
+ /* PAD_NC(GPP_G11, NONE), */
+ _PAD_CFG_STRUCT(GPP_G11,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G12 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_G12,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G13 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_G13,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G14 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_G14,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G15 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_G15,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G16 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_G16,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G17 - GPIO */
+ /* PAD_NC(GPP_G17, NONE), */
+ _PAD_CFG_STRUCT(GPP_G17,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G18 - NMI# */
+ /* PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_G18,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G19 - SMI# */
+ /* PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_G19,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_G20 - GPIO */
+ /* PAD_NC(GPP_G20, NONE), */
+ _PAD_CFG_STRUCT(GPP_G20,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G21 - GPIO */
+ /* PAD_NC(GPP_G21, NONE), */
+ _PAD_CFG_STRUCT(GPP_G21,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G22 - GPIO */
+ /* PAD_NC(GPP_G22, NONE), */
+ _PAD_CFG_STRUCT(GPP_G22,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+
+ /* GPP_G23 - GPIO */
+ /* PAD_NC(GPP_G23, NONE), */
+ _PAD_CFG_STRUCT(GPP_G23,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_H */
- _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H1, 0x84000101, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H3, 0x44000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H4, 0x84000101, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H10, 0x44000700, 0x00000010), /* SML2CLK */
- _PAD_CFG_STRUCT(GPP_H11, 0x44000700, 0x00000010), /* SML2DATA */
- _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H13, 0x44000700, 0x00000010), /* SML3CLK */
- _PAD_CFG_STRUCT(GPP_H14, 0x44000700, 0x00000010), /* SML3DATA */
- _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H16, 0x44000700, 0x00000010), /* SML4CLK */
- _PAD_CFG_STRUCT(GPP_H17, 0x44000700, 0x00000010), /* SML4DATA */
- _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000010), /* GPIO */
+
+ /* GPP_H0 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, DEEP, NONE), */
+ _PAD_CFG_STRUCT(GPP_H0,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H1 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_H1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H2 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, DEEP, NONE), */
+ _PAD_CFG_STRUCT(GPP_H2,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H3 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H3, 1, DEEP, NONE), */
+ _PAD_CFG_STRUCT(GPP_H3,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H4 - GPIO */
+ /* PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, DRIVER), */
+ _PAD_CFG_STRUCT(GPP_H4,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H5 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H5, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_H5,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H6 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H6, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_H6,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H7 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H7, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_H7,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H8 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H8, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_H8,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H9 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H9, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_H9,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H10 - SML2CLK */
+ /* PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_H10,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H11 - SML2DATA */
+ /* PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_H11,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H12 - GPIO */
+ /* PAD_NC(GPP_H12, NONE), */
+ _PAD_CFG_STRUCT(GPP_H12,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H13 - SML3CLK */
+ /* PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_H13,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H14 - SML3DATA */
+ /* PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_H14,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H15 - GPIO */
+ /* PAD_NC(GPP_H15, NONE), */
+ _PAD_CFG_STRUCT(GPP_H15,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H16 - SML4CLK */
+ /* PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_H16,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H17 - SML4DATA */
+ /* PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_H17,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H18 - GPIO */
+ /* PAD_NC(GPP_H18, NONE), */
+ _PAD_CFG_STRUCT(GPP_H18,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H19 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H19, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_H19,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H20 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H20, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_H20,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H21 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H21, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_H21,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H22 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H22, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_H22,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_H23 - GPIO */
+ /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H23, 1, PLTRST, NONE), */
+ _PAD_CFG_STRUCT(GPP_H23,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_I */
- _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000010), /* DDPB_HPD0 */
- _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000010), /* DDPC_HPD1 */
- _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000010), /* DDPD_HPD2 */
- _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000010), /* DDPE_HPD3 */
- _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000010), /* DDPB_CTRLCLK */
- _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000010), /* DDPB_CTRLDATA */
- _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000010), /* DDPC_CTRLCLK */
- _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000010), /* DDPC_CTRLDATA */
- _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000010), /* DDPD_CTRLCLK */
- _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000010), /* DDPD_CTRLDATA */
+
+ /* GPP_I0 - DDPB_HPD0 */
+ /* PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I0,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_I1 - DDPC_HPD1 */
+ /* PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I1,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_I2 - DDPD_HPD2 */
+ /* PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I2,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_I3 - DDPE_HPD3 */
+ /* PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), */
+ _PAD_CFG_STRUCT(GPP_I3,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_I4 - GPIO */
+ /* PAD_NC(GPP_I4, NONE), */
+ _PAD_CFG_STRUCT(GPP_I4,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_I5 - DDPB_CTRLCLK */
+ /* PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I5,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_I6 - DDPB_CTRLDATA */
+ /* PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I6,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_I7 - DDPC_CTRLCLK */
+ /* PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I7,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_I8 - DDPC_CTRLDATA */
+ /* PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I8,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_I9 - DDPD_CTRLCLK */
+ /* PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I9,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_I10 - DDPD_CTRLDATA */
+ /* PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_I10,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPD */
- _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPD2, 0x04000700, 0x00000010), /* LAN_WAKE# */
- _PAD_CFG_STRUCT(GPD3, 0x04000700, 0x00000010), /* PWRBTN# */
- _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000010), /* SLP_S3# */
- _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000010), /* SLP_S4# */
- _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000010), /* SLP_A# */
- _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000010), /* SUSCLK */
- _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000010), /* GPIO */
- _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000010), /* GPIO */
+
+ /* GPD0 - GPIO */
+ /* PAD_NC(GPD0, NONE), */
+ _PAD_CFG_STRUCT(GPD0,
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPD1 - GPIO */
+ /* PAD_NC(GPD1, NONE), */
+ _PAD_CFG_STRUCT(GPD1,
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPD2 - LAN_WAKE# */
+ /* PAD_CFG_NF(GPD2, NONE, PWROK, NF1), */
+ _PAD_CFG_STRUCT(GPD2,
+ PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPD3 - PWRBTN# */
+ /* PAD_CFG_NF(GPD3, NONE, PWROK, NF1), */
+ _PAD_CFG_STRUCT(GPD3,
+ PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPD4 - SLP_S3# */
+ /* PAD_CFG_NF(GPD4, NONE, PWROK, NF1), */
+ _PAD_CFG_STRUCT(GPD4,
+ PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPD5 - SLP_S4# */
+ /* PAD_CFG_NF(GPD5, NONE, PWROK, NF1), */
+ _PAD_CFG_STRUCT(GPD5,
+ PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPD6 - SLP_A# */
+ /* PAD_CFG_NF(GPD6, NONE, PWROK, NF1), */
+ _PAD_CFG_STRUCT(GPD6,
+ PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPD7 - GPIO */
+ /* PAD_NC(GPD7, NONE), */
+ _PAD_CFG_STRUCT(GPD7,
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1,
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPD8 - SUSCLK */
+ /* PAD_CFG_NF(GPD8, NONE, PWROK, NF1), */
+ _PAD_CFG_STRUCT(GPD8,
+ PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPD9 - GPIO */
+ /* PAD_NC(GPD9, NONE), */
+ _PAD_CFG_STRUCT(GPD9,
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPD10 - GPIO */
+ /* PAD_NC(GPD10, NONE), */
+ _PAD_CFG_STRUCT(GPD10,
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPD11 - GPIO */
+ /* PAD_NC(GPD11, NONE), */
+ _PAD_CFG_STRUCT(GPD11,
+ PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
};
/* Early pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = {
/* GPIO Group GPP_A */
/* LPC */
- _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */
- _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */
- _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */
- _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */
- _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */
- _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */
- _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */
- _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */
+
+ /* GPP_A1 - LAD0 */
+ /* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A1,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A2 - LAD1 */
+ /* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A2,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A3 - LAD2 */
+ /* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A3,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A4 - LAD3 */
+ /* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A4,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A5 - LFRAME# */
+ /* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A5,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A8 - CLKRUN# */
+ /* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A8,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A9 - CLKOUT_LPC0 */
+ /* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A9,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
+
+ /* GPP_A10 - CLKOUT_LPC1 */
+ /* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A10,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
/* Serial interrupt */
- _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */
+
+ /* GPP_A6 - SERIRQ */
+ /* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */
+ _PAD_CFG_STRUCT(GPP_A6,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
+ PAD_CFG_OWN_GPIO(DRIVER)),
};
#endif /* _GPIO_X11SSM_F_H */
--
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Gerrit-Change-Id: I209ecdca75a0e62233d3726942c75ea06acc40a2
Gerrit-Change-Number: 42916
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Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
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3
22
Change in coreboot[master]: soc/intel/common/gpio_defs: Remove unused macro for NF
by Maxim Polyakov (Code Review) 24 Jul '20
by Maxim Polyakov (Code Review) 24 Jul '20
24 Jul '20
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42913 )
Change subject: soc/intel/common/gpio_defs: Remove unused macro for NF
......................................................................
soc/intel/common/gpio_defs: Remove unused macro for NF
Since the bufdis parameter (bit 9:8 in Pad Configuration DW0 register)
does not affect the pad in native function mode,
PAD_CFG_NF_BUF_IOSSTATE_IOSTERM() macro is not required to configure
the pad. This macro has not been used, so deleting it will not affect
anything.
Change-Id: Icce6f130308dbe7032b99539f73688bae8ac17e0
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
1 file changed, 0 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/42913/1
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
index 0da0240..0668131 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
@@ -225,12 +225,6 @@
PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
-/* Configure native function, iosstate, iosterm and disable input/output buffer */
-#define PAD_CFG_NF_BUF_IOSSTATE_IOSTERM(pad, pull, rst, func, bufdis, iosstate, iosterm) \
- _PAD_CFG_STRUCT(pad, \
- PAD_RESET(rst) | PAD_BUF(bufdis) | PAD_FUNC(func), \
- PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
-
/* General purpose output, no pullup/down. */
#define PAD_CFG_GPO(pad, val, rst) \
_PAD_CFG_STRUCT(pad, \
--
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Gerrit-Change-Id: Icce6f130308dbe7032b99539f73688bae8ac17e0
Gerrit-Change-Number: 42913
Gerrit-PatchSet: 1
Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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2
3
Change in coreboot[master]: soc/intel/common/gpio_defs: Undo set TxDRxE in GPI_TRIG_OWN()
by Maxim Polyakov (Code Review) 24 Jul '20
by Maxim Polyakov (Code Review) 24 Jul '20
24 Jul '20
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42912 )
Change subject: soc/intel/common/gpio_defs: Undo set TxDRxE in GPI_TRIG_OWN()
......................................................................
soc/intel/common/gpio_defs: Undo set TxDRxE in GPI_TRIG_OWN()
IO Standby State can use various settings independently of
PAD_CFG_GPI_TRIG_OWN (). Instead, use other existing macros to set this
parameter:
- PAD_CFG_GPI_IOSSTATE_TRIG_OWN()
- PAD_CFG_GPI_TRIG_IOS_OWN()
Change-Id: I0f5fbd79f892981eb4534f50ac96a7d0c190f59e
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/42912/1
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
index c2c8951..0da0240 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
@@ -285,7 +285,7 @@
_PAD_CFG_STRUCT(pad, \
PAD_FUNC(GPIO) | PAD_RESET(rst) | \
PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \
- PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE) | PAD_CFG_OWN_GPIO(own))
+ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \
_PAD_CFG_STRUCT(pad, \
--
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Gerrit-Change-Id: I0f5fbd79f892981eb4534f50ac96a7d0c190f59e
Gerrit-Change-Number: 42912
Gerrit-PatchSet: 1
Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
2
4
Change in coreboot[master]: soc/intel/common/gpio_defs: Improve some GPI macros
by Maxim Polyakov (Code Review) 24 Jul '20
by Maxim Polyakov (Code Review) 24 Jul '20
24 Jul '20
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42911 )
Change subject: soc/intel/common/gpio_defs: Improve some GPI macros
......................................................................
soc/intel/common/gpio_defs: Improve some GPI macros
The patch updates existing macros for the GPI:
- PAD_CFG_GPI_IOSSTATE_IOSTERM()
- PAD_CFG_GPI_IOSSTATE()
to allow the user to set the RX Level/Edge Configuration (trig) and
the Host Software Ownership (own) fileds in addition to IO Standby State
(iosstate) and IO Standby Termination (iosterm) in the pad configuration
using these macros.
Change-Id: I8a70a366e816d31720d341a5d26880dc32ff9b8d
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
1 file changed, 9 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/42911/1
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
index e9abd00..c2c8951 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
@@ -266,15 +266,16 @@
PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \
PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
-#define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
- PAD_PULL(pull) | PAD_IOSSTATE(iosstate))
+#define PAD_CFG_GPI_TRIG_IOSSTATE_OWN(pad, pull, rst, trig, iosstate, own) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | PAD_BUF(TX_DISABLE), \
+ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) | PAD_IOSSTATE(iosstate))
-#define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
- PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
+#define PAD_CFG_GPI_TRIG_IOS_OWN(pad, pull, rst, trig, iosstate, iosterm, own) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | PAD_BUF(TX_DISABLE), \
+ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) | \
+ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
/*
* General purpose input. The following macro sets the
--
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3
8
Change in coreboot[master]: soc/amd/picasso/sb: Gate FCH AH2ALB clocks
by Matt Papageorge (Code Review) 24 Jul '20
by Matt Papageorge (Code Review) 24 Jul '20
24 Jul '20
Matt Papageorge has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42829 )
Change subject: soc/amd/picasso/sb: Gate FCH AH2ALB clocks
......................................................................
soc/amd/picasso/sb: Gate FCH AH2ALB clocks
Gate the AH2ALB clocks to save power. This was previously
performed within the AGESA FSP but this change relocates it
into coreboot.
BUG=b:154144239
TEST=Check AH2ALB clock gate bits at the end of POST before and
after change with HDT.
Change-Id: Ifcbc144a8769f8ea440cdd560bab146bf5058cf9
Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com>
---
M src/soc/amd/picasso/include/soc/southbridge.h
M src/soc/amd/picasso/southbridge.c
2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/42829/1
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index e9f7e2e..191904f 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -205,6 +205,13 @@
#define FCH_AOAC_DEV_UART3 26
#define FCH_AOAC_DEV_ESPI 27
+/* FCH AH2ALB Registers */
+#define AH2ALB_BASE 0xFEDC0000ul
+#define AH2ALB_CONTROL_CLK_OFFSET 0x10
+#define AH2ALB_CLK_GATE_EN BIT(1)
+#define AH2ALB_CONTROL_HCLK_OFFSET 0x30
+#define AH2ALB_HCLK_GATE_EN BIT(1)
+
/* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */
#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
#define FCH_AOAC_D0_UNINITIALIZED 0
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 45f66d6..d222e9d 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -328,11 +328,24 @@
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL);
+static void ah2alb_clock_gate(void)
+{
+ uint8_t ah2alb_val;
+
+ ah2alb_val = read8((void *)(AH2ALB_BASE + AH2ALB_CONTROL_CLK_OFFSET));
+ ah2alb_val |= AH2ALB_CLK_GATE_EN;
+ write8((void *)(AH2ALB_BASE + AH2ALB_CONTROL_CLK_OFFSET), ah2alb_val);
+ ah2alb_val = read8((void *)(AH2ALB_BASE + AH2ALB_CONTROL_HCLK_OFFSET));
+ ah2alb_val |= AH2ALB_HCLK_GATE_EN;
+ write8((void *)(AH2ALB_BASE + AH2ALB_CONTROL_HCLK_OFFSET), ah2alb_val);
+}
+
void southbridge_init(void *chip_info)
{
i2c_soc_init();
sb_init_acpi_ports();
acpi_clear_pm1_status();
+ ah2alb_clock_gate();
}
static void set_sb_final_nvs(void)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifcbc144a8769f8ea440cdd560bab146bf5058cf9
Gerrit-Change-Number: 42829
Gerrit-PatchSet: 1
Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com>
Gerrit-MessageType: newchange
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29
Change in coreboot[4.11_branch]: src/mainboard/ocp/monolake: Create SMBIOS type 16 for Monolake platform
by Morgan Jang (Code Review) 24 Jul '20
by Morgan Jang (Code Review) 24 Jul '20
24 Jul '20
Morgan Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37233 )
Change subject: src/mainboard/ocp/monolake: Create SMBIOS type 16 for Monolake platform
......................................................................
src/mainboard/ocp/monolake: Create SMBIOS type 16 for Monolake platform
Create SMBIOS type 16 for Monolake platform, but the memory ECC setting can`t be
enabled by the FSP, so it`s hardcoded to MEMORY_ARRAY_ECC_SINGLE_BIT.
Change-Id: Ie057742112f14447b226d432417d9301d4aea958
Signed-off-by: Morgan Jang <Morgan_Jang(a)wiwynn.com>
---
M src/mainboard/ocp/monolake/mainboard.c
1 file changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/37233/1
diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c
index dffd19f..3a11b55 100644
--- a/src/mainboard/ocp/monolake/mainboard.c
+++ b/src/mainboard/ocp/monolake/mainboard.c
@@ -30,6 +30,8 @@
#define VPD_LEN 10
/* Default countdown is 15 minutes. */
#define DEFAULT_COUNTDOWN 9000
+#define MAX_IMC 1
+#define MAX_DIMM_SIZE_GB (32UL << 20)
static void init_frb2_wdt(void)
{
@@ -60,6 +62,41 @@
}
}
+#if CONFIG(GENERATE_SMBIOS_TABLES)
+static int write_smbios_type16(struct device *dev, int *handle, unsigned long *current)
+{
+ struct smbios_type16 *t = (struct smbios_type16 *)*current;
+ u32 maximum_capacity;
+ int len = sizeof(struct smbios_type16);
+
+ printk(BIOS_INFO, "Create SMBIOS type 16\n");
+
+ memset(t, 0, sizeof(struct smbios_type16));
+ t->type = SMBIOS_PHYS_MEMORY_ARRAY;
+ t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD;
+ t->use = MEMORY_ARRAY_USE_SYSTEM;
+ /* The ECC setting can`t be confirmed in FSP, so hardcode it. */
+ t->memory_error_correction = MEMORY_ARRAY_ECC_SINGLE_BIT;
+ t->memory_error_information_handle = 0xFFFE;
+ t->number_of_memory_devices = CONFIG_DIMM_MAX/MAX_IMC;
+
+ maximum_capacity = (u32)(CONFIG_DIMM_MAX * MAX_DIMM_SIZE_GB);
+ if (maximum_capacity >= 0x80000000) {
+ t->maximum_capacity = 0x80000000;
+ t->extended_maximum_capacity = maximum_capacity << 10;
+ } else {
+ t->maximum_capacity = (u32)maximum_capacity;
+ t->extended_maximum_capacity = 0;
+ }
+
+ *current += len;
+ t->handle = *handle;
+ *handle += 1;
+ t->length = len - 2;
+ return len;
+}
+#endif
+
/*
* mainboard_enable is executed as first thing after enumerate_buses().
* This is the earliest point to add customization.
@@ -76,6 +113,10 @@
clear_ipmi_flags(&rsp);
system_reset();
}
+
+#if CONFIG(GENERATE_SMBIOS_TABLES)
+ dev->ops->get_smbios_data = write_smbios_type16;
+#endif
}
struct chip_operations mainboard_ops = {
--
To view, visit https://review.coreboot.org/c/coreboot/+/37233
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Gerrit-Project: coreboot
Gerrit-Branch: 4.11_branch
Gerrit-Change-Id: Ie057742112f14447b226d432417d9301d4aea958
Gerrit-Change-Number: 37233
Gerrit-PatchSet: 1
Gerrit-Owner: Morgan Jang
Gerrit-MessageType: newchange
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