Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory initialization parameters
Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38507 )
Change subject: mb/intel/jasperlake_rvp: Add memory initialization parameters ......................................................................
mb/intel/jasperlake_rvp: Add memory initialization parameters
JasperLake RVP has 2 different memory support: DDR4 and LPDDR4x
Since there are no major difference except for memory configuration, we're not creating variants for this. We'll handle memory parameters based on board id. Board Id for DDR4 board is 1 and LPDDR4 board is 4.
BUG=NONE BRANCH=NONE TEST=Build jslrvp board and check compilation
Change-Id: Ia59b37900a7f3dba66f47c8f7333aa3503847fff Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c M src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc A src/mainboard/intel/jasperlake_rvp/spd/micron16Gb.spd.hex M src/mainboard/intel/jasperlake_rvp/spd/spd_util.c 4 files changed, 113 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/38507/1
diff --git a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c index 0ab1f48..f63f1b3 100644 --- a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,10 +13,71 @@ * GNU General Public License for more details. */
+#include <arch/byteorder.h> +#include <console/console.h> #include <fsp/api.h> #include <soc/romstage.h> +#include <spd_bin.h> +#include "board_id.h" +#include "spd/spd.h" + +#define BOARD_ID_JSL_DDR4 0x01
void mainboard_memory_init_params(FSPM_UPD *mupd) { - /* ToDo : Fill FSP-M memory params */ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + + u8 board_id = (get_board_id() & 0x1F) & 0x7; + printk(BIOS_DEBUG, "Board Id is 0x%x\n", board_id); + + struct region_device spd_rdev; + + if(board_id == BOARD_ID_JSL_DDR4) { + /* Set Board type for and SmBus Addresses for DDR4 */ + mem_cfg->UserBd = BOARD_TYPE_MOBILE; + + mem_cfg->SpdAddressTable[0] = 0xA0; + mem_cfg->SpdAddressTable[1] = 0xA2; + mem_cfg->SpdAddressTable[2] = 0xA4; + mem_cfg->SpdAddressTable[3] = 0xA6; + + } else { + + mem_cfg->UserBd = BOARD_TYPE_ULT_ULX; + + /* + * Currently only one SPD is required so keeping spd_index = 0 + * In future if we have more variants, we can change it to be based + * on board id. + */ + uint8_t spd_index = 0; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + + /* set smbus addresses to 0 for Lp4x board */ + + mem_cfg->SpdAddressTable[0] = 0x00; + mem_cfg->SpdAddressTable[1] = 0x00; + mem_cfg->SpdAddressTable[2] = 0x00; + mem_cfg->SpdAddressTable[3] = 0x00; + + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + } + + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->CaVrefConfig = 0x2; /* VREF_CA->CHA/CHB */ + mem_cfg->ECT = 1; /* Early Command Training Enabled */ + mem_cfg->RefClk = 0; /* Auto Select CLK freq */ + + mainboard_fill_dq_map_ch0(mem_cfg->DqByteMapCh0); + mainboard_fill_dq_map_ch1(mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_ch0(mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_ch1(mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(mem_cfg->RcompTarget); } diff --git a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc index b8b059a..afe855a 100644 --- a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Intel Corporation. +## Copyright (C) 2020 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,4 +17,4 @@
SPD_BIN = $(obj)/spd.bin
-SPD_SOURCES = empty # 0b000 +SPD_SOURCES = micron16Gb # 0b000 diff --git a/src/mainboard/intel/jasperlake_rvp/spd/micron16Gb.spd.hex b/src/mainboard/intel/jasperlake_rvp/spd/micron16Gb.spd.hex new file mode 100644 index 0000000..a27c249 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/spd/micron16Gb.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 B0 08 00 40 00 00 0A 22 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c b/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c index bdf8ede..afccaf1 100644 --- a/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,10 +21,8 @@ #include "spd.h"
enum jsl_dimm_type { - jsl_u_ddr4 = 0, - jsl_u_lpddr4 = 1, - jsl_u_lpddr4_type_3 = 4, - jsl_y_lpddr4 = 6 + jsl_u_ddr4 = 1, + jsl_u_lpddr4 = 4, };
void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr) @@ -37,7 +35,7 @@ memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); }
-static uint8_t get_spd_index(void) +static uint8_t get_board_type(void) { return get_board_id() & 0x7; } @@ -54,24 +52,15 @@ void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr) { /* DQS CPU<>DRAM map Ch0 */ - const u8 dqs_map_u_ddr[8] = { 2, 0, 1, 3, 6, 4, 7, 5 }; - const u8 dqs_map_u_lpddr[8] = { 2, 3, 0, 1, 7, 6, 4, 5 }; - const u8 dqs_map_u_lpddr_type_3[8] = { 2, 3, 1, 0, 7, 6, 4, 5 }; - const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; + const u8 dqs_map_u_ddr4[8] = { 0, 1, 3, 2, 4, 5, 6, 7 }; + const u8 dqs_map_u_lpddr4[8] = { 0, 3, 2, 1, 7, 5, 4, 6 };
- switch (get_spd_index()) { + switch (get_board_type()) { case jsl_u_ddr4: - memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); + memcpy(dqs_map_ptr, dqs_map_u_ddr4, sizeof(dqs_map_u_ddr4)); break; case jsl_u_lpddr4: - memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); - break; - case jsl_u_lpddr4_type_3: - memcpy(dqs_map_ptr, dqs_map_u_lpddr_type_3, - sizeof(dqs_map_u_lpddr_type_3)); - break; - case jsl_y_lpddr4: - memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); + memcpy(dqs_map_ptr, dqs_map_u_lpddr4, sizeof(dqs_map_u_lpddr4)); break; default: break; @@ -81,20 +70,15 @@ void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr) { /* DQS CPU<>DRAM map Ch1 */ - const u8 dqs_map_u_ddr[8] = { 1, 3, 2, 0, 5, 7, 6, 4 }; - const u8 dqs_map_u_lpddr[8] = { 1, 0, 3, 2, 5, 4, 7, 6 }; - const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 5, 4, 7, 6 }; + const u8 dqs_map_u_ddr4[8] = { 1, 0, 4, 5, 2, 3, 6, 7 }; + const u8 dqs_map_u_lpddr4[8] = { 3, 1, 2, 0, 4, 7, 6, 5 };
- switch (get_spd_index()) { + switch (get_board_type()) { case jsl_u_ddr4: - memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); + memcpy(dqs_map_ptr, dqs_map_u_ddr4, sizeof(dqs_map_u_ddr4)); break; case jsl_u_lpddr4: - case jsl_u_lpddr4_type_3: - memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); - break; - case jsl_y_lpddr4: - memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); + memcpy(dqs_map_ptr, dqs_map_u_lpddr4, sizeof(dqs_map_u_lpddr4)); break; default: break; @@ -112,18 +96,16 @@ { /* Rcomp target */ static const u16 RcompTarget_DDR4[RCOMP_TARGET_PARAMS] = { - 100, 33, 32, 33, 28 }; + 0, 0, 0, 0, 0 }; static const u16 RcompTarget_LPDDR4_Ax[RCOMP_TARGET_PARAMS] = { 80, 40, 40, 40, 30 };
- switch (get_spd_index()) { + switch (get_board_type()) { case jsl_u_ddr4: memcpy(rcomp_strength_ptr, RcompTarget_DDR4, sizeof(RcompTarget_DDR4)); break; - case jsl_y_lpddr4: case jsl_u_lpddr4: - case jsl_u_lpddr4_type_3: memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax, sizeof(RcompTarget_LPDDR4_Ax)); break;
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38507 )
Change subject: mb/intel/jasperlake_rvp: Add memory initialization parameters ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38507/1/src/mainboard/intel/jasperl... File src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/38507/1/src/mainboard/intel/jasperl... PS1, Line 35: if(board_id == BOARD_ID_JSL_DDR4) { space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/38507/1/src/mainboard/intel/jasperl... PS1, Line 73: mem_cfg->CaVrefConfig = 0x2; /* VREF_CA->CHA/CHB */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/38507/1/src/mainboard/intel/jasperl... PS1, Line 74: mem_cfg->ECT = 1; /* Early Command Training Enabled */ please, no space before tabs
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38507
to look at the new patch set (#2).
Change subject: mb/intel/jasperlake_rvp: Add memory initialization parameters ......................................................................
mb/intel/jasperlake_rvp: Add memory initialization parameters
JasperLake RVP has 2 different memory support: DDR4 and LPDDR4x
Since there are no major difference except for memory configuration, we're not creating variants for this. We'll handle memory parameters based on board id. Board Id for DDR4 board is 1 and LPDDR4 board is 4.
BUG=NONE BRANCH=NONE TEST=Build jslrvp board and check compilation
Change-Id: Ia59b37900a7f3dba66f47c8f7333aa3503847fff Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c M src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc A src/mainboard/intel/jasperlake_rvp/spd/micron16Gb.spd.hex M src/mainboard/intel/jasperlake_rvp/spd/spd_util.c 4 files changed, 113 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/38507/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38507 )
Change subject: mb/intel/jasperlake_rvp: Add memory initialization parameters ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38507/2/src/mainboard/intel/jasperl... File src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/38507/2/src/mainboard/intel/jasperl... PS2, Line 35: if(board_id == BOARD_ID_JSL_DDR4){ space required before the open brace '{'
https://review.coreboot.org/c/coreboot/+/38507/2/src/mainboard/intel/jasperl... PS2, Line 35: if(board_id == BOARD_ID_JSL_DDR4){ space required before the open parenthesis '('
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38507
to look at the new patch set (#3).
Change subject: mb/intel/jasperlake_rvp: Add memory initialization parameters ......................................................................
mb/intel/jasperlake_rvp: Add memory initialization parameters
JasperLake RVP has 2 different memory support: DDR4 and LPDDR4x
Since there are no major difference except for memory configuration, we're not creating variants for this. We'll handle memory parameters based on board id. Board Id for DDR4 board is 1 and LPDDR4 board is 4.
BUG=NONE BRANCH=NONE TEST=Build jslrvp board and check compilation
Change-Id: Ia59b37900a7f3dba66f47c8f7333aa3503847fff Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c M src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc A src/mainboard/intel/jasperlake_rvp/spd/micron16Gb.spd.hex M src/mainboard/intel/jasperlake_rvp/spd/spd_util.c 4 files changed, 113 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/38507/3
Maulik V Vaghela has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/38507 )
Change subject: mb/intel/jasperlake_rvp: Add memory initialization parameters ......................................................................
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