Change in coreboot[master]: mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4

[Brandon Breitenstein (Code Review)]

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41543 )

Change subject: mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4
......................................................................

mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4

This change enables PCIEXP_HOTPLUG to support resource allocation for
TCSS TBT/USB4.

BUG=b:149186922

Change-Id: Id3066204c8a780ade251c7be4052a60a861e43db
Signed-off-by: Brandon Breitenstein 
---
M src/mainboard/intel/tglrvp/Kconfig
1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41543/1

diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig
index d60918f..edbd486 100644
--- a/src/mainboard/intel/tglrvp/Kconfig
+++ b/src/mainboard/intel/tglrvp/Kconfig
@@ -15,6 +15,7 @@
    select SOC_INTEL_TIGERLAKE
    select INTEL_LPSS_UART_FOR_CONSOLE
    select DRIVERS_INTEL_ISH
+	select PCIEXP_HOTPLUG

config CHROMEOS
    bool
@@ -49,6 +50,18 @@
    int
    default 8

+config PCIEXP_HOTPLUG_BUSES
+	int
+	default 42
+
+config PCIEXP_HOTPLUG_MEM
+	hex
+	default 0xc200000 # 194 MiB
+
+config PCIEXP_HOTPLUG_PREFETCH_MEM
+	hex
+	default 0x1c00000 # 448 MiB
+
 config DEVICETREE
    string
    default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"

[John Zhao (Code Review)]

John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41543 )

Change subject: mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4
......................................................................

Patch Set 1: Code-Review+2

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41543 )

Change subject: mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41543/1/src/mainboard/intel/tglrvp/... 
File src/mainboard/intel/tglrvp/Kconfig:

https://review.coreboot.org/c/coreboot/+/41543/1/src/mainboard/intel/tglrvp/... 
PS1, Line 18: select PCIEXP_HOTPLUG
Does it also enable hotplug for other PCIe port?
FSPs upd has below UPD and we can enable/disable hotplug indivisually.
PcieRpHotPlug[24];
CpuPcieRpHotPlug[4];

[John Zhao (Code Review)]

John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41543 )

Change subject: mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41543/1/src/mainboard/intel/tglrvp/... 
File src/mainboard/intel/tglrvp/Kconfig:

https://review.coreboot.org/c/coreboot/+/41543/1/src/mainboard/intel/tglrvp/... 
PS1, Line 18: select PCIEXP_HOTPLUG
> Does it also enable hotplug for other PCIe port? […]

This PCIEXP_HOTPLUG selection only make sure resources are allocated for Thunderbolt PCIe root ports, not for others.

[Jamie Ryu (Code Review)]

Jamie Ryu has uploaded a new patch set (#2) to the change originally created by Brandon Breitenstein. ( https://review.coreboot.org/c/coreboot/+/41543 )

Change subject: mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4
......................................................................

mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4

This change enables PCIEXP_HOTPLUG to support resource allocation for
TCSS TBT/USB4.

BUG=b:149186922

Change-Id: Id3066204c8a780ade251c7be4052a60a861e43db
Signed-off-by: Brandon Breitenstein 
---
M src/mainboard/intel/tglrvp/Kconfig
1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41543/2

[Jamie Ryu (Code Review)]

Jamie Ryu has uploaded a new patch set (#3) to the change originally created by Brandon Breitenstein. ( https://review.coreboot.org/c/coreboot/+/41543 )

Change subject: mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4
......................................................................

mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4

This change enables PCIEXP_HOTPLUG to support resource allocation for
TCSS TBT/USB4.

BUG=b:149186922

Change-Id: Id3066204c8a780ade251c7be4052a60a861e43db
Signed-off-by: Brandon Breitenstein 
---
M src/mainboard/intel/tglrvp/Kconfig
1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41543/3

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41543 )

Change subject: mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4
......................................................................

Patch Set 3: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41543 )

Change subject: mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4
......................................................................

mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4

This change enables PCIEXP_HOTPLUG to support resource allocation for
TCSS TBT/USB4.

BUG=b:149186922

Change-Id: Id3066204c8a780ade251c7be4052a60a861e43db
Signed-off-by: Brandon Breitenstein 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41543
Tested-by: build bot (Jenkins) 
Reviewed-by: Wonkyu Kim 
---
M src/mainboard/intel/tglrvp/Kconfig
1 file changed, 13 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Wonkyu Kim: Looks good to me, approved

diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig
index 8277875..867c88e 100644
--- a/src/mainboard/intel/tglrvp/Kconfig
+++ b/src/mainboard/intel/tglrvp/Kconfig
@@ -17,6 +17,7 @@
    select INTEL_LPSS_UART_FOR_CONSOLE
    select DRIVERS_INTEL_ISH
    select EC_ACPI
+	select PCIEXP_HOTPLUG

config CHROMEOS
    bool
@@ -55,6 +56,18 @@
    int
    default 8

+config PCIEXP_HOTPLUG_BUSES
+	int
+	default 42
+
+config PCIEXP_HOTPLUG_MEM
+	hex
+	default 0xc200000 # 194 MiB
+
+config PCIEXP_HOTPLUG_PREFETCH_MEM
+	hex
+	default 0x1c00000 # 448 MiB
+
 config DEVICETREE
    string
    default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"