Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41543 )
Change subject: mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ......................................................................
mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4
This change enables PCIEXP_HOTPLUG to support resource allocation for TCSS TBT/USB4.
BUG=b:149186922
Change-Id: Id3066204c8a780ade251c7be4052a60a861e43db Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41543 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com --- M src/mainboard/intel/tglrvp/Kconfig 1 file changed, 13 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Wonkyu Kim: Looks good to me, approved
diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 8277875..867c88e 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -17,6 +17,7 @@ select INTEL_LPSS_UART_FOR_CONSOLE select DRIVERS_INTEL_ISH select EC_ACPI + select PCIEXP_HOTPLUG
config CHROMEOS bool @@ -55,6 +56,18 @@ int default 8
+config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c00000 # 448 MiB + config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"