Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42075 )
Change subject: mb/volteer: Update Aux settings for USB3 Daughterboard ......................................................................
mb/volteer: Update Aux settings for USB3 Daughterboard
On certain volteer board configs the daughter card can have no retimer there will need to be a way to verify if this is the case and then correctly config the aux orientation settings
This is a WIP and will need some changes but pushing the initial changes for testing and USB3 verification on certain Volteer configs
Change-Id: Id0db1b684cfb8b9df6ac8007aee243d3315270bb Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/gpio.c 2 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/42075/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index a55ef7d..0dbcea5 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -147,11 +147,11 @@
# TCSS USB3 register "TcssXhciEn" = "1" - register "TcssAuxOri" = "1" + register "TcssAuxOri" = "5" register "IomTypeCPortPadCfg[0]" = "0x090E000A" register "IomTypeCPortPadCfg[1]" = "0x090E000D" - register "IomTypeCPortPadCfg[2]" = "0x0" - register "IomTypeCPortPadCfg[3]" = "0x0" + register "IomTypeCPortPadCfg[2]" = "0x090E0016" + register "IomTypeCPortPadCfg[3]" = "0x090E0017" register "IomTypeCPortPadCfg[4]" = "0x0" register "IomTypeCPortPadCfg[5]" = "0x0" register "IomTypeCPortPadCfg[6]" = "0x0" diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 3290f44..588ea91 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -239,9 +239,9 @@ /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */ - PAD_NC(GPP_E22, NONE), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */ - PAD_NC(GPP_E23, NONE), + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
/* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42075 )
Change subject: mb/volteer: Update Aux settings for USB3 Daughterboard ......................................................................
Patch Set 1:
This change is ready for review.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42075 )
Change subject: mb/volteer: Update Aux settings for USB3 Daughterboard ......................................................................
Patch Set 1:
(2 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/42075/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42075/1//COMMIT_MSG@7 PS1, Line 7: mb/volteer mb/google/volteer
https://review.coreboot.org/c/coreboot/+/42075/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42075/1/src/mainboard/google/voltee... PS1, Line 150: 5 This can't be set here as it does not apply to all volteers (it would enable TCSS muxing on ports that didn't need it for all the SKUs that have retimers).
I think you will need to do it in a similar fashion to this : https://review.coreboot.org/c/coreboot/+/42255/10/src/mainboard/google/volte...
I realize this CL is WIP, I'm just trying to help 😊
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Brandon Breitenstein (Code Review) -
Nick Vaccaro (Code Review)