Wuxy - has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM part number for oak. ......................................................................
mb/google/oak: Add new DRAM part number for oak.
This change adds the following memory parts to oak:
1.K4E8E304ED-2GB 2.K4E6E304ED-4GB
BUG=b:157702981a BRANCH=none TEST=none
Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E304ED-2GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/1
diff --git a/src/mainboard/google/oak/sdram_configs.c b/src/mainboard/google/oak/sdram_configs.c index 60b212a..2b9fc14 100644 --- a/src/mainboard/google/oak/sdram_configs.c +++ b/src/mainboard/google/oak/sdram_configs.c @@ -14,8 +14,8 @@ #include "sdram_inf/sdram-lpddr3-MT52L512M32D2PF-4GB.inc" /* ram_code = 0110 */ #include "sdram_inf/sdram-lpddr3-H9CCNNNBJTALAR-4GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-MT52L256M32D1PF-2GB.inc" /* ram_code = 1000 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-lpddr3-K4E8E304ED-2GB.inc" /* ram_code = 1001 */ +#include "sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc new file mode 100644 index 0000000..e6c3a83 --- /dev/null +++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc @@ -0,0 +1,116 @@ +{ /* 4GB (16Gb + 16Gb) for dual rank dram setting */ + { + .impedance_drvp = 0x9, + .impedance_drvn = 0xa, + .datlat_ucfirst = 18, + + .ca_train = { + [CHANNEL_A] = { 6, 4, 3, 5, 4, 0, 0, 0, 0, 0}, + [CHANNEL_B] = { 1, 1, 1, 1, 0, 6, 5, 5, 5, 7} + }, + + .ca_train_center = { + [CHANNEL_A] = 3, + [CHANNEL_B] = 3 + }, + + .wr_level = { + [CHANNEL_A] = { 8, 10, 6, 8}, + [CHANNEL_B] = { 9, 9, 7, 6} + }, + + .gating_win = { + [CHANNEL_A] = { + { 27, 64}, + { 27, 72} + }, + [CHANNEL_B] = { + { 27, 72}, + { 27, 72} + } + }, + + .rx_dqs_dly = { + [CHANNEL_A] = 0x08080908, + [CHANNEL_B] = 0x0b0b060b + }, + + .rx_dq_dly = { + [CHANNEL_A] = { + 0x01010300, + 0x06030002, + 0x01010201, + 0x03020002, + 0x00010103, + 0x02010201, + 0x02040200, + 0x02020201 + }, + [CHANNEL_B] = { + 0x00020202, + 0x02020202, + 0x01020201, + 0x01010100, + 0x01010101, + 0x01000002, + 0x02000201, + 0x00010101, + } + }, + }, + { + .actim = 0xaafd478c, + .actim1 = 0x91001f59, + .actim05t = 0x000025e1, + .conf1 = 0x00048403, + .conf2 = 0x030000a9, + .ddr2ctl = 0x000063b1, + .gddr3ctl1 = 0x11000000, + .misctl0 = 0x21000000, + .pd_ctrl = 0xd1976442, + .rkcfg = 0x002156c1, + .test2_3 = 0xbfc70401, + .test2_4 = 0x2801110d + }, + { + .cona = 0x50a350a7, + .conb = 0x17283544, + .conc = 0x0a1a0b1a, + .cond = 0x00000000, + .cone = 0xffff0848, + .conf = 0x08420000, + .cong = 0x2b2b2a38, + .conh = 0x00000000, + .conm_1 = 0x40000500, + .conm_2 = 0x400005ff, + .mdct_1 = 0x80030303, + .mdct_2 = 0x34220c3f, + .test0 = 0xcccccccc, + .test1 = 0xcccccccc, + .testb = 0x00060124, + .testc = 0x38470000, + .testd = 0x00000000, + .arba = 0x7f077a49, + .arbc = 0xa0a070dd, + .arbd = 0x07007046, + .arbe = 0x40407046, + .arbf = 0xa0a070c6, + .arbg = 0xffff7047, + .arbi = 0x20406188, + .arbj = 0x9719595e, + .arbk = 0x64f3fc79, + .slct_1 = 0x00010800, + .slct_2 = 0xff03ff00, + .bmen = 0x00ff0001 + }, + { + .mrs_1 = 0x00830001, + .mrs_2 = 0x001c0002, + .mrs_3 = 0x00010003, + .mrs_10 = 0x00ff000a, + .mrs_11 = 0x0000000b, + .mrs_63 = 0x0000003f + }, + .type = TYPE_LPDDR3, + .dram_freq = 896 * MHz, +}, diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E304ED-2GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E304ED-2GB.inc new file mode 100644 index 0000000..4c58286 --- /dev/null +++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E304ED-2GB.inc @@ -0,0 +1,116 @@ +{ /* 2GB (8Gb + 8Gb) for dual rank dram setting */ + { + .impedance_drvp = 0x9, + .impedance_drvn = 0xa, + .datlat_ucfirst = 18, + + .ca_train = { + [CHANNEL_A] = { 6, 4, 3, 5, 4, 0, 0, 0, 0, 0}, + [CHANNEL_B] = { 1, 1, 1, 1, 0, 6, 5, 5, 5, 7} + }, + + .ca_train_center = { + [CHANNEL_A] = 3, + [CHANNEL_B] = 3 + }, + + .wr_level = { + [CHANNEL_A] = { 8, 10, 6, 8}, + [CHANNEL_B] = { 9, 9, 7, 6} + }, + + .gating_win = { + [CHANNEL_A] = { + { 27, 64}, + { 27, 72} + }, + [CHANNEL_B] = { + { 27, 72}, + { 27, 72} + } + }, + + .rx_dqs_dly = { + [CHANNEL_A] = 0x08080908, + [CHANNEL_B] = 0x0b0b060b + }, + + .rx_dq_dly = { + [CHANNEL_A] = { + 0x01010300, + 0x06030002, + 0x01010201, + 0x03020002, + 0x00010103, + 0x02010201, + 0x02040200, + 0x02020201 + }, + [CHANNEL_B] = { + 0x00020202, + 0x02020202, + 0x01020201, + 0x01010100, + 0x01010101, + 0x01000002, + 0x02000201, + 0x00010101, + } + }, + }, + { + .actim = 0xaafd478c, + .actim1 = 0x91001f59, + .actim05t = 0x000025e1, + .conf1 = 0x00048403, + .conf2 = 0x030000a9, + .ddr2ctl = 0x000063b1, + .gddr3ctl1 = 0x11000000, + .misctl0 = 0x21000000, + .pd_ctrl = 0xd1976442, + .rkcfg = 0x002156c1, + .test2_3 = 0xbfc70401, + .test2_4 = 0x2801110d + }, + { + .cona = 0x50535057, + .conb = 0x17283544, + .conc = 0x0a1a0b1a, + .cond = 0x00000000, + .cone = 0xffff0848, + .conf = 0x08420000, + .cong = 0x2b2b2a38, + .conh = 0x00000000, + .conm_1 = 0x40000500, + .conm_2 = 0x400005ff, + .mdct_1 = 0x80030303, + .mdct_2 = 0x34220c3f, + .test0 = 0xcccccccc, + .test1 = 0xcccccccc, + .testb = 0x00060124, + .testc = 0x38470000, + .testd = 0x00000000, + .arba = 0x7f077a49, + .arbc = 0xa0a070dd, + .arbd = 0x07007046, + .arbe = 0x40407046, + .arbf = 0xa0a070c6, + .arbg = 0xffff7047, + .arbi = 0x20406188, + .arbj = 0x9719595e, + .arbk = 0x64f3fc79, + .slct_1 = 0x00010800, + .slct_2 = 0xff03ff00, + .bmen = 0x00ff0001 + }, + { + .mrs_1 = 0x00830001, + .mrs_2 = 0x001c0002, + .mrs_3 = 0x00010003, + .mrs_10 = 0x00ff000a, + .mrs_11 = 0x0000000b, + .mrs_63 = 0x0000003f + }, + .type = TYPE_LPDDR3, + .dram_freq = 896 * MHz, +},
Hello Patrick Georgi, Martin Roth, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#2).
Change subject: mb/google/oak: Add new DRAM part number for oak. ......................................................................
mb/google/oak: Add new DRAM part number for oak.
This change adds the following memory parts to oak:
1.K4E8E304ED-2GB 2.K4E6E304ED-4GB
BUG=b:157702981 BRANCH=none TEST=none
Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E304ED-2GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#3).
Change subject: mb/google/oak: Add new DRAM part number for oak. ......................................................................
mb/google/oak: Add new DRAM part number for oak.
This change adds the following memory parts to oak:
1.K4E8E304ED-2GB 2.K4E6E304ED-4GB
BUG=b:157702981 BRANCH=none TEST=none
Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E304ED-2GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/3
Wuxy - has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM part number for oak ......................................................................
Patch Set 6:
This change is ready for review.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#7).
Change subject: mb/google/oak: Add new DRAM part number for oak ......................................................................
mb/google/oak: Add new DRAM part number for oak
This change adds the following memory parts to oak:
1.K4E8E304ED-2GB 2.NT6CL512T32AM-2GB
BUG=b:157702981 BRANCH=none TEST=none
Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E304ED-2GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-2GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/7
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM part number for oak ......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42184/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42184/7//COMMIT_MSG@7 PS7, Line 7: part number modules
https://review.coreboot.org/c/coreboot/+/42184/7//COMMIT_MSG@15 PS7, Line 15: none oak
https://review.coreboot.org/c/coreboot/+/42184/7//COMMIT_MSG@16 PS7, Line 16: none please at least build and boot this on an oak device.
Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#8).
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
mb/google/oak: Add new DRAM modules for oak
This change adds the following memory parts to oak:
1.K4E8E304ED-2GB 2.NT6CL512T32AM-2GB
BUG=b:157702981 BRANCH=oak TEST=none
Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E304ED-2GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-2GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/8
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 8: Code-Review+2
Wuxy - has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42184/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42184/7//COMMIT_MSG@16 PS7, Line 16: none
please at least build and boot this on an oak device.
Actually,we are re-working a new device for testing this CL now,at the same time, hope that Google can assign the ram id or we can use the current one.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 8:
I think it is fine to use current IDs.
Wuxy - has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 8:
Patch Set 8:
I think it is fine to use current IDs.
Thank you,we are re-working new boards with these sources today,I will give a feedback here if devices can boot to system,actually,we still change the 'mosys' code to match these new sources,and that is not coreboot side,so let's focus on this first.
Tony Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 8: Code-Review-1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42184/8/src/mainboard/google/oak/sd... File src/mainboard/google/oak/sdram_configs.c:
https://review.coreboot.org/c/coreboot/+/42184/8/src/mainboard/google/oak/sd... PS8, Line 17: K4E8E304ED Please double check it should be K4E6E304ED or K4E8E304ED? The part number request from issue tracker is different than it's listed here. https://issuetracker.google.com/157702981
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 8: -Code-Review
Wuxy - has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 8:
(1 comment)
I have double checked issue b:157702981 #7, sdram-lpddr3-K4E8E304ED-2GB.inc = 2G, sdram-lpddr3-K4E6E304ED-4GB.inc = 4G, It looks like he changed to 2 different names,like this: #include "sdram_inf/sdram-lpddr3-K4E8E304EE-2GB.inc" /* ram_code = 0001 */ #include "sdram_inf/sdram-lpddr3-K4E6E304EE-4GB.inc" /* ram_code = 0010 */ So there is no problem with this patch, he set different names for different capacity
https://review.coreboot.org/c/coreboot/+/42184/8/src/mainboard/google/oak/sd... File src/mainboard/google/oak/sdram_configs.c:
https://review.coreboot.org/c/coreboot/+/42184/8/src/mainboard/google/oak/sd... PS8, Line 17: K4E8E304ED
Please double check it should be K4E6E304ED or K4E8E304ED? […]
Thanks for reminding,actually,I have seen this error, I will fix it,in addition, if we will use a combination(2GB+2GB) on a board,should I submit 2GB or 4GB for spd?
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 8: Code-Review+1
(1 comment)
Looks good to me from the code side, can't comment on the actual training values or part numbers.
https://review.coreboot.org/c/coreboot/+/42184/8/src/mainboard/google/oak/sd... File src/mainboard/google/oak/sdram_configs.c:
https://review.coreboot.org/c/coreboot/+/42184/8/src/mainboard/google/oak/sd... PS8, Line 17: K4E8E304ED
Thanks for reminding,actually,I have seen this error, I will fix it,in addition, if we will use a co […]
If you're talking about the file name, the 2GB here are referring to the total for the whole board (so 2GB+2GB would be a file ending in -4GB.inc).
Hello Hung-Te Lin, build bot (Jenkins), Tony Lin, Patrick Georgi, Martin Roth, Julius Werner, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#9).
Change subject: mb/google/oak: Add new DRAM part number for oak ......................................................................
mb/google/oak: Add new DRAM part number for oak
This change adds the following memory parts to oak, and the combination is 2G+2G,so add the 4GB.inc files.
1.K4E6E304ED-4GB 2.NT6CL512T32AM-H0-4GB
BUG=b:157702981a BRANCH=oak TEST=none
Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/9
Hello Hung-Te Lin, build bot (Jenkins), Tony Lin, Patrick Georgi, Martin Roth, Julius Werner, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#10).
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
mb/google/oak: Add new DRAM modules for oak
This change adds the following memory parts to oak, and the combination is 2G+2G,so add the 4GB.inc files.
1.K4E6E304ED-4GB 2.NT6CL512T32AM-H0-4GB
BUG=b:157702981a BRANCH=oak TEST=none
Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/10
Hello Hung-Te Lin, build bot (Jenkins), Tony Lin, Patrick Georgi, Martin Roth, Julius Werner, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#11).
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
mb/google/oak: Add new DRAM modules for oak
This change adds the following memory parts to oak, and the combination is 2G+2G,so add the 4GB.inc files.
1.K4E6E304ED-4GB 2.NT6CL512T32AM-H0-4GB
BUG=b:157702981a BRANCH=oak TEST=none
Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/11
Hello Hung-Te Lin, build bot (Jenkins), Tony Lin, Patrick Georgi, Martin Roth, Julius Werner, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#12).
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
mb/google/oak: Add new DRAM modules for oak
This change adds the following memory parts to oak. The combination is 2G+2G,so add the 4GB.inc files.
1.K4E6E304ED-4GB 2.NT6CL512T32AM-H0-4GB
BUG=b:157702981 BRANCH=oak TEST=none
Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/12
Hello Hung-Te Lin, build bot (Jenkins), Tony Lin, Patrick Georgi, Martin Roth, Julius Werner, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#13).
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
mb/google/oak: Add new DRAM modules for oak
This change adds the following memory parts to oak.
1.K4E6E304ED-4GB 2.NT6CL512T32AM-H0-4GB
BUG=b:157702981 BRANCH=oak TEST=none
Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/13
Hello Hung-Te Lin, build bot (Jenkins), Tony Lin, Patrick Georgi, Martin Roth, Julius Werner, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#14).
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
mb/google/oak: Add new DRAM modules for oak
This change adds the following memory parts to oak.
1.K4E6E304ED-4GB 2.NT6CL512T32AM-H0-4GB
BUG=b:157702981 BRANCH=oak TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge
Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/14
Hello Hung-Te Lin, build bot (Jenkins), Tony Lin, Patrick Georgi, Martin Roth, Julius Werner, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#15).
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
mb/google/oak: Add new DRAM modules for oak
This change adds the following memory parts to oak. This combination is 2G+2G,so add the xxx.4GB.inc
1.K4E6E304ED-4GB 2.NT6CL512T32AM-H0-4GB
BUG=b:157702981 BRANCH=oak TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge
Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/15
Hello Hung-Te Lin, build bot (Jenkins), Tony Lin, Patrick Georgi, Martin Roth, Julius Werner, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#16).
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
mb/google/oak: Add new DRAM modules for oak
This change adds the following memory parts to oak this combination is 2G+2G,so add the xxx.4GB.inc
1.K4E6E304ED-4GB 2.NT6CL512T32AM-H0-4GB
BUG=b:157702981 BRANCH=oak TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge
Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/16
Hello Hung-Te Lin, build bot (Jenkins), Tony Lin, Patrick Georgi, Martin Roth, Julius Werner, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#17).
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
mb/google/oak: Add new DRAM modules for oak
This change adds the following memory parts to oak: K4E6E304ED-4GB #1001 NT6CL512T32AM-H0-4GB #1010
BUG=b:157702981 BRANCH=oak TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge
Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/17
Hello Hung-Te Lin, build bot (Jenkins), Tony Lin, Patrick Georgi, Martin Roth, Julius Werner, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#18).
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
mb/google/oak: Add new DRAM modules for oak
Add DRAM support for oak: Samsung K4E6E304ED-4GB # 1001 Nanya NT6CL512T32AM-H0-4GB # 1010
BUG=b:157702981 BRANCH=oak TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge
Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/18
Wuxy - has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 18:
I have verified that units with Nanya's dram can boot into system,I will verify +1 once the Samsung's dram can work too.
Hello Hung-Te Lin, build bot (Jenkins), Tony Lin, Patrick Georgi, Martin Roth, Julius Werner, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#19).
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
mb/google/oak: Add new DRAM modules for oak
Add DRAM support for oak: Samsung K4E6E304ED-4GB # 1001 Nanya NT6CL512T32AM-H0-4GB # 1010
BUG=b:157702981 BRANCH=oak TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge
Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/19
Wuxy - has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 19:
Update the fine tune setting for Nanya.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 19:
Please let us know when you've finished all validation.
Or maybe you can split this into two CLs.
Wuxy - has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 19:
Patch Set 19:
Please let us know when you've finished all validation.
Or maybe you can split this into two CLs.
Thanks Hung-Te,customer want to merge two sources together,but Samsung's dram still has issue,we are working with Samsung/MTK now,so let's wait for related test result.
Hello Hung-Te Lin, build bot (Jenkins), Tony Lin, Patrick Georgi, Martin Roth, Julius Werner, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#20).
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
mb/google/oak: Add new DRAM modules for oak
Add DRAM support for oak: Samsung K4E6E304ED-4GB # 1001 Nanya NT6CL512T32AM-H0-4GB # 1010
BUG=b:157702981 BRANCH=oak TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge
Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/20
Wuxy - has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 20:
Hi all, Please help review this patch again,I used this changes to run 'memteseter' test with 2 devices(Samsung and Nanya),none of them encountered any reboot or FAILURE issue.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 20: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 20: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/42184/20//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42184/20//COMMIT_MSG@15 PS20, Line 15: TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge What tests did you run?
https://review.coreboot.org/c/coreboot/+/42184/20/src/mainboard/google/oak/s... File src/mainboard/google/oak/sdram_configs.c:
https://review.coreboot.org/c/coreboot/+/42184/20/src/mainboard/google/oak/s... PS20, Line 18: Only use one space.
Hello Hung-Te Lin, build bot (Jenkins), Tony Lin, Patrick Georgi, Martin Roth, Paul Menzel, Julius Werner, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42184
to look at the new patch set (#21).
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
mb/google/oak: Add new DRAM modules for oak
Add DRAM support for oak: Samsung K4E6E304ED-4GB # 1001 Nanya NT6CL512T32AM-H0-4GB # 1010
BUG=b:157702981 BRANCH=oak TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge, update FW to DUTs,these DUTs can pass 'memtester' test over 48 hours.
Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/21
Wuxy - has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 21:
(2 comments)
Hi Hung-Te and Paul, Could you help review this patch and merge? Thanks.
https://review.coreboot.org/c/coreboot/+/42184/20//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42184/20//COMMIT_MSG@15 PS20, Line 15: TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge
What tests did you run?
Add 'memtester' for detail test.
https://review.coreboot.org/c/coreboot/+/42184/20/src/mainboard/google/oak/s... File src/mainboard/google/oak/sdram_configs.c:
https://review.coreboot.org/c/coreboot/+/42184/20/src/mainboard/google/oak/s... PS20, Line 18:
Only use one space.
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 21: Code-Review+2
(5 comments)
Please remember to solve/ack all comments in future.
https://review.coreboot.org/c/coreboot/+/42184/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42184/3//COMMIT_MSG@7 PS3, Line 7: mb/google/oak: Add new DRAM part number for oak.
Pleas remove the dot/period at the end.
Ack
https://review.coreboot.org/c/coreboot/+/42184/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42184/7//COMMIT_MSG@7 PS7, Line 7: part number
modules
Ack
https://review.coreboot.org/c/coreboot/+/42184/7//COMMIT_MSG@15 PS7, Line 15: none
oak
Ack
https://review.coreboot.org/c/coreboot/+/42184/7//COMMIT_MSG@16 PS7, Line 16: none
Actually,we are re-working a new device for testing this CL now,at the same time, hope that Google c […]
Ack
https://review.coreboot.org/c/coreboot/+/42184/8/src/mainboard/google/oak/sd... File src/mainboard/google/oak/sdram_configs.c:
https://review.coreboot.org/c/coreboot/+/42184/8/src/mainboard/google/oak/sd... PS8, Line 17: K4E8E304ED
If you're talking about the file name, the 2GB here are referring to the total for the whole board ( […]
Ack
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 21:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42184/20//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42184/20//COMMIT_MSG@15 PS20, Line 15: TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge
Add 'memtester' for detail test.
Ack
Wuxy - has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 21:
Patch Set 21: Code-Review+2
(5 comments)
Please remember to solve/ack all comments in future.
Got it,thanks for your help,I will do it in future,so can we merge this patch?
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 21:
Got it,thanks for your help,I will do it in future,so can we merge this patch?
Need commiters to merge - @jwerner and @pgeorgi?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 21: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42184/21//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42184/21//COMMIT_MSG@16 PS21, Line 16: update FW to DUTs,these DUTs can pass 'memtester' test over 48 hours. Nit: Please add a space after the comma.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
Patch Set 21:
(1 comment)
Need commiters to merge - @jwerner and @pgeorgi?
Just tell Stefan to put you on the committers list already, you've been working on this project for close to a decade. ^^
https://review.coreboot.org/c/coreboot/+/42184/21//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42184/21//COMMIT_MSG@16 PS21, Line 16: update FW to DUTs,these DUTs can pass 'memtester' test over 48 hours.
Nit: Please add a space after the comma.
Since you said "nit" I assume you're okay with this being merged without it, and since people explicitly asked to get it in...
Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42184 )
Change subject: mb/google/oak: Add new DRAM modules for oak ......................................................................
mb/google/oak: Add new DRAM modules for oak
Add DRAM support for oak: Samsung K4E6E304ED-4GB # 1001 Nanya NT6CL512T32AM-H0-4GB # 1010
BUG=b:157702981 BRANCH=oak TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge, update FW to DUTs,these DUTs can pass 'memtester' test over 48 hours.
Signed-off-by: Xingyu Wu wuxy@bitland.corp-partner.google.com Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42184 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Hung-Te Lin hungte@chromium.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc 3 files changed, 234 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Hung-Te Lin: Looks good to me, approved
diff --git a/src/mainboard/google/oak/sdram_configs.c b/src/mainboard/google/oak/sdram_configs.c index 60b212a..34a8014 100644 --- a/src/mainboard/google/oak/sdram_configs.c +++ b/src/mainboard/google/oak/sdram_configs.c @@ -14,8 +14,8 @@ #include "sdram_inf/sdram-lpddr3-MT52L512M32D2PF-4GB.inc" /* ram_code = 0110 */ #include "sdram_inf/sdram-lpddr3-H9CCNNNBJTALAR-4GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-MT52L256M32D1PF-2GB.inc" /* ram_code = 1000 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc" /* ram_code = 1001 */ +#include "sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc new file mode 100644 index 0000000..fb2ec4a --- /dev/null +++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc @@ -0,0 +1,116 @@ +{ /* 4GB (16Gb + 16Gb) for dual rank dram setting */ + { + .impedance_drvp = 0x9, + .impedance_drvn = 0xa, + .datlat_ucfirst = 18, + + .ca_train = { + [CHANNEL_A] = { 6, 5, 5, 7, 7, 1, 0, 2, 1, 1}, + [CHANNEL_B] = { 0, 1, 2, 1, 2, 6, 6, 4, 6, 7} + }, + + .ca_train_center = { + [CHANNEL_A] = 2, + [CHANNEL_B] = 2 + }, + + .wr_level = { + [CHANNEL_A] = { 8, 8, 6, 8}, + [CHANNEL_B] = { 8, 6, 7, 6} + }, + + .gating_win = { + [CHANNEL_A] = { + { 28, 64}, + { 28, 64} + }, + [CHANNEL_B] = { + { 28, 56}, + { 28, 64} + } + }, + + .rx_dqs_dly = { + [CHANNEL_A] = 0x08080908, + [CHANNEL_B] = 0x0b0b060b + }, + + .rx_dq_dly = { + [CHANNEL_A] = { + 0x01010300, + 0x06030002, + 0x01010201, + 0x03020002, + 0x00010103, + 0x02010201, + 0x02040200, + 0x02020201 + }, + [CHANNEL_B] = { + 0x00020202, + 0x02020202, + 0x01020201, + 0x01010100, + 0x01010101, + 0x01000002, + 0x02000201, + 0x00010101, + } + }, + }, + { + .actim = 0xaafd478c, + .actim1 = 0x91001f59, + .actim05t = 0x000025e1, + .conf1 = 0x00048403, + .conf2 = 0x030000a9, + .ddr2ctl = 0x000063b1, + .gddr3ctl1 = 0x11000000, + .misctl0 = 0x21000000, + .pd_ctrl = 0xd1976442, + .rkcfg = 0x002156c1, + .test2_3 = 0xbfc70401, + .test2_4 = 0x2801110d + }, + { + .cona = 0xa053a057, + .conb = 0x17283544, + .conc = 0x0a1a0b1a, + .cond = 0x00000000, + .cone = 0xffff0848, + .conf = 0x08420000, + .cong = 0x2b2b2a38, + .conh = 0x00000000, + .conm_1 = 0x40000500, + .conm_2 = 0x400005ff, + .mdct_1 = 0x80030303, + .mdct_2 = 0x34220c3f, + .test0 = 0xcccccccc, + .test1 = 0xcccccccc, + .testb = 0x00060124, + .testc = 0x38470000, + .testd = 0x00000000, + .arba = 0x7f077a49, + .arbc = 0xa0a070dd, + .arbd = 0x07007046, + .arbe = 0x40407046, + .arbf = 0xa0a070c6, + .arbg = 0xffff7047, + .arbi = 0x20406188, + .arbj = 0x9719595e, + .arbk = 0x64f3fc79, + .slct_1 = 0x00010800, + .slct_2 = 0xff03ff00, + .bmen = 0x00ff0001 + }, + { + .mrs_1 = 0x00830001, + .mrs_2 = 0x001c0002, + .mrs_3 = 0x00010003, + .mrs_10 = 0x00ff000a, + .mrs_11 = 0x0000000b, + .mrs_63 = 0x0000003f + }, + .type = TYPE_LPDDR3, + .dram_freq = 896 * MHz, +}, diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc new file mode 100644 index 0000000..eb05d47 --- /dev/null +++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc @@ -0,0 +1,116 @@ +{ /* 2GB (8Gb + 8Gb) for single rank dram setting */ + { + .impedance_drvp = 0x9, + .impedance_drvn = 0xb, + .datlat_ucfirst = 18, + + .ca_train = { + [CHANNEL_A] = { 3, 3, 2, 3, 3, 1, 0, 1, 1, 0}, + [CHANNEL_B] = { 0, 0, 2, 0, 1, 3, 3, 2, 3, 4} + }, + + .ca_train_center = { + [CHANNEL_A] = 0, + [CHANNEL_B] = 0 + }, + + .wr_level = { + [CHANNEL_A] = { 2, 2, 3, 3}, + [CHANNEL_B] = { 3, 2, 3, 2} + }, + + .gating_win = { + [CHANNEL_A] = { + { 28, 64}, + { 28, 64} + }, + [CHANNEL_B] = { + { 28, 64}, + { 28, 64} + } + }, + + .rx_dqs_dly = { + [CHANNEL_A] = 0x110e0b0b, + [CHANNEL_B] = 0x0D100d0d + }, + + .rx_dq_dly = { + [CHANNEL_A] = { + 0x01040302, + 0x04010300, + 0x02040300, + 0x04030302, + 0x04070400, + 0x07070707, + 0x05070808, + 0x00010404 + }, + [CHANNEL_B] = { + 0x05060604, + 0x04010400, + 0x05070300, + 0x05030504, + 0x07090500, + 0x08090707, + 0x080a0a0a, + 0x02000604 + } + }, + }, + { + .actim = 0xaafd478c, + .actim1 = 0x91001f59, + .actim05t = 0x000025e1, + .conf1 = 0x00048403, + .conf2 = 0x030000a9, + .ddr2ctl = 0x000063b1, + .gddr3ctl1 = 0x11000000, + .misctl0 = 0x21000000, + .pd_ctrl = 0xd1976442, + .rkcfg = 0x002156c1, + .test2_3 = 0xbfc70401, + .test2_4 = 0x2801110d + }, + { + .cona = 0xa053a057, + .conb = 0x17283544, + .conc = 0x0a1a0b1a, + .cond = 0x00000000, + .cone = 0xffff0848, + .conf = 0x08420000, + .cong = 0x2b2b2a38, + .conh = 0x00000000, + .conm_1 = 0x40000500, + .conm_2 = 0x400005ff, + .mdct_1 = 0x80030303, + .mdct_2 = 0x34220c3f, + .test0 = 0xcccccccc, + .test1 = 0xcccccccc, + .testb = 0x00060124, + .testc = 0x38470000, + .testd = 0x00000000, + .arba = 0x7f077a49, + .arbc = 0xa0a070dd, + .arbd = 0x07007046, + .arbe = 0x40407046, + .arbf = 0xa0a070c6, + .arbg = 0xffff7047, + .arbi = 0x20406188, + .arbj = 0x9719595e, + .arbk = 0x64f3fc79, + .slct_1 = 0x00010800, + .slct_2 = 0xff03ff00, + .bmen = 0x00ff0001 + }, + { + .mrs_1 = 0x00830001, + .mrs_2 = 0x001c0002, + .mrs_3 = 0x00010003, + .mrs_10 = 0x00ff000a, + .mrs_11 = 0x0000000b, + .mrs_63 = 0x0000003f + }, + .type = TYPE_LPDDR3, + .dram_freq = 896 * MHz, +},
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Hung-Te Lin (Code Review) -
Julius Werner (Code Review)
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Paul Menzel (Code Review)
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Tony Lin (Code Review)
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Wuxy - (Code Review)