coreboot-gerrit June 2020

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Change in coreboot[master]: acpi: Add support for call method
by Paul Menzel (Code Review) 09 Jun '20

09 Jun '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41620 ) Change subject: acpi: Add support for call method ...................................................................... Patch Set 11: (3 comments) https://review.coreboot.org/c/coreboot/+/41620/11//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41620/11//COMMIT_MSG@7 PS11, Line 7: acpi: Add support for call method The STA method is not mentioned. https://review.coreboot.org/c/coreboot/+/41620/11//COMMIT_MSG@10 PS11, Line 10: STA function which returns an external variable. Could be two commits? https://review.coreboot.org/c/coreboot/+/41620/11/src/acpi/acpigen.c File src/acpi/acpigen.c: https://review.coreboot.org/c/coreboot/+/41620/11/src/acpi/acpigen.c@1970 PS11, Line 1970: int unsigned int -- To view, visit https://review.coreboot.org/c/coreboot/+/41620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcb67bd756dc8ae1dfd2d40020c273325583df0f Gerrit-Change-Number: 41620 Gerrit-PatchSet: 11 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Jun 2020 07:01:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: camera SSDT generation
by Paul Menzel (Code Review) 09 Jun '20

09 Jun '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41607 ) Change subject: drivers/intel/mipi_camera: camera SSDT generation ...................................................................... Patch Set 12: (13 comments) https://review.coreboot.org/c/coreboot/+/41607/12//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41607/12//COMMIT_MSG@7 PS12, Line 7: drivers/intel/mipi_camera: camera SSDT generation Please make it a statement by adding a verb (in imperative mood). > Generate SSDT for camera https://review.coreboot.org/c/coreboot/+/41607/12//COMMIT_MSG@12 PS12, Line 12: missing some properties needed for Linux drivers. Please mention the properties. https://review.coreboot.org/c/coreboot/+/41607/12//COMMIT_MSG@9 PS12, Line 9: Some boards & variants are using raw asl files to define the ACPI devices : (and related properties) required by Linux MIPI camera drivers. : The mipi_camera driver can provide a SSDB property, but it's : missing some properties needed for Linux drivers. Please re-flow for 75 characters per line. https://review.coreboot.org/c/coreboot/+/41607/12//COMMIT_MSG@21 PS12, Line 21: asl ASL https://review.coreboot.org/c/coreboot/+/41607/12//COMMIT_MSG@22 PS12, Line 22: Please mention one difference. https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… File src/drivers/intel/mipi_camera/camera.c: https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 42: uint32_t i, j; Please use the native types `unsigned int` or `size_t`. https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 607: prefix = "ERR"; /* Error */ Should a debug message be added for this case? https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 612: know knows? https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… File src/drivers/intel/mipi_camera/chip.h: https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 131: * General settings that can be used for any type (but doesn't don’t? https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 132: * necessarily need to be used/specified for each device. Missing closing ). https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 148: uint8_t num_freq_entries; /* # of elements in link_freq */ Please use native types. https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 163: * you can use zero for a value. Please re-flow for at least 80 characters per line (maybe even 96). https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 167: uint32_t nvm_size; Can native types be used here? -- To view, visit https://review.coreboot.org/c/coreboot/+/41607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Gerrit-Change-Number: 41607 Gerrit-PatchSet: 12 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Jun 2020 06:59:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: console: Update for vboot before bootblock
by build bot (Jenkins) (Code Review) 09 Jun '20

09 Jun '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41815 ) Change subject: console: Update for vboot before bootblock ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/41815/5/src/console/init.c File src/console/init.c: https://review.coreboot.org/c/coreboot/+/41815/5/src/console/init.c@70 PS5, Line 70: if (CONFIG(EARLY_PCI_BRIDGE) && !ENV_SMM && !ENV_RAMSTAGE && \ Avoid unnecessary line continuations -- To view, visit https://review.coreboot.org/c/coreboot/+/41815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc9fb0810e0816fe0a68e52287eda6145043a619 Gerrit-Change-Number: 41815 Gerrit-PatchSet: 5 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 09 Jun 2020 06:45:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot: Add option to run verstage before bootblock
by build bot (Jenkins) (Code Review) 09 Jun '20

09 Jun '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41814 ) Change subject: security/vboot: Add option to run verstage before bootblock ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/41814/6/src/security/vboot/vboot_l… File src/security/vboot/vboot_loader.c: https://review.coreboot.org/c/coreboot/+/41814/6/src/security/vboot/vboot_l… PS6, Line 16: _Static_assert( (!CONFIG(VBOOT_SEPARATE_VERSTAGE)) || (CONFIG(VBOOT_SEPARATE_VERSTAGE) && space prohibited after that open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/41814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4849777cb7ba9f90fe8428b82c21884d1e662b96 Gerrit-Change-Number: 41814 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 09 Jun 2020 06:45:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot: Add option to run verstage before bootblock
by Martin Roth (Code Review) 09 Jun '20

09 Jun '20

Hello Raul Rangel, Patrick Georgi, Furquan Shaikh, Julius Werner, Eric Peers, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41814 to look at the new patch set (#6). Change subject: security/vboot: Add option to run verstage before bootblock ...................................................................... security/vboot: Add option to run verstage before bootblock For AMD's family 17h, verstage can run as a userspace app in the PSP before the X86 is released. The flags for this have been made generic to support any other future systems that might run verstage before the main processor starts. Although an attempt has been made to make things somewhat generic, since this is the first and currently only chip to support verstage before bootblock, there are a number of options which might ultimately be needed which have currently been left out for simplicity. Examples of this are: - PCI is not currently supported - this is currently just a given instead of making a separate Kconfig option for it. - The PSP uses an ARM v7 processor, so that's the only processor that is getting updated for the verstage-before-bootblock option. BUG=b:158124527 TEST=Build with following patches Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I4849777cb7ba9f90fe8428b82c21884d1e662b96 --- M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc M src/security/vboot/common.c M src/security/vboot/misc.h M src/security/vboot/vboot_loader.c 5 files changed, 65 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/41814/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/41814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4849777cb7ba9f90fe8428b82c21884d1e662b96 Gerrit-Change-Number: 41814 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: console: Update for vboot before bootblock
by Martin Roth (Code Review) 09 Jun '20

09 Jun '20

Hello Raul Rangel, Patrick Georgi, Furquan Shaikh, Eric Peers, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41815 to look at the new patch set (#5). Change subject: console: Update for vboot before bootblock ...................................................................... console: Update for vboot before bootblock Exclude pieces of console code from the vboot if running before bootlock. The PSP verstage code will re-implement some of these in its own code. BUG=b:123887623 TEST=Build with following patches Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ifc9fb0810e0816fe0a68e52287eda6145043a619 --- M src/console/Makefile.inc M src/console/init.c 2 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/41815/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/41815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc9fb0810e0816fe0a68e52287eda6145043a619 Gerrit-Change-Number: 41815 Gerrit-PatchSet: 5 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2
by Gaggery Tsai (Code Review) 09 Jun '20

09 Jun '20

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41555 ) Change subject: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 ...................................................................... mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ For Type-C adapter, we don't have Pcritcial(10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power. BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings is correct Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc --- M src/mainboard/google/hatch/variants/puff/mainboard.c 1 file changed, 50 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/41555/1 diff --git a/src/mainboard/google/hatch/variants/puff/mainboard.c b/src/mainboard/google/hatch/variants/puff/mainboard.c index ef5df4a..8c33d4c 100644 --- a/src/mainboard/google/hatch/variants/puff/mainboard.c +++ b/src/mainboard/google/hatch/variants/puff/mainboard.c @@ -4,8 +4,11 @@ #include <chip.h> #include <delay.h> #include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> +#include <soc/pci_devs.h> #include <timer.h> #define GPIO_HDMI_HPD GPP_E13 @@ -36,10 +39,10 @@ */ #define SET_PSYSPL2(w) (9 * (w) / 10) -#define PUFF_PL2 (35) - -#define PUFF_PSYSPL2 (58) - +#define PUFF_U22_PL2 (35) +#define PUFF_U62_U42_PL2 (51) +#define PUFF_CELERON_PENTIUM_PSYSPL2 (65) +#define PUFF_CORE_CPU_PSYSPL2 (90) #define PUFF_MAX_TIME_WINDOW 6 #define PUFF_MIN_DUTYCYCLE 4 @@ -55,18 +58,15 @@ * +-------------+-----+---------+-----------+-------+ * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | * +-------------+-----+---------+-----------+-------+ - * | i7 U42 | 51 | 81 | x(.85PL4) | x(82) | - * | celeron U22 | 35 | 58 | x(.85PL4) | x(51) | + * | i7 U42 | 51 | 90 | x(.85PL4) | x(82) | + * | i3 U22 | 35 | 65 | x(.85PL4) | x(51) | * +-------------+-----+---------+-----------+-------+ * For USB C charger: - * +-------------+-----+---------+---------+-------+ - * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+---------+---------+-------+ - * | 60 (U42) | 44 | 54 | 54 | 54 | - * | 60 (U22) | 29 | 54 | 54 | x(43) | - * | n (U42) | 44 | .9n | .9n | .9n | - * | n (U22) | 29 | .9n | .9n | x(43) | - * +-------------+-----+---------+---------+-------+ + * +-------------+-----------------+---------+---------+-------+ + * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | + * +-------------+-----+-----------+---------+---------+-------+ + * | n | min(0.9n, PL2) | 0.9n | 0.9n | 0.9n | + * +-------------+-----+-----------+---------+---------+-------+ */ /* @@ -85,15 +85,22 @@ */ #define PSYS_IMAX 9600 #define BJ_VOLTS_MV 19000 +#define ROP_MAX (30) static void mainboard_set_power_limits(config_t *conf) { enum usb_chg_type type; u32 watts; u16 volts_mv, current_ma; - u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22 + u32 psyspl2 = PUFF_CELERON_PENTIUM_PSYSPL2; // default BJ value + u32 pl2 = PUFF_U22_PL2; // default PL2 for U22 int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv); + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + u16 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + dev = pcidev_path_on_root(SA_DEVFN_IGD); + u16 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ conf->tdp_psyspl3 = 0; conf->tdp_pl4 = 0; @@ -101,23 +108,44 @@ if (rv == 0 && type == USB_CHG_TYPE_PD) { /* Detected USB-PD. Base on max value of adapter */ watts = ((u32)current_ma * volts_mv) / 1000000; - psyspl2 = watts; - conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); + /* set psyspl2 to 90% of adapter rating */ + psyspl2 = SET_PSYSPL2(watts); + + /* Limit PL2 if the adapter is with lower capability */ + if (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT || + mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_6_2) + pl2 = (psyspl2 > PUFF_U62_U42_PL2) ? PUFF_U62_U42_PL2 : psyspl2; + else + pl2 = (psyspl2 > PUFF_U22_PL2) ? PUFF_U22_PL2 : psyspl2; + + conf->tdp_psyspl3 = psyspl2; /* set max possible time window */ conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; /* set minimum duty cycle */ conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; - conf->tdp_pl4 = SET_PSYSPL2(psyspl2); + /* No data about an arbitary Type-C adapter, set pl4 conservatively. */ + conf->tdp_pl4 = psyspl2; } else { - /* Input type is barrel jack */ + /*i + * Input type is barrel jack, from the SKU matrix: + * 1. i3/i5/i7 SKUs use 90W BJ + * 2. Celeron and Pentium use 65W BJ (default) + */ volts_mv = BJ_VOLTS_MV; + /* Use IGD ID to check if CPU is Core SKUs */ + if (igd_id != PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1 && + igd_id != PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5) { + psyspl2 = PUFF_CORE_CPU_PSYSPL2; + if (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT || + mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_6_2) + pl2 = PUFF_U62_U42_PL2; + } } /* voltage unit is milliVolts and current is in milliAmps */ conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); - conf->tdp_pl2_override = PUFF_PL2; - /* set psyspl2 to 90% of max adapter power */ - conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); + conf->tdp_pl2_override = pl2; + conf->tdp_psyspl2 = psyspl2; } void variant_ramstage_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/41555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc Gerrit-Change-Number: 41555 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: SMBIOS: Remove Kconfig SYSTEM_ENCLOSURE_TYPE
by Kyösti Mälkki (Code Review) 09 Jun '20

09 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42139 ) Change subject: SMBIOS: Remove Kconfig SYSTEM_ENCLOSURE_TYPE ...................................................................... SMBIOS: Remove Kconfig SYSTEM_ENCLOSURE_TYPE This gets rid of the magic numbers in Kconfig. Change-Id: Ibee033b6c99e3131bb323f0d86d306dcd82f9b45 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/Kconfig M src/arch/x86/smbios.c 2 files changed, 16 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/42139/1 diff --git a/src/Kconfig b/src/Kconfig index b96d51f..63ecd0a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -734,20 +734,6 @@ help Override the default Product name stored in SMBIOS structures. -config SMBIOS_ENCLOSURE_TYPE - hex - depends on GENERATE_SMBIOS_TABLES - default 0x09 if SYSTEM_TYPE_LAPTOP - default 0x1e if SYSTEM_TYPE_TABLET - default 0x1f if SYSTEM_TYPE_CONVERTIBLE - default 0x20 if SYSTEM_TYPE_DETACHABLE - default 0x03 - help - System Enclosure or Chassis Types as defined in SMBIOS specification. - The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop, - convertible, or tablet enclosure will be used if the appropriate - system type is selected. - endmenu source "payloads/Kconfig" diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 29d5d54..ee69408 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -479,9 +479,24 @@ return SMBIOS_BOARD_TYPE_UNKNOWN; } +/* + * System Enclosure or Chassis Types as defined in SMBIOS specification. + * The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop, + * convertible, or tablet enclosure will be used if the appropriate + * system type is selected. + */ smbios_enclosure_type __weak smbios_mainboard_enclosure_type(void) { - return CONFIG_SMBIOS_ENCLOSURE_TYPE; + if (CONFIG(SYSTEM_TYPE_LAPTOP)) + return SMBIOS_ENCLOSURE_LAPTOP; + else if (CONFIG(SYSTEM_TYPE_TABLET)) + return SMBIOS_ENCLOSURE_TABLET; + else if (CONFIG(SYSTEM_TYPE_CONVERTIBLE)) + return SMBIOS_ENCLOSURE_CONVERTIBLE; + else if (CONFIG(SYSTEM_TYPE_DETACHABLE)) + return SMBIOS_ENCLOSURE_DETACHABLE; + else + return SMBIOS_ENCLOSURE_DESKTOP; } const char *__weak smbios_system_serial_number(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/42139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibee033b6c99e3131bb323f0d86d306dcd82f9b45 Gerrit-Change-Number: 42139 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/scaleway/tagada: Move override of SMBIOS_ENCLOSURE_TYPE
by Kyösti Mälkki (Code Review) 09 Jun '20

09 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42138 ) Change subject: mb/scaleway/tagada: Move override of SMBIOS_ENCLOSURE_TYPE ...................................................................... mb/scaleway/tagada: Move override of SMBIOS_ENCLOSURE_TYPE Change-Id: Iaefeccadb82106667a5108a2c77e538474ae18c2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/scaleway/tagada/Kconfig M src/mainboard/scaleway/tagada/ramstage.c 2 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/42138/1 diff --git a/src/mainboard/scaleway/tagada/Kconfig b/src/mainboard/scaleway/tagada/Kconfig index 34473a8..cbbb6ae 100644 --- a/src/mainboard/scaleway/tagada/Kconfig +++ b/src/mainboard/scaleway/tagada/Kconfig @@ -24,8 +24,4 @@ help Location of BMC SERIAL information. -config SMBIOS_ENCLOSURE_TYPE - hex - default 0x19 # SMBIOS_ENCLOSURE_MULTI_SYSTEM_CHASSIS - endif # BOARD_SCALEWAY_TAGADA diff --git a/src/mainboard/scaleway/tagada/ramstage.c b/src/mainboard/scaleway/tagada/ramstage.c index 5cad2ba..6d5d3ff 100644 --- a/src/mainboard/scaleway/tagada/ramstage.c +++ b/src/mainboard/scaleway/tagada/ramstage.c @@ -72,6 +72,11 @@ return SMBIOS_BOARD_TYPE_SERVER_BLADE; } +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_MULTI_SYSTEM_CHASSIS; +} + /* Add any mainboard specific information for dimm */ void mainboard_add_dimm_info( struct memory_info *mem_info, -- To view, visit https://review.coreboot.org/c/coreboot/+/42138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaefeccadb82106667a5108a2c77e538474ae18c2 Gerrit-Change-Number: 42138 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register"
by Nico Huber (Code Review) 09 Jun '20

09 Jun '20

Hello build bot (Jenkins), Patrick Georgi, HAOUAS Elyes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42163 to review the following change. Change subject: Revert "sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register" ...................................................................... Revert "sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register" This reverts commit 04506e2987162ec0f280afddd6f4acac070bbf15. Turned out that `dev->command` is only a `u8` and the way it's used here is wrong: It is not supposed to reflect the state of the register but only gathers (lower) bits to be enabled during allocation. Change-Id: Iacd2b753939e8adcf5aedd4b9cf101638a324aa6 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/amd/cimx/sb800/late.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/42163/1 diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index de91a9a..1cf3ae8 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -98,7 +98,7 @@ } dev->command |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, dev->command); + pci_write_config8(dev, PCI_COMMAND, dev->command); printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacd2b753939e8adcf5aedd4b9cf101638a324aa6 Gerrit-Change-Number: 42163 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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coreboot-gerrit June 2020