coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/poppy: Add retail names
by Angel Pons (Code Review) 09 Jun '20

09 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42143 ) Change subject: mb/google/poppy: Add retail names ...................................................................... mb/google/poppy: Add retail names Taken from Chrome OS update information. Looks like nami encompasses many different devices, which would not fit in one line, so skip it. Change-Id: I53405cba269cbfc25bd4618777b946500f173e7e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/poppy/Kconfig.name 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/42143/1 diff --git a/src/mainboard/google/poppy/Kconfig.name b/src/mainboard/google/poppy/Kconfig.name index c33d7fb..9ecdb44 100644 --- a/src/mainboard/google/poppy/Kconfig.name +++ b/src/mainboard/google/poppy/Kconfig.name @@ -1,7 +1,7 @@ comment "Poppy" config BOARD_GOOGLE_ATLAS - bool "-> Atlas" + bool "-> Atlas (Google Pixelbook Go)" select BOARD_GOOGLE_BASEBOARD_POPPY select VARIANT_SPECIFIC_OPTIONS_ATLAS @@ -16,21 +16,21 @@ select VARIANT_SPECIFIC_OPTIONS_NAMI config BOARD_GOOGLE_NAUTILUS - bool "-> Nautilus" + bool "-> Nautilus (Samsung Chromebook Plus (V2 / LTE))" select BOARD_GOOGLE_BASEBOARD_POPPY select VARIANT_SPECIFIC_OPTIONS_NAUTILUS config BOARD_GOOGLE_NOCTURNE - bool "-> Nocturne" + bool "-> Nocturne (Google Pixel Slate)" select BOARD_GOOGLE_BASEBOARD_POPPY select VARIANT_SPECIFIC_OPTIONS_NOCTURNE config BOARD_GOOGLE_RAMMUS - bool "-> Rammus" + bool "-> Rammus (Asus Chromebook C425, Flip C433, Flip C434)" select BOARD_GOOGLE_BASEBOARD_POPPY select VARIANT_SPECIFIC_OPTIONS_RAMMUS config BOARD_GOOGLE_SORAKA - bool "-> Soraka" + bool "-> Soraka (HP Chromebook x2)" select BOARD_GOOGLE_BASEBOARD_POPPY select VARIANT_SPECIFIC_OPTIONS_SORAKA -- To view, visit https://review.coreboot.org/c/coreboot/+/42143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53405cba269cbfc25bd4618777b946500f173e7e Gerrit-Change-Number: 42143 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: MAINTAINERS: Add myself as some northbridges' maintainer
by Angel Pons (Code Review) 09 Jun '20

09 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42128 ) Change subject: MAINTAINERS: Add myself as some northbridges' maintainer ...................................................................... MAINTAINERS: Add myself as some northbridges' maintainer I've got hardware to test things on these northbridges, and I am quite familiar with their code. Change-Id: Ied5adbb8bad94291a1843531be8a0923464d6212 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M MAINTAINERS 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/42128/1 diff --git a/MAINTAINERS b/MAINTAINERS index 8845851..e15e31c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -178,12 +178,22 @@ S: Maintained F: src/mainboard/getac/p470 +INTEL HASWELL NORTHBRIDGE +M: Angel Pons <th3fanbus(a)gmail.com> +S: Maintained +F: src/northbridge/intel/haswell/ + INTEL PINEVIEW CHIPSET M: Damien Zammit <damien(a)zamaudio.com> M: Angel Pons <th3fanbus(a)gmail.com> S: Odd Fixes F: src/northbridge/intel/pineview/ +INTEL SANDYBRIDGE NORTHBRIDGE +M: Angel Pons <th3fanbus(a)gmail.com> +S: Maintained +F: src/northbridge/intel/sandybridge/ + INTEL D510MO MAINBOARD M: Damien Zammit <damien(a)zamaudio.com> S: Odd Fixes -- To view, visit https://review.coreboot.org/c/coreboot/+/42128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5adbb8bad94291a1843531be8a0923464d6212 Gerrit-Change-Number: 42128 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: MAINTAINERS: Add myself to x4x and pineview northbridges
by Angel Pons (Code Review) 09 Jun '20

09 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42127 ) Change subject: MAINTAINERS: Add myself to x4x and pineview northbridges ...................................................................... MAINTAINERS: Add myself to x4x and pineview northbridges Change-Id: I42b1e8670f4e2ddfea7d473421e86649211eae86 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M MAINTAINERS 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/42127/1 diff --git a/MAINTAINERS b/MAINTAINERS index 53c36e0..8845851 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -180,6 +180,7 @@ INTEL PINEVIEW CHIPSET M: Damien Zammit <damien(a)zamaudio.com> +M: Angel Pons <th3fanbus(a)gmail.com> S: Odd Fixes F: src/northbridge/intel/pineview/ @@ -190,6 +191,7 @@ INTEL X4X CHIPSET M: Damien Zammit <damien(a)zamaudio.com> +M: Angel Pons <th3fanbus(a)gmail.com> S: Odd Fixes F: src/northbridge/intel/x4x/ -- To view, visit https://review.coreboot.org/c/coreboot/+/42127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42b1e8670f4e2ddfea7d473421e86649211eae86 Gerrit-Change-Number: 42127 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: MAINTAINERS: Add myself as some mainboards' maintainer
by Angel Pons (Code Review) 09 Jun '20

09 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42126 ) Change subject: MAINTAINERS: Add myself as some mainboards' maintainer ...................................................................... MAINTAINERS: Add myself as some mainboards' maintainer I've ported some more mainboards, but forgot to update MAINTAINERS. Change-Id: I46d2cd3737d584156e8bf49a0d7ab6b0327e0063 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M MAINTAINERS 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42126/1 diff --git a/MAINTAINERS b/MAINTAINERS index 3531292..53c36e0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -287,6 +287,11 @@ S: Maintained F: src/mainboard/asrock/h81m-hds/ +ASROCK B85M PRO4 MAINBOARD +M: Angel Pons <th3fanbus(a)gmail.com> +S: Maintained +F: src/mainboard/asrock/b85m_pro4/ + ASUS AM1I-A MAINBOARD M: Mike Banon <mikebdp2(a)gmail.com> S: Maintained @@ -302,11 +307,21 @@ S: Maintained F: src/mainboard/asus/p5qc/ +ASUS P5QPL-AM MAINBOARD & VARIANTS +M: Angel Pons <th3fanbus(a)gmail.com> +S: Maintained +F: src/mainboard/asus/p5qpl-am/ + ASUS P8H61-M LX MAINBOARD M: Tristan Corrick <tristan(a)corrick.kiwi> S: Maintained F: src/mainboard/asus/p8h61-m_lx/ +ASUS P8H61-M LX3 R2.0 MAINBOARD +M: Angel Pons <th3fanbus(a)gmail.com> +S: Maintained +F: src/mainboard/asus/p8h61-m_lx3_r2_0/ + ASUS P8H61-M PRO MAINBOARD M: Angel Pons <th3fanbus(a)gmail.com> S: Maintained @@ -317,6 +332,11 @@ S: Maintained F: src/mainboard/asus/p8z77-m_pro/ +ASUS P8Z77-V LX2 MAINBOARD +M: Angel Pons <th3fanbus(a)gmail.com> +S: Maintained +F: src/mainboard/asus/p8z77-v_lx2/ + LIBRETREND LT1000 MAINBOARD M: Piotr Król <piotr.krol(a)3mdeb.com> M: Michał Żygowski <michal.zygowski(a)3mdeb.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/42126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46d2cd3737d584156e8bf49a0d7ab6b0327e0063 Gerrit-Change-Number: 42126 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: Add support for call method
by Patrick Rudolph (Code Review) 09 Jun '20

09 Jun '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41620 ) Change subject: acpi: Add support for call method ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/41620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcb67bd756dc8ae1dfd2d40020c273325583df0f Gerrit-Change-Number: 41620 Gerrit-PatchSet: 11 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 09 Jun 2020 05:22:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: camera SSDT generation
by Sugnan Prabhu S (Code Review) 09 Jun '20

09 Jun '20

Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41607 ) Change subject: drivers/intel/mipi_camera: camera SSDT generation ...................................................................... Patch Set 12: (10 comments) https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… File src/drivers/intel/mipi_camera/camera.c: https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 40: = 0; > will update this in next patch. Done https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 54: struct acpi_dp *lanes = acpi_dp_new_table("data-lanes"); : uint32_t j; > in coreboot, we usually declare all local variables at the top of the function. Done https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 94: if (!config->pld.ignore_color) : config->pld.ignore_color = 1; : : if (!config->pld.visible) : config->pld.visible = 1; : : if (!config->pld.vertical_offset) : config->pld.vertical_offset = 0xffff; : : if (!config->pld.horizontal_offset) : config->pld.horizontal_offset = 0xffff; : : /* : * PLD_PANEL_TOP has a value of zero, so the following will change any instance : * of PLD_PANEL_TOP to PLD_PANEL_FRONT unless disable_pld_defaults is set. : */ : if (!config->pld.panel) : config->pld.panel = PLD_PANEL_FRONT; : : /* : * PLD_HORIZONTAL_POSITION_LEFT has a value of zero, so the following will : * change any instance of that value to PLD_HORIZONTAL_POSITION_CENTER unless : * disable_pld_defaults is set. : */ : if (!config->pld.horizontal_position) : config->pld.horizontal_position = PLD_HORIZONTAL_POSITION_CENTER; : : /* : * The desired default for |vertical_position| is PLD_VERTICAL_POSITION_UPPER, : * which has a value of zero so no work is needed to set a default. The same : * applies for setting |shape| to PLD_SHAPE_ROUND. : */ > suggestion: break this out into a separate function Done https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 139: 0x4 > 4 Done https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 148: 822ace8f-2814-4174-a56b-5f029fe079ee > a symbolic constant with a nice name would be helpful Done https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 156: 26257549-9271-4ca4-bb43-c4899d5a4881 > a symbolic constant with a nice name would be helpful Done https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 167: acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | : ((uint32_t)i2c_addr) << 8 | 0x0); /* type 0 for sensor */ : acpigen_pop_len(); /* If Arg2=2 */ : : if (config->ssdb.vcm_type) { : /* If (LEqual (Local1, 3)) */ : acpigen_write_if_lequal_op_int(LOCAL1_OP, 3); : acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | /* type 1 for vcm */ : ((uint32_t)config->vcm_address) << 8 | 0x01); : acpigen_pop_len(); /* If Arg2=3 */ : } : : if (config->ssdb.rom_type) { : /* If (LEqual (Local1, 3 or 4)) */ : acpigen_write_if_lequal_op_int(LOCAL1_OP, 3 + (config->ssdb.vcm_type ? 1 : 0)); : acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | /* type 2 for rom */ : ((uint32_t)config->rom_address) << 8 | 0x02); : acpigen_pop_len(); /* If Arg2=3 or 4 */ > suggestion: add a helper function for creating these return values, with maybe an enum per type, sen […] Done https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 229: if (!config->disable_ssdb_defaults) { : if (!config->ssdb.bdf_value) : config->ssdb.bdf_value = PCI_DEVFN(CIO2_PCI_DEV, CIO2_PCI_FN); : : if (!config->ssdb.platform) : config->ssdb.platform = PLATFORM_SKC; : : if (!config->ssdb.flash_support) : config->ssdb.flash_support = FLASH_DISABLE; : : if (!config->ssdb.privacy_led) : config->ssdb.privacy_led = PRIVACY_LED_A_16mA; : : if (!config->ssdb.mipi_define) : config->ssdb.mipi_define = MIPI_INFO_ACPI_DEFINED; : : if (!config->ssdb.mclk_speed) : config->ssdb.mclk_speed = CLK_FREQ_19_2MHZ; : : if (!config->ssdb.lanes_used) { : cio2_config = cio2 ? cio2->chip_info : NULL; : : if (!cio2_config) { : printk(BIOS_ERR, "Failed to get CIO2 config\n"); : } else if (cio2_config->device_type != INTEL_ACPI_CAMERA_CIO2) { : printk(BIOS_ERR, "Device type isn't CIO2: %u\n", : (u32)cio2_config->device_type); : } else if (config->ssdb.link_used >= cio2_config->cio2_num_ports) { : printk(BIOS_ERR, "%u exceeds CIO2's %u links\n", : (u32)config->ssdb.link_used, : (u32)cio2_config->cio2_num_ports); : } else { : config->ssdb.lanes_used = : cio2_config->cio2_lanes_used[config->ssdb.link_used]; : } : } : } > suggestion: same here, separate this out into a separate function Done https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 298: remote_name = "\\_SB.PCI0.CIO2"; > Could you add this to the rest of the defaults? Done https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 566: if (config->device_type == INTEL_ACPI_CAMERA_CIO2) : return "CIO2"; : else if (config->device_type == INTEL_ACPI_CAMERA_IMGU) : return "IMGU"; : else if (config->device_type == INTEL_ACPI_CAMERA_PMIC) : return "PMIC"; : : switch (config->device_type) { : case INTEL_ACPI_CAMERA_SENSOR: : prefix = "CAM"; : break; : case INTEL_ACPI_CAMERA_VCM: : prefix = "VCM"; : break; : case INTEL_ACPI_CAMERA_NVM: : prefix = "NVM"; : break; : default: : prefix = "ERR"; /* Error */ : break; : } > This can just be one switch statement; you can just return from the cases that have all 4 characters […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/41607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Gerrit-Change-Number: 41607 Gerrit-PatchSet: 12 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 09 Jun 2020 04:41:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: camera SSDT generation
by Sugnan Prabhu S (Code Review) 09 Jun '20

09 Jun '20

Hello Varshit B Pandya, Matt Delco, build bot (Jenkins), Daniel Kang, Furquan Shaikh, Wonkyu Kim, Tim Wawrzynczak, Rizwan Qureshi, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41607 to look at the new patch set (#12). Change subject: drivers/intel/mipi_camera: camera SSDT generation ...................................................................... drivers/intel/mipi_camera: camera SSDT generation Some boards & variants are using raw asl files to define the ACPI devices (and related properties) required by Linux MIPI camera drivers. The mipi_camera driver can provide a SSDB property, but it's missing some properties needed for Linux drivers. This change updates the mipi_camera driver so it can provide what's required by Linux and expands the support for the IMGU and CIO2 devices. BUG=WIP BRANCH=none TEST=Verified that the ACPI state generated by the driver (with appropriate devicetree changes) is extremely comparible to what's generated by the asl files. Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Signed-off-by: Matt Delco <delco(a)chromium.org> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h 2 files changed, 659 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/41607/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/41607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Gerrit-Change-Number: 41607 Gerrit-PatchSet: 12 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: acpi: Add support for call method
by Sugnan Prabhu S (Code Review) 09 Jun '20

09 Jun '20

Hello Varshit B Pandya, build bot (Jenkins), Daniel Kang, Furquan Shaikh, Wonkyu Kim, Tim Wawrzynczak, Rizwan Qureshi, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41620 to look at the new patch set (#11). Change subject: acpi: Add support for call method ...................................................................... acpi: Add support for call method This change adds support function for calling methods and method to add STA function which returns an external variable. Change-Id: Ibcb67bd756dc8ae1dfd2d40020c273325583df0f Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/41620/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/41620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcb67bd756dc8ae1dfd2d40020c273325583df0f Gerrit-Change-Number: 41620 Gerrit-PatchSet: 11 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: console: Update for vboot before bootblock
by Kyösti Mälkki (Code Review) 09 Jun '20

09 Jun '20

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41815 ) Change subject: console: Update for vboot before bootblock ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/41815/4/src/console/Makefile.inc File src/console/Makefile.inc: https://review.coreboot.org/c/coreboot/+/41815/4/src/console/Makefile.inc@14 PS4, Line 14: ifneq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) The files here should be arch-agnostic. Which parts exactly are not usable for psp-verstage? Is there a followup to look at? https://review.coreboot.org/c/coreboot/+/41815/4/src/console/init.c File src/console/init.c: https://review.coreboot.org/c/coreboot/+/41815/4/src/console/init.c@72 PS4, Line 72: pci_early_bridge_init > I think there's a good argument to make for having it here. […] We could probably change this to EARLY_PCI_BRIDGE && (ENV_BOOTBLOCK || ENV_ROMSTAGE). I don't see why we would need it called for verstage as the BARs on the secondary side PCIe device (assummed serial uart) persist across stage changes. The entire EARLY_PCI_BRIDGE is very rarely used indeed and probably does not even work with FSP, PCIe rootports are not usable until late FSP-M from what I remember. Like Martin said, it was used for debugging some of the first Chromebooks with mini-PCI-e serial cards, before servo and closed-case-debugging. -- To view, visit https://review.coreboot.org/c/coreboot/+/41815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc9fb0810e0816fe0a68e52287eda6145043a619 Gerrit-Change-Number: 41815 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Jun 2020 04:18:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: Add support for call method and store value
by Sugnan Prabhu S (Code Review) 09 Jun '20

09 Jun '20

Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41620 ) Change subject: acpi: Add support for call method and store value ...................................................................... Patch Set 10: (2 comments) https://review.coreboot.org/c/coreboot/+/41620/5/src/acpi/acpigen.c File src/acpi/acpigen.c: https://review.coreboot.org/c/coreboot/+/41620/5/src/acpi/acpigen.c@1928 PS5, Line 1928: void acpigen_call_method(const char *name, unsigned char *params, int params_len) : { : int i; : char ud[] = "____"; : for (i = 0; i < 4; i++) { : if ((name[i] == '\0')) { : acpigen_emit_stream(ud, 4 - i); : break; : } : acpigen_emit_byte(name[i]); : } : : for (i = 0; i < params_len; i++) : acpigen_write_byte(params[i]); : } > Why is this necessary? This is required to call any method. we are using this in powerresource generation patch to call MCON and MCOF https://review.coreboot.org/c/coreboot/+/41624/11/src/drivers/intel/mipi_ca… https://review.coreboot.org/c/coreboot/+/41620/5/src/acpi/acpigen.c@1944 PS5, Line 1944: void acpigen_write_store_var(const char *name, uint8_t value) : { : int i; : char ud[] = "____"; : : acpigen_write_store(); : acpigen_emit_byte(value); : : for (i = 0; i < 4; i++) { : if ((name[i] == '\0')) { : acpigen_emit_stream(ud, 4 - i); : break; : } : acpigen_emit_byte(name[i]); : } : } > Why is this necessary? This method has been removed in the latest patch. https://review.coreboot.org/c/coreboot/+/41620/10/src/acpi/acpigen.c During development I couldn't find any method for storing value in to a variable, but later found that acpigen_write_store_op_to_namestr has been added. -- To view, visit https://review.coreboot.org/c/coreboot/+/41620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcb67bd756dc8ae1dfd2d40020c273325583df0f Gerrit-Change-Number: 41620 Gerrit-PatchSet: 10 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 09 Jun 2020 03:05:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit June 2020