coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: lib: Upgrade LZMA Decoder to version 19.0
by Paul Menzel (Code Review) 09 Jun '20

09 Jun '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41963 ) Change subject: lib: Upgrade LZMA Decoder to version 19.0 ...................................................................... Patch Set 5: Elyes, thank you for testing. It’d be great if you summarized result of your tests though. So, the new code is also slower for you as mentioned in ticket #194. [1]: https://ticket.coreboot.org/issues/194 -- To view, visit https://review.coreboot.org/c/coreboot/+/41963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f43e8bdda6536c719879381cad6a921dd94718 Gerrit-Change-Number: 41963 Gerrit-PatchSet: 5 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes HAOUAS Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Jun 2020 14:28:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Upgrade LZMA Decoder to version 19.0
by HAOUAS Elyes (Code Review) 09 Jun '20

09 Jun '20

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41963 ) Change subject: lib: Upgrade LZMA Decoder to version 19.0 ...................................................................... Patch Set 5: tested on (i945GC,ich7) based board: =========== Old LZMA version =========== 'COREBOOT' (CBFS, size 523776, offset 512) It is possible to perform either the write action or the CBFS add/remove actions on every section listed above. To see the image's read-only sections as well, rerun with the -w option. CBFSPRINT coreboot.rom FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 47676 none cpu_microcode_blob.bin 0xbb40 microcode 181248 none fallback/ramstage 0x37fc0 stage 68670 none config 0x48c40 raw 163 none revision 0x48d40 raw 674 none fallback/dsdt.aml 0x49040 raw 8699 none cmos_layout.bin 0x4b2c0 cmos_layout 1856 none fallback/postcar 0x4ba40 stage 18676 none fallback/payload 0x50380 simple elf 69881 none payload_config 0x614c0 raw 1621 none payload_revision 0x61b80 raw 237 none (empty) 0x61cc0 null 57560 none bootblock 0x6fdc0 bootblock 65536 none HOSTCC cbfstool/ifwitool.o HOSTCC cbfstool/ifwitool (link) Built nec/945g-m4 (945G-M4) =========== New LZMA version =========== 'COREBOOT' (CBFS, size 523776, offset 512) It is possible to perform either the write action or the CBFS add/remove actions on every section listed above. To see the image's read-only sections as well, rerun with the -w option. CBFSPRINT coreboot.rom FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 47676 none cpu_microcode_blob.bin 0xbb40 microcode 181248 none fallback/ramstage 0x37fc0 stage 72231 none config 0x49a40 raw 289 none revision 0x49bc0 raw 674 none fallback/dsdt.aml 0x49ec0 raw 8699 none cmos_layout.bin 0x4c140 cmos_layout 1856 none fallback/postcar 0x4c8c0 stage 23416 none fallback/payload 0x52480 simple elf 69881 none payload_config 0x635c0 raw 1621 none payload_revision 0x63c80 raw 237 none (empty) 0x63dc0 null 49112 none bootblock 0x6fdc0 bootblock 65536 none HOSTCC cbfstool/ifwitool.o HOSTCC cbfstool/ifwitool (link) Built nec/945g-m4 (945G-M4) ========== cbmem -t log: =========== ===== Old LZMA version ===== 27 entries total: 0:1st timestamp 541 11:start of bootblock 20,035 (19,494) 12:end of bootblock 117,490 (97,455) 13:starting to load romstage 345,636 (228,145) 14:finished loading romstage 387,770 (42,134) 1:start of romstage 511,440 (123,670) 2:before RAM initialization 955,790 (444,349) 3:after RAM initialization 3,108,870 (2,153,079) 4:end of romstage 5,696,114 (2,587,243) 100:start of postcar 5,784,010 (87,896) 101:end of postcar 5,784,011 (0) 8:starting to load ramstage 5,794,848 (10,837) 15:starting LZMA decompress (ignore for x86) 5,800,680 (5,832) 16:finished LZMA decompress (ignore for x86) 5,875,438 (74,757) 9:finished loading ramstage 5,887,719 (12,281) 10:start of ramstage 5,901,698 (13,979) 30:device enumeration 5,902,848 (1,149) 40:device configuration 6,172,352 (269,503) 50:device enable 7,235,082 (1,062,729) 60:device initialization 7,340,554 (105,472) 70:device setup done 8,472,667 (1,132,113) 75:cbmem post 8,477,617 (4,949) 80:write tables 8,477,620 (3) 85:finalize chips 8,866,202 (388,581) 90:load payload 8,871,408 (5,206) 15:starting LZMA decompress (ignore for x86) 8,912,540 (41,131) 16:finished LZMA decompress (ignore for x86) 8,987,157 (74,617) 99:selfboot jump 9,005,616 (18,458) Total Time: 9,005,062 ===== New LZMA version ===== 27 entries total: 0:1st timestamp 541 11:start of bootblock 19,996 (19,455) 12:end of bootblock 117,451 (97,455) 13:starting to load romstage 345,596 (228,144) 14:finished loading romstage 387,676 (42,080) 1:start of romstage 511,346 (123,669) 2:before RAM initialization 956,004 (444,657) 3:after RAM initialization 3,107,685 (2,151,681) 4:end of romstage 5,700,401 (2,592,716) 100:start of postcar 5,788,304 (87,902) 101:end of postcar 5,788,304 (0) 8:starting to load ramstage 5,799,140 (10,835) 15:starting LZMA decompress (ignore for x86) 5,804,973 (5,833) 16:finished LZMA decompress (ignore for x86) 5,956,720 (151,746) 9:finished loading ramstage 5,969,004 (12,284) 10:start of ramstage 5,982,977 (13,972) 30:device enumeration 5,984,126 (1,149) 40:device configuration 6,253,630 (269,504) 50:device enable 7,316,351 (1,062,721) 60:device initialization 7,421,815 (105,463) 70:device setup done 8,551,456 (1,129,640) 75:cbmem post 8,556,405 (4,948) 80:write tables 8,556,408 (3) 85:finalize chips 8,945,092 (388,684) 90:load payload 8,950,388 (5,295) 15:starting LZMA decompress (ignore for x86) 8,991,519 (41,131) 16:finished LZMA decompress (ignore for x86) 9,138,001 (146,481) 99:selfboot jump 9,156,542 (18,541) Total Time: 9,155,989 -- To view, visit https://review.coreboot.org/c/coreboot/+/41963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f43e8bdda6536c719879381cad6a921dd94718 Gerrit-Change-Number: 41963 Gerrit-PatchSet: 5 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes HAOUAS Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Jun 2020 11:26:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/libpayload: Fix BIT macro redefinition error
by Subrata Banik (Code Review) 09 Jun '20

09 Jun '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41059 ) Change subject: payloads/libpayload: Fix BIT macro redefinition error ...................................................................... payloads/libpayload: Fix BIT macro redefinition error /firmware/libpayload/bin/../include/libpayload.h:88: error: "BIT" redefined [-Werror] #define BIT(x) (1ul << (x)) from src/board/tglrvp/board.c:28: usr/include/chromeos/ec/ec_commands.h:49: note: this is the location of the previous definition #define BIT(nr) (1UL << (nr)) Change-Id: I0a5fd069acbd7e59980f6602b63362fcb3220009 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M payloads/libpayload/include/libpayload.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/41059/1 diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index e3f8fd3..65aec2e 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -85,7 +85,9 @@ #define MAX(a, b) __CMP(a, b, >) #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) +#ifndef BIT #define BIT(x) (1ul << (x)) +#endif #define DIV_ROUND_UP(x, y) ({ \ typeof(x) _div_local_x = (x); \ -- To view, visit https://review.coreboot.org/c/coreboot/+/41059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a5fd069acbd7e59980f6602b63362fcb3220009 Gerrit-Change-Number: 41059 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: console: Update for vboot before bootblock
by Kyösti Mälkki (Code Review) 09 Jun '20

09 Jun '20

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41815 ) Change subject: console: Update for vboot before bootblock ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/41815/6/src/console/init.c File src/console/init.c: https://review.coreboot.org/c/coreboot/+/41815/6/src/console/init.c@70 PS6, Line 70: CONFIG(EARLY_PCI_BRIDGE) > If I understand this correctly you want to support EARLY_PCI_BRIDGE […] I think you missed one negation there? It was stated elsewhere PCI config does not work inside psp-verstage. I had comment on patchset #4 for alternative solution. -- To view, visit https://review.coreboot.org/c/coreboot/+/41815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc9fb0810e0816fe0a68e52287eda6145043a619 Gerrit-Change-Number: 41815 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Jun 2020 08:45:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: console: Update for vboot before bootblock
by Nico Huber (Code Review) 09 Jun '20

09 Jun '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41815 ) Change subject: console: Update for vboot before bootblock ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/41815/6/src/console/init.c File src/console/init.c: https://review.coreboot.org/c/coreboot/+/41815/6/src/console/init.c@70 PS6, Line 70: CONFIG(EARLY_PCI_BRIDGE) If I understand this correctly you want to support EARLY_PCI_BRIDGE && VBOOT_STARTS_BEFORE_BOOTBLOCK? Is this really a use case? If EARLY_PCI_BRIDGE is needed for later stages, how would the console work in the PSP? -- To view, visit https://review.coreboot.org/c/coreboot/+/41815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc9fb0810e0816fe0a68e52287eda6145043a619 Gerrit-Change-Number: 41815 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Jun 2020 08:24:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: camera SSDT generation
by Sugnan Prabhu S (Code Review) 09 Jun '20

09 Jun '20

Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41607 ) Change subject: drivers/intel/mipi_camera: camera SSDT generation ...................................................................... Patch Set 12: (13 comments) https://review.coreboot.org/c/coreboot/+/41607/12//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41607/12//COMMIT_MSG@7 PS12, Line 7: drivers/intel/mipi_camera: camera SSDT generation > Please make it a statement by adding a verb (in imperative mood). […] I will update this in next patch. https://review.coreboot.org/c/coreboot/+/41607/12//COMMIT_MSG@9 PS12, Line 9: Some boards & variants are using raw asl files to define the ACPI devices : (and related properties) required by Linux MIPI camera drivers. : The mipi_camera driver can provide a SSDB property, but it's : missing some properties needed for Linux drivers. > Please re-flow for 75 characters per line. I will update this in next patch. https://review.coreboot.org/c/coreboot/+/41607/12//COMMIT_MSG@12 PS12, Line 12: missing some properties needed for Linux drivers. > Please mention the properties. I will update this in next patch. https://review.coreboot.org/c/coreboot/+/41607/12//COMMIT_MSG@21 PS12, Line 21: asl > ASL I will update this in next patch. https://review.coreboot.org/c/coreboot/+/41607/12//COMMIT_MSG@22 PS12, Line 22: > Please mention one difference. I will update this in next patch. https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… File src/drivers/intel/mipi_camera/camera.c: https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 42: uint32_t i, j; > Please use the native types `unsigned int` or `size_t`. I will update this in next patch. https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 607: prefix = "ERR"; /* Error */ > Should a debug message be added for this case? I will update this in next patch. https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 612: know > knows? I will update this in next patch. https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… File src/drivers/intel/mipi_camera/chip.h: https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 131: * General settings that can be used for any type (but doesn't > don’t? I will update this in next patch. https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 132: * necessarily need to be used/specified for each device. > Missing closing ). I will update this in next patch. https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 148: uint8_t num_freq_entries; /* # of elements in link_freq */ > Please use native types. Any specific reason to change them to native. Other structures in this file are already using non native types. https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 163: * you can use zero for a value. > Please re-flow for at least 80 characters per line (maybe even 96). I will update this in next patch. https://review.coreboot.org/c/coreboot/+/41607/12/src/drivers/intel/mipi_ca… PS12, Line 167: uint32_t nvm_size; > Can native types be used here? Any specific reason to change them to native. Other structures in this file are already using non native types. -- To view, visit https://review.coreboot.org/c/coreboot/+/41607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Gerrit-Change-Number: 41607 Gerrit-PatchSet: 12 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Jun 2020 08:05:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: camera SSDT changes for JSLRVP
by Paul Menzel (Code Review) 09 Jun '20

09 Jun '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41758 ) Change subject: mb/intel/jasperlake_rvp: camera SSDT changes for JSLRVP ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/c/coreboot/+/41758/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41758/5//COMMIT_MSG@7 PS5, Line 7: mb/intel/jasperlake_rvp: camera SSDT changes for JSLRVP Please make it a statement by adding a verb in imperative mood. https://review.coreboot.org/c/coreboot/+/41758/5//COMMIT_MSG@8 PS5, Line 8: Please elaborate. -- To view, visit https://review.coreboot.org/c/coreboot/+/41758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Gerrit-Change-Number: 41758 Gerrit-PatchSet: 5 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 09 Jun 2020 07:09:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: Support for adding camera power resource
by Paul Menzel (Code Review) 09 Jun '20

09 Jun '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41624 ) Change subject: drivers/intel/mipi_camera: Support for adding camera power resource ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/c/coreboot/+/41624/12//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41624/12//COMMIT_MSG@7 PS12, Line 7: drivers/intel/mipi_camera: Support for adding camera power resource Please make it a statement by adding a verb (in imperative mood): > Add support for adding camera power resource > Support adding camera power resource -- To view, visit https://review.coreboot.org/c/coreboot/+/41624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e Gerrit-Change-Number: 41624 Gerrit-PatchSet: 12 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Jun 2020 07:08:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: console: Update for vboot before bootblock
by build bot (Jenkins) (Code Review) 09 Jun '20

09 Jun '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41815 ) Change subject: console: Update for vboot before bootblock ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/41815/6/src/console/init.c File src/console/init.c: https://review.coreboot.org/c/coreboot/+/41815/6/src/console/init.c@70 PS6, Line 70: if (CONFIG(EARLY_PCI_BRIDGE) && !ENV_SMM && !ENV_RAMSTAGE && \ Avoid unnecessary line continuations -- To view, visit https://review.coreboot.org/c/coreboot/+/41815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc9fb0810e0816fe0a68e52287eda6145043a619 Gerrit-Change-Number: 41815 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Jun 2020 07:08:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot: Add option to run verstage before bootblock
by build bot (Jenkins) (Code Review) 09 Jun '20

09 Jun '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41814 ) Change subject: security/vboot: Add option to run verstage before bootblock ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/41814/7/src/security/vboot/vboot_l… File src/security/vboot/vboot_loader.c: https://review.coreboot.org/c/coreboot/+/41814/7/src/security/vboot/vboot_l… PS7, Line 16: _Static_assert( (!CONFIG(VBOOT_SEPARATE_VERSTAGE)) || (CONFIG(VBOOT_SEPARATE_VERSTAGE) && space prohibited after that open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/41814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4849777cb7ba9f90fe8428b82c21884d1e662b96 Gerrit-Change-Number: 41814 Gerrit-PatchSet: 7 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Jun 2020 07:07:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2020