coreboot-gerrit June 2020

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Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197
by Srinidhi N Kaushik (Code Review) 09 Jun '20

09 Jun '20

Hello John Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42046 to review the following change. Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197 ...................................................................... vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197 Update FSP headers for Tiger Lake platform generated based FSP version 3197 to include below additional UPD: FSPS: ITbtConnectTopologyTimeoutInMs Signed-off-by: John Zhao <john.zhao(a)intel.com> Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I06d605b156c1e6f90921c20e0b8fbbe4d64916ce --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 1 file changed, 39 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/42046/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index a68ba17..8f5e6d0 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -528,7 +528,17 @@ /** Offset 0x04D8 - Reserved **/ - UINT8 Reserved25[11]; + UINT8 Reserved25[2]; + +/** Offset 0x04DA - ITbtConnectTopology Timeout value + ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range + is 0-10000. 100 = 100 ms. +**/ + UINT16 ITbtConnectTopologyTimeoutInMs; + +/** Offset 0x04DC - Reserved +**/ + UINT8 Reserved26[7]; /** Offset 0x04E3 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports @@ -538,7 +548,7 @@ /** Offset 0x04E7 - Reserved **/ - UINT8 Reserved26[194]; + UINT8 Reserved27[194]; /** Offset 0x05A9 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit @@ -549,7 +559,7 @@ /** Offset 0x05AA - Reserved **/ - UINT8 Reserved27[10]; + UINT8 Reserved28[10]; /** Offset 0x05B4 - CpuMpPpi <b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. @@ -560,7 +570,7 @@ /** Offset 0x05B8 - Reserved **/ - UINT8 Reserved28[46]; + UINT8 Reserved29[46]; /** Offset 0x05E6 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -570,7 +580,7 @@ /** Offset 0x05E7 - Reserved **/ - UINT8 Reserved29[36]; + UINT8 Reserved30[36]; /** Offset 0x060B - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -579,7 +589,7 @@ /** Offset 0x060C - Reserved **/ - UINT8 Reserved30[2]; + UINT8 Reserved31[2]; /** Offset 0x060E - Enable PCH ISH SPI pins assigned Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -603,7 +613,7 @@ /** Offset 0x061C - Reserved **/ - UINT8 Reserved31[2]; + UINT8 Reserved32[2]; /** Offset 0x061E - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region @@ -614,7 +624,7 @@ /** Offset 0x061F - Reserved **/ - UINT8 Reserved32[2]; + UINT8 Reserved33[2]; /** Offset 0x0621 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper @@ -625,7 +635,7 @@ /** Offset 0x0622 - Reserved **/ - UINT8 Reserved33[24]; + UINT8 Reserved34[24]; /** Offset 0x063A - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. @@ -634,7 +644,7 @@ /** Offset 0x0652 - Reserved **/ - UINT8 Reserved34[24]; + UINT8 Reserved35[24]; /** Offset 0x066A - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. @@ -648,7 +658,7 @@ /** Offset 0x069A - Reserved **/ - UINT8 Reserved35[168]; + UINT8 Reserved36[168]; /** Offset 0x0742 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. @@ -663,7 +673,7 @@ /** Offset 0x075B - Reserved **/ - UINT8 Reserved36[5]; + UINT8 Reserved37[5]; /** Offset 0x0760 - Touch Host Controller Port 1 Assignment Assign THC Port 1 @@ -673,7 +683,7 @@ /** Offset 0x0761 - Reserved **/ - UINT8 Reserved37[79]; + UINT8 Reserved38[79]; /** Offset 0x07B0 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is @@ -694,7 +704,7 @@ /** Offset 0x07F8 - Reserved **/ - UINT8 Reserved38[79]; + UINT8 Reserved39[79]; /** Offset 0x0847 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. @@ -717,7 +727,7 @@ /** Offset 0x084A - Reserved **/ - UINT8 Reserved39[16]; + UINT8 Reserved40[16]; /** Offset 0x085A - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. @@ -727,7 +737,7 @@ /** Offset 0x085B - Reserved **/ - UINT8 Reserved40[42]; + UINT8 Reserved41[42]; /** Offset 0x0885 - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). @@ -741,7 +751,7 @@ /** Offset 0x0895 - Reserved **/ - UINT8 Reserved41; + UINT8 Reserved42; /** Offset 0x0896 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. @@ -750,7 +760,7 @@ /** Offset 0x08A6 - Reserved **/ - UINT8 Reserved42[72]; + UINT8 Reserved43[72]; /** Offset 0x08EE - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. @@ -764,7 +774,7 @@ /** Offset 0x0908 - Reserved **/ - UINT8 Reserved43[16]; + UINT8 Reserved44[16]; /** Offset 0x0918 - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time @@ -784,7 +794,7 @@ /** Offset 0x091A - Reserved **/ - UINT8 Reserved44[3]; + UINT8 Reserved45[3]; /** Offset 0x091D - Hybrid Storage Detection and Configuration Mode Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. @@ -795,7 +805,7 @@ /** Offset 0x091E - Reserved **/ - UINT8 Reserved45[96]; + UINT8 Reserved46[96]; /** Offset 0x097E - USB2 Port Reset Message Enable 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message @@ -804,7 +814,7 @@ /** Offset 0x098E - Reserved **/ - UINT8 Reserved46[322]; + UINT8 Reserved47[322]; /** Offset 0x0AD0 - RpPtmBytes **/ @@ -812,7 +822,7 @@ /** Offset 0x0AD4 - Reserved **/ - UINT8 Reserved47[101]; + UINT8 Reserved48[101]; /** Offset 0x0B39 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, @@ -830,7 +840,7 @@ /** Offset 0x0B3A - Reserved **/ - UINT8 Reserved48[80]; + UINT8 Reserved49[80]; /** Offset 0x0B8A - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns @@ -840,7 +850,7 @@ /** Offset 0x0B8B - Reserved **/ - UINT8 Reserved49[179]; + UINT8 Reserved50[179]; /** Offset 0x0C3E - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. @@ -862,7 +872,7 @@ /** Offset 0x0C41 - Reserved **/ - UINT8 Reserved50; + UINT8 Reserved51; /** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -876,7 +886,7 @@ /** Offset 0x0CA2 - Reserved **/ - UINT8 Reserved51[269]; + UINT8 Reserved52[269]; /** Offset 0x0DAF - LpmStateEnableMask **/ @@ -884,7 +894,7 @@ /** Offset 0x0DB0 - Reserved **/ - UINT8 Reserved52[232]; + UINT8 Reserved53[232]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -901,7 +911,7 @@ /** Offset 0x0E98 **/ - UINT8 UnusedUpdSpace36[6]; + UINT8 UnusedUpdSpace35[6]; /** Offset 0x0E9E **/ -- To view, visit https://review.coreboot.org/c/coreboot/+/42046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06d605b156c1e6f90921c20e0b8fbbe4d64916ce Gerrit-Change-Number: 42046 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: nb/intel/x4x: Use PCI bitwise ops
by Angel Pons (Code Review) 09 Jun '20

09 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42155 ) Change subject: nb/intel/x4x: Use PCI bitwise ops ...................................................................... nb/intel/x4x: Use PCI bitwise ops Tested with BUILD_TIMELESS=1, Intel DG43GT does not change. Change-Id: I1bb7a7fd808cbbb45efbbfb9581c6a948323a48f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/x4x/gma.c M src/northbridge/intel/x4x/raminit.c M src/northbridge/intel/x4x/raminit_ddr23.c 3 files changed, 10 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/42155/1 diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index d2d2bb0..68d382e 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -48,11 +48,9 @@ static void gma_func0_disable(struct device *dev) { struct device *dev_host = pcidev_on_root(0, 0); - u16 ggc; - ggc = pci_read_config16(dev_host, D0F0_GGC); - ggc |= (1 << 1); /* VGA cycles to discrete GPU */ - pci_write_config16(dev_host, D0F0_GGC, ggc); + /* VGA cycles to discrete GPU */ + pci_or_config16(dev_host, D0F0_GGC, 1 << 1); } static void gma_generate_ssdt(const struct device *device) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index e505a5b..5fc9a7a 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -597,10 +597,9 @@ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); /* do magic 0xf0 thing. */ - u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); + pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); + + pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2)); full_reset(); } @@ -690,11 +689,10 @@ do_raminit(&s, fast_boot); - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~0x80); + pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~0x80); - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, reg8 | 1); + pci_or_config8(PCI_DEV(0, 0, 0), 0xf4, 1); + printk(BIOS_DEBUG, "RAM initialization finished.\n"); cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME); diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index ef1094f..332af32 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1701,7 +1701,6 @@ u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; - u8 reg8; ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); gfxsize = ggc2uma[(ggc & 0xf0) >> 4]; @@ -1745,11 +1744,8 @@ pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud); pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20); pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20); - /* Enable and set tseg size to 2M */ - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); - reg8 &= ~0x7; - reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */ - pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8); + /* Enable and set TSEG size to 2M */ + pci_update_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bb7a7fd808cbbb45efbbfb9581c6a948323a48f Gerrit-Change-Number: 42155 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/haswell: Use PCI bitwise ops
by Angel Pons (Code Review) 09 Jun '20

09 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42153 ) Change subject: nb/intel/haswell: Use PCI bitwise ops ...................................................................... nb/intel/haswell: Use PCI bitwise ops Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I99379299f7e744a3e906bdbc46d55060d9c75d6a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/minihd.c 2 files changed, 2 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/42153/1 diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index fb148fa..fd188a1 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -37,7 +37,6 @@ { bool igd_enabled; u16 ggc; - u8 reg8; printk(BIOS_DEBUG, "Initializing IGD...\n"); @@ -59,10 +58,7 @@ } /* Enable 256MB aperture */ - reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC); - reg8 &= ~0x06; - reg8 |= 0x02; - pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8); + pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02); } static void start_peg2_link_training(const pci_devfn_t dev) diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 71ca1e6..c6b5a12 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -59,8 +59,7 @@ printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Mini-HD configuration */ reg32 = read32(base + 0x100c); -- To view, visit https://review.coreboot.org/c/coreboot/+/42153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99379299f7e744a3e906bdbc46d55060d9c75d6a Gerrit-Change-Number: 42153 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: arch/x86/bootblock_ctr0.S: Export bootblock_protected_mode_entry
by Raul Rangel (Code Review) 09 Jun '20

09 Jun '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42210 ) Change subject: arch/x86/bootblock_ctr0.S: Export bootblock_protected_mode_entry ...................................................................... arch/x86/bootblock_ctr0.S: Export bootblock_protected_mode_entry Picasso will use this as the entry point when resuming from S3. BUG=b:147042464 TEST=Boot trembyle using patch train and see reboot Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ibbfa8deb99c69e59827a6c028ce4c63f74302da3 --- M src/arch/x86/bootblock_crt0.S 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/42210/1 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 9f45413..e2f42e6 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -10,6 +10,8 @@ #include <cpu/x86/cr.h> +.global bootblock_protected_mode_entry + .section .text /* -- To view, visit https://review.coreboot.org/c/coreboot/+/42210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbfa8deb99c69e59827a6c028ce4c63f74302da3 Gerrit-Change-Number: 42210 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/amd/picasso/bootblock: Clear BSS
by Raul Rangel (Code Review) 09 Jun '20

09 Jun '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42208 ) Change subject: soc/amd/picasso/bootblock: Clear BSS ...................................................................... soc/amd/picasso/bootblock: Clear BSS The PSP does not currently reload bootblock on S3 resume. This means the memory retains the previous values from the run. We need to clear bss to avoid sharing state from the last run. BUG=b:147042464 TEST=Verified staic variables are 0 on S3 resume. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I6071600b14e9edb7b09510b595e9380ae8957d9f --- M src/soc/amd/picasso/bootblock/pre_c.S 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/42208/1 diff --git a/src/soc/amd/picasso/bootblock/pre_c.S b/src/soc/amd/picasso/bootblock/pre_c.S index 5c186f1..da9ecb9 100644 --- a/src/soc/amd/picasso/bootblock/pre_c.S +++ b/src/soc/amd/picasso/bootblock/pre_c.S @@ -18,6 +18,15 @@ and $0xfffffff0, %esp sub $8, %esp + /* clear .bss section since it is not cleared on S3 resume. */ + cld + xor %eax, %eax + movl $(_ebss), %ecx + movl $(_bss), %edi + sub %edi, %ecx + shrl $2, %ecx + rep stosl + movd %mm2, %eax pushl %eax /* tsc[63:32] */ movd %mm1, %eax -- To view, visit https://review.coreboot.org/c/coreboot/+/42208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6071600b14e9edb7b09510b595e9380ae8957d9f Gerrit-Change-Number: 42208 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Increase heap size
by Duncan Laurie (Code Review) 09 Jun '20

09 Jun '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42211 ) Change subject: soc/intel/tigerlake: Increase heap size ...................................................................... soc/intel/tigerlake: Increase heap size With SoundWire and USB4 enabled some boards are running out of memory with all of the ACPI devices and properties. Increase the heap size to accommodate. BUG=b:147462631 TEST=Successfully boot on volteer SKU5 board with SoundWire enabled, before boot was failing with "Error! memalign: Out of memory" Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I0245bdfad93b381871514578e66640e7fe6fa5c4 --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/42211/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index fbf56b4..92bba250 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -97,7 +97,7 @@ config HEAP_SIZE hex - default 0x8000 + default 0x10000 config MAX_ROOT_PORTS int -- To view, visit https://review.coreboot.org/c/coreboot/+/42211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0245bdfad93b381871514578e66640e7fe6fa5c4 Gerrit-Change-Number: 42211 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Add symbols for CAR MTRRs in linker script
by Aaron Durbin (Code Review) 09 Jun '20

09 Jun '20

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30872 ) Change subject: arch/x86: Add symbols for CAR MTRRs in linker script ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/c/coreboot/+/30872/7/src/arch/x86/car.ld File src/arch/x86/car.ld: https://review.coreboot.org/c/coreboot/+/30872/7/src/arch/x86/car.ld@3 PS7, Line 3: #include <cpu/x86/mtrr.h> What did we need this #include for again? LOG2CEIL is a linker thing. https://review.coreboot.org/c/coreboot/+/30872/7/src/arch/x86/car.ld@7 PS7, Line 7: _car_mtrr_start Why wouldn't you just set this symbol to _car_region_start and group the newly added symbols in one hunk with the guard? -- To view, visit https://review.coreboot.org/c/coreboot/+/30872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa Gerrit-Change-Number: 30872 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Jun 2020 16:22:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Add symbols for CAR MTRRs in linker script
by Aaron Durbin (Code Review) 09 Jun '20

09 Jun '20

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30872 ) Change subject: arch/x86: Add symbols for CAR MTRRs in linker script ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/30872/5/src/arch/x86/car.ld File src/arch/x86/car.ld: https://review.coreboot.org/c/coreboot/+/30872/5/src/arch/x86/car.ld@90 PS5, Line 90: _xip_mtrr_mask = ~(MAX(4096, _xip_program_sz_log2) - 1); > The references are in couple cache_as_ram.S files and I don't have a single good guard ready at hand. It would be either new Kconfig or logical or of selected CPU_INTEL_SLOT_x and CPU_INTEL_SOCKET_x. > > Would you accept _booblock_mtrr_mask exposed unconditionally? The xip symbols are conditional on !CONFIG(NO_XIP_EARLY_STAGES). They shouldn't be unconditionally exposed. I wouldn't be opposed to a Kconfig indicating 'expose symbols for MTRR init' because it'd be easy for auditing purposes, and it'd be explicit about intention of relying on these symbols. -- To view, visit https://review.coreboot.org/c/coreboot/+/30872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa Gerrit-Change-Number: 30872 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Jun 2020 16:18:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: Add support for call method
by Tim Wawrzynczak (Code Review) 09 Jun '20

09 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41620 ) Change subject: acpi: Add support for call method ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/41620/11/src/acpi/acpigen.c File src/acpi/acpigen.c: https://review.coreboot.org/c/coreboot/+/41620/11/src/acpi/acpigen.c@1970 PS11, Line 1970: int > unsigned int only if params_len is unsigned, otherwise you've got signed/unsigned comparisons -- To view, visit https://review.coreboot.org/c/coreboot/+/41620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcb67bd756dc8ae1dfd2d40020c273325583df0f Gerrit-Change-Number: 41620 Gerrit-PatchSet: 11 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Jun 2020 15:57:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] cpu/x86/smm: Enable SMM support for Xeon-SP
by Rocky Phagura (Code Review) 09 Jun '20

09 Jun '20

Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41829 ) Change subject: [WIP] cpu/x86/smm: Enable SMM support for Xeon-SP ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/c/coreboot/+/41829/3/src/cpu/x86/smm/smm_module… File src/cpu/x86/smm/smm_module_loader.c: https://review.coreboot.org/c/coreboot/+/41829/3/src/cpu/x86/smm/smm_module… PS3, Line 96: > When building these segments the algorithm needs to account for the SMM save state size and location […] Yes, that's exactly what I have done is tiled the CPU threads. AS for the txt smm descriptor it is included in params->params->per_cpu_save_state_size. So if STM config option is enabled then that params->per_cpu_save_state_size will be updated in mp_init.c, fill_mp_state(). Then this value will get passed eventually to smm_load_module and then to this method smm_create_map. So overall the cpu state save area here should be properly reflected and assigned. Are you seeing any boot/runtime issues with state save after porting to these changes? Line 113 below is the where the calculation is done to include state save area (ss_size). https://review.coreboot.org/c/coreboot/+/41829/3/src/cpu/x86/smm/smm_module… PS3, Line 573: fxsave_area -= total_stack_size + fxsave_size; > This calculation can place the location of the fxsave_area below the bottom of the TSEG. […] This is a bug in my code. Good catch. I will fix the issue and resubmit. -- To view, visit https://review.coreboot.org/c/coreboot/+/41829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78bd74c11ca42fb430f63711b5ec87d4bfe6ca2a Gerrit-Change-Number: 41829 Gerrit-PatchSet: 3 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Eugene Myers <cedarhouse(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki.2011(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ron Minnich <rminnich(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Jun 2020 14:50:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-MessageType: comment

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coreboot-gerrit June 2020