coreboot-gerrit June 2020

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Change in coreboot[master]: mb/google/volteer: Change PCH VR settings for better Sx power savings
by Venkata Krishna Nimmagadda (Code Review) 10 Jun '20

10 Jun '20

Venkata Krishna Nimmagadda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42236 ) Change subject: mb/google/volteer: Change PCH VR settings for better Sx power savings ...................................................................... mb/google/volteer: Change PCH VR settings for better Sx power savings For Tigerlake platforms, this patch set optimized values for PCH external VR settings and ext rail voltage/current, to achieve better power savings in sleep states. BUG=None BRANCH=None TEST=Build and boot volteer and check VR settings with debugger. Change-Id: Ib46423872c956af9aaa92902fce552d5447237c4 Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda(a)intel.com> Change-Id: Ief6194ec8109b6020056cb9e310a3b6519bc8424 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/42236/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index a55ef7d..fdf44fa 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -244,6 +244,29 @@ }, }" + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_S0i1_S0i2 | + FIVR_ENABLE_S0i3 | + FIVR_ENABLE_S3 | + FIVR_ENABLE_S4 | + FIVR_ENABLE_S5, + .vnn_enable_bitmap = FIVR_ENABLE_S0i1_S0i2 | + FIVR_ENABLE_S0i3 | + FIVR_ENABLE_S3 | + FIVR_ENABLE_S4 | + FIVR_ENABLE_S5, + + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" + device domain 0 on #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y -- To view, visit https://review.coreboot.org/c/coreboot/+/42236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief6194ec8109b6020056cb9e310a3b6519bc8424 Gerrit-Change-Number: 42236 Gerrit-PatchSet: 1 Gerrit-Owner: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/acpi/sb_fch: mark _CRS methods as Serialized
by Felix Held (Code Review) 10 Jun '20

10 Jun '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42207 ) Change subject: soc/amd/picasso/acpi/sb_fch: mark _CRS methods as Serialized ...................................................................... soc/amd/picasso/acpi/sb_fch: mark _CRS methods as Serialized ACPI objects are created inside these methods, so they need to be serialized. TEST=iasl stops complaining about those methods not being serialized Change-Id: Ic43fcaed5a8b19dbd5634c17f34a159803ba8577 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/acpi/sb_fch.asl 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/42207/1 diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index a7f60c2..3dccaf5 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -26,7 +26,7 @@ Name (_UID, 0) Name (_DDN, GPIO_DEVICE_DESC) - Method (_CRS, 0) { + Method (_CRS, 0, Serialized) { Name (RBUF, ResourceTemplate() { Interrupt ( ResourceConsumer, @@ -61,7 +61,7 @@ { Name (_HID, "AMDI0040") Name (_UID, 0x0) - Method (_CRS, 0) { + Method (_CRS, 0, Serialized) { Name (RBUF, ResourceTemplate() { Interrupt ( ResourceConsumer, @@ -96,7 +96,7 @@ { Name (_HID, "AMD0020") Name (_UID, 0x0) - Method (_CRS, 0) { + Method (_CRS, 0, Serialized) { Name (RBUF, ResourceTemplate() { Interrupt ( ResourceConsumer, @@ -132,7 +132,7 @@ Device (FUR1) { Name (_HID, "AMD0020") Name (_UID, 0x1) - Method (_CRS, 0) { + Method (_CRS, 0, Serialized) { Name (RBUF, ResourceTemplate() { Interrupt ( ResourceConsumer, @@ -168,7 +168,7 @@ Device (FUR2) { Name (_HID, "AMD0020") Name (_UID, 0x2) - Method (_CRS, 0) { + Method (_CRS, 0, Serialized) { Name (RBUF, ResourceTemplate() { Interrupt ( ResourceConsumer, @@ -204,7 +204,7 @@ Device (FUR3) { Name (_HID, "AMD0020") Name (_UID, 0x3) - Method (_CRS, 0) { + Method (_CRS, 0, Serialized) { Name (RBUF, ResourceTemplate() { Interrupt ( ResourceConsumer, @@ -240,7 +240,7 @@ Device (I2C2) { Name (_HID, "AMD0010") Name (_UID, 0x2) - Method (_CRS, 0) { + Method (_CRS, 0, Serialized) { Name (RBUF, ResourceTemplate() { Interrupt ( ResourceConsumer, @@ -275,7 +275,7 @@ { Name (_HID, "AMD0010") Name (_UID, 0x3) - Method (_CRS, 0) { + Method (_CRS, 0, Serialized) { Name (RBUF, ResourceTemplate() { Interrupt ( ResourceConsumer, @@ -308,7 +308,7 @@ Device (I2C4) { Name (_HID, "AMD0010") Name (_UID, 0x4) - Method (_CRS, 0) { + Method (_CRS, 0, Serialized) { Name (RBUF, ResourceTemplate() { Interrupt ( ResourceConsumer, -- To view, visit https://review.coreboot.org/c/coreboot/+/42207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic43fcaed5a8b19dbd5634c17f34a159803ba8577 Gerrit-Change-Number: 42207 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/mipi_camera: Support for adding camera power resource
by Tim Wawrzynczak (Code Review) 10 Jun '20

10 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41624 ) Change subject: drivers/intel/mipi_camera: Support for adding camera power resource ...................................................................... Patch Set 12: (11 comments) https://review.coreboot.org/c/coreboot/+/41624/12/src/drivers/intel/mipi_ca… File src/drivers/intel/mipi_camera/camera.c: https://review.coreboot.org/c/coreboot/+/41624/12/src/drivers/intel/mipi_ca… PS12, Line 437: method_params[0] = config->clk_panel.clks[index].clknum; : method_params[1] = config->clk_panel.clks[index].freq; : acpigen_call_method("MCON", method_params, 2); This is why I don't particularly like acpigen_call_method(), because I don't find this any easier to read (and I'd argue less readable) than: acpigen_emit_namestring("MCON"); acpigen_write_integer(config->clk_panel.clks[index].clknum); acpigen_write_integer(config->clk_panel.clks[]index].freq); https://review.coreboot.org/c/coreboot/+/41624/12/src/drivers/intel/mipi_ca… PS12, Line 512: (config->pr0 This should check for again NULL and supply a default. Or is a custom name always required? https://review.coreboot.org/c/coreboot/+/41624/12/src/drivers/intel/mipi_ca… PS12, Line 513: acpigen_write_name_integer("STA", 0); : acpigen_write_STA_ext("STA"); : : acpigen_write_method_serialized("_ON", 0); : acpigen_write_if(); : acpigen_emit_byte(LEQUAL_OP); : acpigen_emit_namestring("STA"); : acpigen_write_integer(0); : : add_power_resource(config, &config->on_seq); : : acpigen_write_store_op_to_namestr(1, "STA"); : acpigen_pop_len(); /* if */ : acpigen_pop_len(); /* _ON */ : : /* _OFF operations */ : acpigen_write_method_serialized("_OFF", 0); : acpigen_write_if(); : acpigen_emit_byte(LEQUAL_OP); : acpigen_emit_namestring("STA"); : acpigen_write_integer(1); : : add_power_resource(config, &config->off_seq); : : acpigen_write_store_op_to_namestr(0, "STA"); Why is the extra "STA" "variable" necessary? The OS should only call _ON and _OFF as appropriate, I don't think you need to guard against the OS calling it multiple times per suspend or resume. https://review.coreboot.org/c/coreboot/+/41624/12/src/drivers/intel/mipi_ca… PS12, Line 599: acpigen_write_name("_DEP"); : acpigen_write_package(1); : acpigen_emit_namestring(config->dep); : acpigen_pop_len(); I still don't understand this. The ACPI spec says this about _DEP: _DEP evaluates to a package and designates device objects that OSPM should assign a higher priority in start ordering due to future operation region accesses. What operation region is being accessed from 2 places ? https://review.coreboot.org/c/coreboot/+/41624/12/src/drivers/intel/mipi_ca… File src/drivers/intel/mipi_camera/chip.h: https://review.coreboot.org/c/coreboot/+/41624/12/src/drivers/intel/mipi_ca… PS12, Line 69: clk_ct there could be a better name here, I'm not sure what the 'ct' refers to. maybe clk_config? https://review.coreboot.org/c/coreboot/+/41624/12/src/drivers/intel/mipi_ca… PS12, Line 81: 2 symbolic constant please https://review.coreboot.org/c/coreboot/+/41624/12/src/drivers/intel/mipi_ca… PS12, Line 84: gp_ctrl_panel gpio_... ? https://review.coreboot.org/c/coreboot/+/41624/12/src/drivers/intel/mipi_ca… PS12, Line 85: 4 symbolic constant please https://review.coreboot.org/c/coreboot/+/41624/12/src/drivers/intel/mipi_ca… PS12, Line 85: struct gp_ct gps[4]; is the struct for gp_ct necessary? could just have uint8_t gpios[4]. https://review.coreboot.org/c/coreboot/+/41624/12/src/drivers/intel/mipi_ca… PS12, Line 90: index what is the index for? Doesn't their relative order in operation_seq define the order they're applied in? https://review.coreboot.org/c/coreboot/+/41624/12/src/drivers/intel/mipi_ca… PS12, Line 97: delay_ms should specify (in a comment or in the name) if it is pre- or post-op delay -- To view, visit https://review.coreboot.org/c/coreboot/+/41624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e Gerrit-Change-Number: 41624 Gerrit-PatchSet: 12 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Jun 2020 22:13:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: move volteer-specific GPIOs to variant gpio.c
by Nick Vaccaro (Code Review) 09 Jun '20

09 Jun '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41797 ) Change subject: mb/google/volteer: move volteer-specific GPIOs to variant gpio.c ...................................................................... mb/google/volteer: move volteer-specific GPIOs to variant gpio.c Move the GPIOs that are likely to be volteer-specific (mostly peripherals) to reside in variants/volteer/gpio.c so that variants don't have to override too many GPIO settings. BUG=b:157597158 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer SKU4 to kernel. Change-Id: Ib2f384f539d55a3a8d4a7608336ef22aca3d8c4f Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/gpio.c A src/mainboard/google/volteer/variants/volteer/gpio.c 2 files changed, 412 insertions(+), 191 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/41797/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 3290f44..29f4a92 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -19,20 +19,20 @@ /* A4 : ESPI_CS# ==> ESPI_CS_L */ /* A5 : ESPI_CLK ==> ESPI_CLK */ /* A6 : ESPI_RESET# ==> NC(TP764) */ - /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ - PAD_CFG_GPO(GPP_A7, 1, DEEP), - /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A7 : I2S2_SCLK ==> NC */ + PAD_NC(GPP_A7, NONE), + /* A8 : I2S2_SFRM ==> NC */ + PAD_NC(GPP_A8, NONE), /* A9 : I2S2_TXD ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_A9, NONE, DEEP), - /* A10 : I2S2_RXD ==> EN_SPKR_PA */ - PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A10 : I2S2_RXD ==> NC */ + PAD_NC(GPP_A10, NONE), /* A11 : PMC_I2C_SDA ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_A11, 1, DEEP), /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), - /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ - PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> NC */ + PAD_NC(GPP_A13, NONE), /* A14 : USB_OC1# ==> USB_A0_OC_ODL */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* A15 : USB_OC2# ==> USB_A1_OC_ODL */ @@ -41,18 +41,18 @@ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), - /* A18 : DDSP_HPDB ==> HDMI_HPD */ - PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> NC */ + PAD_NC(GPP_A18, NONE), /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), - /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_A21, 1, DEEP), - /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ - PAD_CFG_GPO(GPP_A22, 1, DEEP), - /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ - PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : I2S1_SCLK ==> NC */ + PAD_NC(GPP_A23, NONE), /* B0 : CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), @@ -60,22 +60,22 @@ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* B2 : VRALERT# ==> VRALERT_L */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), - /* B3 : CPU_GP2 ==> PEN_DET_ODL */ - PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B3 : CPU_GP2 ==> NC */ + PAD_NC(GPP_B3, NONE), /* B4 : CPU_GP3 ==> NC */ PAD_NC(GPP_B4, NONE), - /* B5 : ISH_I2C0_CVF_SDA */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - /* B6 : ISH_I2C0_CVF_SCL */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), - /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), - /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), - /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B5 : NC */ + PAD_NC(GPP_B5, NONE), + /* B6 : NC */ + PAD_NC(GPP_B6, NONE), + /* B7 : ISH_12C1_SDA ==> NC */ + PAD_NC(GPP_B7, NONE), + /* B8 : ISH_I2C1_SCL ==> NC */ + PAD_NC(GPP_B8, NONE), + /* B9 : I2C5_SDA ==> NC */ + PAD_NC(GPP_B9, NONE), + /* B10 : I2C5_SCL ==> NC */ + PAD_NC(GPP_B10, NONE), /* B11 : PMCALERT# ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), /* B12 : SLP_S0# ==> SLP_S0_L */ @@ -92,19 +92,19 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ - PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), - /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ - PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), - /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ - PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> NC */ + PAD_NC(GPP_B19, NONE), + /* B20 : GSPI1_CLK ==> NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : GSPI1_MISO ==> NC */ + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> PCH_GSPI1_GPMCU_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ PAD_NC(GPP_B23, NONE), - /* C0 : SMBCLK ==> EN_PP3300_WLAN */ - PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C0 : SMBCLK ==> NC */ + PAD_NC(GPP_C0, NONE), /* C1 : SMBDATA ==> NOT USED */ PAD_NC(GPP_C1, NONE), /* C2 : SMBALERT# ==> GPP_C2_STRAP */ @@ -129,48 +129,47 @@ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* C12 : UART1_RXD ==> MEM_STRAP_0 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), - /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ - PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C13 : UART1_TXD ==> NC */ + PAD_NC(GPP_C13, NONE), /* C14 : UART1_RTS# ==> MEM_STRAP_2 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* C15 : UART1_CTS# ==> MEM_STRAP_1 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), - /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* C20 : UART2_RXD ==> FPMCU_INT_L */ - /* APIC interrupt conflict, so used GPI_INT; see b/147500717 */ - PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C16 : I2C0_SDA ==> NC */ + PAD_NC(GPP_C16, NONE), + /* C17 : I2C0_SCL ==> NC */ + PAD_NC(GPP_C17, NONE), + /* C18 : I2C1_SDA ==> NC */ + PAD_NC(GPP_C18, NONE), + /* C19 : I2C1_SCL ==> NC */ + PAD_NC(GPP_C19, NONE), + /* C20 : UART2_RXD ==> NC */ + PAD_NC(GPP_C20, NONE), /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ - PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* C22 : UART2_RTS# ==> NC */ + PAD_NC(GPP_C22, NONE), + /* C23 : UART2_CTS# ==> NC */ + PAD_NC(GPP_C23, NONE), - /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + /* D0 : ISH_GP0 ==> NC */ PAD_NC(GPP_D0, NONE), - /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ - PAD_CFG_GPI(GPP_D1, NONE, DEEP), - /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ - PAD_CFG_GPI(GPP_D2, NONE, DEEP), - /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */ - PAD_CFG_GPI(GPP_D3, NONE, DEEP), - /* D4 : IMGCLKOUT0 ==> FCAM_RST_L */ - PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC(GPP_D1, NONE), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC(GPP_D2, NONE), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D4 : IMGCLKOUT0 ==> NC */ + PAD_NC(GPP_D4, NONE), /* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), - /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), - /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */ + /* D6 : SRCCLKREQ1# ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), - /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> PCH_GSPI2_CVF_CS_L */ PAD_CFG_NF(GPP_D9, NONE, DEEP, NF7), /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ @@ -179,27 +178,27 @@ PAD_CFG_NF(GPP_D11, NONE, DEEP, NF7), /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), - /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ - PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), - /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ - PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : ISH_UART0_TXD ==> NC */ + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> MEM_STRAP_3 */ PAD_CFG_GPI(GPP_D15, NONE, DEEP), - /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), - /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ - PAD_CFG_GPO(GPP_D17, 1, DEEP), - /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */ - PAD_CFG_GPO(GPP_D18, 1, DEEP), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC(GPP_D16, NONE), + /* D17 : ISH_GP4 ==> NC */ + PAD_NC(GPP_D17, NONE), + /* D18 : ISH_GP5 ==> NC */ + PAD_NC(GPP_D18, NONE), /* D19 : I2S_MCLK1 ==> I2S_MCLK1 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* E0 : SATAXPCIE0 ==> USB_A1_RT_RST_ODL */ PAD_CFG_GPO(GPP_E0, 1, DEEP), - /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), - /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E1 : SPI1_IO2 ==> NC */ + PAD_NC(GPP_E1, NONE), + /* E2 : SPI1_IO3 ==> NC */ + PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> USI_REPORT_EN */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ @@ -216,20 +215,20 @@ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF6), - /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ - PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E11 : SPI1_CLK ==> NC */ + PAD_NC(GPP_E11, NONE), /* E12 : SPI1_MISO_IO1 ==> NOT USED */ PAD_NC(GPP_E12, NONE), /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF6), /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), - /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */ - PAD_CFG_GPI(GPP_E16, NONE, DEEP), - /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ - PAD_CFG_GPO(GPP_E17, 1, DEEP), + /* E15 : ISH_GP6 ==> NC */ + PAD_NC(GPP_E15, NONE), + /* E16 : ISH_GP7 ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> NC */ + PAD_NC(GPP_E17, NONE), /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ @@ -255,32 +254,32 @@ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), - /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ - PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), /* F7 : GPPF7_STRAP */ PAD_NC(GPP_F7, NONE), - /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ - PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F8 : I2S_MCLK2_INOUT ==> NC */ + PAD_NC(GPP_F8, NONE), /* F9 : Reserved ==> NC */ PAD_NC(GPP_F9, NONE), /* F10 : GPPF10_STRAP */ PAD_NC(GPP_F10, DN_20K), - /* F12 : GSXDOUT ==> WWAN_RST_ODL */ - PAD_CFG_GPI(GPP_F12, NONE, DEEP), - /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ - PAD_CFG_GPO(GPP_F13, 1, DEEP), - /* F14 : GSXDIN ==> SAR0_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), - /* F15 : GSXSRESET# ==> RCAM_RST_L */ - PAD_CFG_GPO(GPP_F15, 1, DEEP), - /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ - PAD_CFG_GPO(GPP_F16, 1, DEEP), - /* F17 : WWAN_RF_DISABLE_ODL */ - PAD_CFG_GPO(GPP_F17, 1, DEEP), - /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), - /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + /* F12 : GSXDOUT ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GSXDOUT ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : GSXDIN ==> NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : GSXCLK ==> NC */ + PAD_NC(GPP_F16, NONE), + /* F17 : NC */ + PAD_NC(GPP_F17, NONE), + /* F18 : THC1_SPI2_INT# ==> NC */ + PAD_NC(GPP_F18, NONE), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), /* F20 : EXT_PWR_GATE# ==> EXT_PWR_GATE_L */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* F21 : EXT_PWR_GATE2# ==> EXT_PWR_GATE2_L */ @@ -296,82 +295,82 @@ PAD_NC(GPP_H1, NONE), /* H2 : GPPH2_BOOT_STRAP3 */ PAD_NC(GPP_H2, NONE), - /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ - PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H3 : SX_EXIT_HOLDOFF# ==> NC */ + PAD_NC(GPP_H3, NONE), /* H4 : I2C2_SDA ==> PCH_I2C2_MISC_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : I2C2_SCL ==> PCH_I2C2_MISC_SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), - /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H6 : I2C3_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : I2C3_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), /* H10 : SRCCLKREQ4# ==> USB_C1_RT_FORCE_PWR */ PAD_CFG_GPO(GPP_H10, 1, DEEP), - /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ - PAD_CFG_GPO(GPP_H11, 1, DEEP), - /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */ - PAD_CFG_GPI(GPP_H12, NONE, DEEP), - /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ - PAD_CFG_GPI(GPP_H13, NONE, DEEP), - /* H14 : M2_SKT2_CFG2 # ==> RCAM_SNRPWR_EN */ - PAD_CFG_GPO(GPP_H14, 1, DEEP), - /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ - PAD_CFG_GPI(GPP_H15, NONE, DEEP), - /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ - PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), - /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ - PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H11 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H11, NONE), + /* H12 : M2_SKT2_CFG0 ==> NONE */ + PAD_NC(GPP_H12, NONE), + /* H13 : M2_SKT2_CFG1 # ==> NONE */ + PAD_NC(GPP_H13, NONE), + /* H14 : M2_SKT2_CFG2 # ==> NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : M2_SKT2_CFG3 # ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H16 : DDPB_CTRLCLK ==> NC */ + PAD_NC(GPP_H16, NONE), + /* H17 : DDPB_CTRLDATA ==> NC */ + PAD_NC(GPP_H17, NONE), /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE_L */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), - /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ - PAD_CFG_GPI(GPP_H19, NONE, DEEP), - /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */ - PAD_CFG_GPO(GPP_H20, 1, DEEP), - /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ - PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), - /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ - PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), - /* H23 : IMGCLKOUT4 ==> WWAN_ESIM_SEL_ODL */ - PAD_CFG_GPO(GPP_H23, 1, DEEP), + /* H19 : TIME_SYNC0 ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : IMGCLKOUT1 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : IMGCLKOUT4 ==> NC */ + PAD_NC(GPP_H23, NONE), - /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ - PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), - /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ - PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), - /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ - PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), - /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ - PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R0 : HDA_BCLK ==> NC */ + PAD_NC(GPP_R0, NONE), + /* R1 : HDA_SYNC ==> NC */ + PAD_NC(GPP_R1, NONE), + /* R2 : HDA_SDO ==> NC */ + PAD_NC(GPP_R2, NONE), + /* R3 : HDA_SDIO ==> NC */ + PAD_NC(GPP_R3, NONE), /* R4 : HDA_RST# ==> HDA_RST_L */ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), - /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), - /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), - /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : I2S1_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S1_SFRM ==> NC */ + PAD_NC(GPP_R7, NONE), - /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), - /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), - /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), - /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), - /* S4 : SNDW2_CLK ==> DMIC_CLK1 */ - PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), - /* S5 : SNDW2_DATA ==> DMIC_DATA1 */ - PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), - /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ - PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), - /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ - PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + /* S0 : SNDW0_CLK ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : SNDW0_DATA ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S2 : SNDW1_CLK ==> NC */ + PAD_NC(GPP_S2, NONE), + /* S3 : SNDW1_DATA ==> NC */ + PAD_NC(GPP_S3, NONE), + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), /* GPD0: BATLOW# ==> BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -391,11 +390,12 @@ PAD_CFG_GPI(GPD7, DN_20K, DEEP), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), - /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ - PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD9: SLP_WLAN# ==> NC */ + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> SLP_S5_L */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* GPD11: LANPHYC ==> NC */ + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -421,28 +421,14 @@ /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C0 : SMBCLK ==> EN_PP3300_WLAN */ - PAD_CFG_GPO(GPP_C0, 1, DEEP), - /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ - PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ PAD_CFG_GPO(GPP_E12, 1, DEEP), /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_F11, 1, DEEP), - - /* F12 : GSXDOUT ==> WWAN_RST_ODL - To meet timing constrains - drive reset low. - Deasserted in ramstage. */ - PAD_CFG_GPO(GPP_F12, 0, DEEP), - - /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ - PAD_CFG_GPO(GPP_H11, 1, DEEP), }; const struct pad_config *__weak variant_base_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/volteer/gpio.c b/src/mainboard/google/volteer/variants/volteer/gpio.c new file mode 100644 index 0000000..37ae1f3 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/gpio.c @@ -0,0 +1,235 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { + /* A0 thru A6 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_CLK ==> ESPI_CLK */ + /* A6 : ESPI_RESET# ==> NC(TP764) */ + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B3 : CPU_GP2 ==> PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B5 : ISH_I2C0_CVF_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : ISH_I2C0_CVF_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + /* APIC interrupt conflict, so used GPI_INT; see b/147500717 */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */ + PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* D4 : IMGCLKOUT0 ==> FCAM_RST_L */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */ + PAD_CFG_GPO(GPP_D18, 1, DEEP), + + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E17, 1, DEEP), + + /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F12 : GSXDOUT ==> WWAN_RST_ODL */ + PAD_CFG_GPI(GPP_F12, NONE, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F14 : GSXDIN ==> SAR0_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + /* F15 : GSXSRESET# ==> RCAM_RST_L */ + PAD_CFG_GPO(GPP_F15, 1, DEEP), + /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_F17, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H14 : M2_SKT2_CFG2 # ==> RCAM_SNRPWR_EN */ + PAD_CFG_GPO(GPP_H14, 1, DEEP), + /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ + PAD_CFG_GPI(GPP_H15, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), + /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* H23 : IMGCLKOUT4 ==> WWAN_ESIM_SEL_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S4 : SNDW2_CLK ==> DMIC_CLK1 */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* S5 : SNDW2_DATA ==> DMIC_DATA1 */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* F12 : GSXDOUT ==> WWAN_RST_ODL + To meet timing constrains - drive reset low. + Deasserted in ramstage. */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2f384f539d55a3a8d4a7608336ef22aca3d8c4f Gerrit-Change-Number: 41797 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters
by Jonathan Zhang (Code Review) 09 Jun '20

09 Jun '20

Hello Philipp Deppenwiese, build bot (Jenkins), Anjaneya "Reddy" Chagam, Johnny Lin, Jingle Hsu, Morgan Jang, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40385 to look at the new patch set (#24). Change subject: soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters ...................................................................... soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters Configure FSP-M UPD parameters. TESTED=Boot CPX-SP based server. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: I2d0762a742d8803c7396034e3244120c1e8ece67 --- M src/soc/intel/xeon_sp/cpx/romstage.c 1 file changed, 54 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/40385/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/40385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d0762a742d8803c7396034e3244120c1e8ece67 Gerrit-Change-Number: 40385 Gerrit-PatchSet: 24 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] cpu/x86/smm: Enable SMM support for Xeon-SP
by Eugene Myers (Code Review) 09 Jun '20

09 Jun '20

Eugene Myers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41829 ) Change subject: [WIP] cpu/x86/smm: Enable SMM support for Xeon-SP ...................................................................... Patch Set 4: (2 comments) This change is ready for review. https://review.coreboot.org/c/coreboot/+/41829/3/src/cpu/x86/mp_init.c File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/41829/3/src/cpu/x86/mp_init.c@758 PS3, Line 758: mp_state.perm_smbase, For the STM to be properly setup in this method, the above line (758) needs to be changed to 'perm_smbase' (which should be the same as the third parameter) https://review.coreboot.org/c/coreboot/+/41829/3/src/cpu/x86/smm/smm_module… File src/cpu/x86/smm/smm_module_loader.c: https://review.coreboot.org/c/coreboot/+/41829/3/src/cpu/x86/smm/smm_module… PS3, Line 96: > Yes, that's exactly what I have done is tiled the CPU threads. […] Thanks, maybe you could clarify what is happening in your comments and diagrams. Two issues (not sure that they are related). (1) Looks like a min number segments needed = 0 might be a problem. Haven't traced it out. smm_create_map: cpus in one segment 6 smm_create_map: min # of segments needed 0 (2) The second issue I resolved myself when I went back and realized what was really changed. The STM issue was that the EIP for the SMI hander was incorrect because of the change in how the SMI handler is started. The STM is setup to start the SMI handler in step #2.5 - .5 because the STM starts the handler in 32-bit mode, so the start is at an offset where the 32-bit code is. I did this because the STM normally starts the SMI handler in 64-bit mode and the modification for a 32-bit mode start was three line of code. Starting a VM in 16-bit is somewhat more complicated, so I wanted to avoid that. The previous method had all entries going to a single location and then switching to 32-bit mode. Now the suggested patch to mp_init.c fixes that issue and works well on my test machine. -- To view, visit https://review.coreboot.org/c/coreboot/+/41829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78bd74c11ca42fb430f63711b5ec87d4bfe6ca2a Gerrit-Change-Number: 41829 Gerrit-PatchSet: 4 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Eugene Myers <cedarhouse(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki.2011(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ron Minnich <rminnich(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Jun 2020 19:50:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eugene Myers <cedarhouse1(a)comcast.net> Comment-In-Reply-To: Rocky Phagura Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Add symbols for CAR MTRRs in linker script
by Kyösti Mälkki (Code Review) 09 Jun '20

09 Jun '20

Hello build bot (Jenkins), Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30872 to look at the new patch set (#9). Change subject: arch/x86: Add symbols for CAR MTRRs in linker script ...................................................................... arch/x86: Add symbols for CAR MTRRs in linker script This allows to remove references to CONFIG_DCACHE_RAM entries in most cache_as_ram.S files. While Kconfig variable names appear for every stage, linker symbol names will only appear in stages they are valid in. Also, linker scripts have LOG2CEIL which comes in handy to enforce MTRR alignments. Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/30872/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/30872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa Gerrit-Change-Number: 30872 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Add symbols for CAR MTRRs in linker script
by Kyösti Mälkki (Code Review) 09 Jun '20

09 Jun '20

Hello build bot (Jenkins), Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30872 to look at the new patch set (#8). Change subject: arch/x86: Add symbols for CAR MTRRs in linker script ...................................................................... arch/x86: Add symbols for CAR MTRRs in linker script This allows to remove references to CONFIG_DCACHE_RAM entries in most cache_as_ram.S files. While Kconfig variable names appear for every stage, linker symbol names will only appear in stages they are valid in. Also, linker scripts have LOG2CEIL which comes in handy to enforce MTRR alignments. Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/30872/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/30872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa Gerrit-Change-Number: 30872 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMs
by John Zhao (Code Review) 09 Jun '20

09 Jun '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42056 ) Change subject: soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMs ...................................................................... soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMs The Connect Topology Command(CNTP) is sent with default timeout value (0x1388) along with FW CM. The CNTP is supposed to be skipped while using SW CM. While transition from FW CM to SW CM, the default timeout value could cause boot time delay up to ~10 seconds. Set this FSPS UPD ITbtConnectTopologyTimeoutInMs to be 0 in order to avoid the 10 seconds delay. Future FSP release will evaluate this ITbtConnectTopologyTimeoutInMs value. While FSP finds this UPD value being 0, FSP will skip sendig CNTP. BUG=b:155893566 TEST=Built image with SW CM Thunderbolt firmware and verified no outstanding delay time while using FSP v3197 during boot to kernel. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I47e3519fd818cb56e6abd16464d8370ffddabc5b --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/42056/1 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index ed09aaa..e693699 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -238,6 +238,9 @@ */ uint16_t TcssAuxOri; + /* Connect Topology Command timeout value */ + uint16_t ITbtConnectTopologyTimeoutInMs; + /* * Override GPIO PM configuration: * 0: Use FSP default GPIO PM program, diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index bdcd357..b615485 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -114,6 +114,9 @@ for (i = 0; i < 8; i++) params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; + /* Set FSPS UPD ITbtConnectTopologyTimeoutInMs */ + params->ITbtConnectTopologyTimeoutInMs = 0; + /* Chipset Lockdown */ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { params->PchLockDownGlobalSmi = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/42056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47e3519fd818cb56e6abd16464d8370ffddabc5b Gerrit-Change-Number: 42056 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197
by Srinidhi N Kaushik (Code Review) 09 Jun '20

09 Jun '20

Hello John Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42046 to review the following change. Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197 ...................................................................... vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197 Update FSP headers for Tiger Lake platform generated based FSP version 3197 to include below additional UPD: FSPS: ITbtConnectTopologyTimeoutInMs Signed-off-by: John Zhao <john.zhao(a)intel.com> Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I06d605b156c1e6f90921c20e0b8fbbe4d64916ce --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 1 file changed, 39 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/42046/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index a68ba17..8f5e6d0 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -528,7 +528,17 @@ /** Offset 0x04D8 - Reserved **/ - UINT8 Reserved25[11]; + UINT8 Reserved25[2]; + +/** Offset 0x04DA - ITbtConnectTopology Timeout value + ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range + is 0-10000. 100 = 100 ms. +**/ + UINT16 ITbtConnectTopologyTimeoutInMs; + +/** Offset 0x04DC - Reserved +**/ + UINT8 Reserved26[7]; /** Offset 0x04E3 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports @@ -538,7 +548,7 @@ /** Offset 0x04E7 - Reserved **/ - UINT8 Reserved26[194]; + UINT8 Reserved27[194]; /** Offset 0x05A9 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit @@ -549,7 +559,7 @@ /** Offset 0x05AA - Reserved **/ - UINT8 Reserved27[10]; + UINT8 Reserved28[10]; /** Offset 0x05B4 - CpuMpPpi <b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. @@ -560,7 +570,7 @@ /** Offset 0x05B8 - Reserved **/ - UINT8 Reserved28[46]; + UINT8 Reserved29[46]; /** Offset 0x05E6 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -570,7 +580,7 @@ /** Offset 0x05E7 - Reserved **/ - UINT8 Reserved29[36]; + UINT8 Reserved30[36]; /** Offset 0x060B - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -579,7 +589,7 @@ /** Offset 0x060C - Reserved **/ - UINT8 Reserved30[2]; + UINT8 Reserved31[2]; /** Offset 0x060E - Enable PCH ISH SPI pins assigned Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -603,7 +613,7 @@ /** Offset 0x061C - Reserved **/ - UINT8 Reserved31[2]; + UINT8 Reserved32[2]; /** Offset 0x061E - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region @@ -614,7 +624,7 @@ /** Offset 0x061F - Reserved **/ - UINT8 Reserved32[2]; + UINT8 Reserved33[2]; /** Offset 0x0621 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper @@ -625,7 +635,7 @@ /** Offset 0x0622 - Reserved **/ - UINT8 Reserved33[24]; + UINT8 Reserved34[24]; /** Offset 0x063A - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. @@ -634,7 +644,7 @@ /** Offset 0x0652 - Reserved **/ - UINT8 Reserved34[24]; + UINT8 Reserved35[24]; /** Offset 0x066A - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. @@ -648,7 +658,7 @@ /** Offset 0x069A - Reserved **/ - UINT8 Reserved35[168]; + UINT8 Reserved36[168]; /** Offset 0x0742 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. @@ -663,7 +673,7 @@ /** Offset 0x075B - Reserved **/ - UINT8 Reserved36[5]; + UINT8 Reserved37[5]; /** Offset 0x0760 - Touch Host Controller Port 1 Assignment Assign THC Port 1 @@ -673,7 +683,7 @@ /** Offset 0x0761 - Reserved **/ - UINT8 Reserved37[79]; + UINT8 Reserved38[79]; /** Offset 0x07B0 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is @@ -694,7 +704,7 @@ /** Offset 0x07F8 - Reserved **/ - UINT8 Reserved38[79]; + UINT8 Reserved39[79]; /** Offset 0x0847 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. @@ -717,7 +727,7 @@ /** Offset 0x084A - Reserved **/ - UINT8 Reserved39[16]; + UINT8 Reserved40[16]; /** Offset 0x085A - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. @@ -727,7 +737,7 @@ /** Offset 0x085B - Reserved **/ - UINT8 Reserved40[42]; + UINT8 Reserved41[42]; /** Offset 0x0885 - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). @@ -741,7 +751,7 @@ /** Offset 0x0895 - Reserved **/ - UINT8 Reserved41; + UINT8 Reserved42; /** Offset 0x0896 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. @@ -750,7 +760,7 @@ /** Offset 0x08A6 - Reserved **/ - UINT8 Reserved42[72]; + UINT8 Reserved43[72]; /** Offset 0x08EE - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. @@ -764,7 +774,7 @@ /** Offset 0x0908 - Reserved **/ - UINT8 Reserved43[16]; + UINT8 Reserved44[16]; /** Offset 0x0918 - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time @@ -784,7 +794,7 @@ /** Offset 0x091A - Reserved **/ - UINT8 Reserved44[3]; + UINT8 Reserved45[3]; /** Offset 0x091D - Hybrid Storage Detection and Configuration Mode Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. @@ -795,7 +805,7 @@ /** Offset 0x091E - Reserved **/ - UINT8 Reserved45[96]; + UINT8 Reserved46[96]; /** Offset 0x097E - USB2 Port Reset Message Enable 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message @@ -804,7 +814,7 @@ /** Offset 0x098E - Reserved **/ - UINT8 Reserved46[322]; + UINT8 Reserved47[322]; /** Offset 0x0AD0 - RpPtmBytes **/ @@ -812,7 +822,7 @@ /** Offset 0x0AD4 - Reserved **/ - UINT8 Reserved47[101]; + UINT8 Reserved48[101]; /** Offset 0x0B39 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, @@ -830,7 +840,7 @@ /** Offset 0x0B3A - Reserved **/ - UINT8 Reserved48[80]; + UINT8 Reserved49[80]; /** Offset 0x0B8A - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns @@ -840,7 +850,7 @@ /** Offset 0x0B8B - Reserved **/ - UINT8 Reserved49[179]; + UINT8 Reserved50[179]; /** Offset 0x0C3E - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. @@ -862,7 +872,7 @@ /** Offset 0x0C41 - Reserved **/ - UINT8 Reserved50; + UINT8 Reserved51; /** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -876,7 +886,7 @@ /** Offset 0x0CA2 - Reserved **/ - UINT8 Reserved51[269]; + UINT8 Reserved52[269]; /** Offset 0x0DAF - LpmStateEnableMask **/ @@ -884,7 +894,7 @@ /** Offset 0x0DB0 - Reserved **/ - UINT8 Reserved52[232]; + UINT8 Reserved53[232]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -901,7 +911,7 @@ /** Offset 0x0E98 **/ - UINT8 UnusedUpdSpace36[6]; + UINT8 UnusedUpdSpace35[6]; /** Offset 0x0E9E **/ -- To view, visit https://review.coreboot.org/c/coreboot/+/42046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06d605b156c1e6f90921c20e0b8fbbe4d64916ce Gerrit-Change-Number: 42046 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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