coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/sandybridge: Use MCHBAR bitwise ops
by Angel Pons (Code Review) 09 Jun '20

09 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42151 ) Change subject: nb/intel/sandybridge: Use MCHBAR bitwise ops ...................................................................... nb/intel/sandybridge: Use MCHBAR bitwise ops Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: If16d8c4aef3dfd1dbeaf48d6855dd4c0ef328168 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/early_init.c 1 file changed, 5 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42151/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 0c9325d..2ee273c 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -62,7 +62,6 @@ static void sandybridge_setup_graphics(void) { - u32 reg32; u16 reg16; u8 gfxsize; @@ -106,27 +105,18 @@ pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02); /* Erratum workarounds */ - reg32 = MCHBAR32(SAPMCTL); - reg32 |= (1 << 9) | (1 << 10); - MCHBAR32(SAPMCTL) = reg32; + MCHBAR32_OR(SAPMCTL, (1 << 9) | (1 << 10)); /* Enable SA Clock Gating */ - reg32 = MCHBAR32(SAPMCTL); - MCHBAR32(SAPMCTL) = reg32 | 1; + MCHBAR32_OR(SAPMCTL, 1); /* GPU RC6 workaround for sighting 366252 */ - reg32 = MCHBAR32(SSKPD_HI); - reg32 |= (1 << 31); - MCHBAR32(SSKPD_HI) = reg32; + MCHBAR32_OR(SSKPD_HI, 1 << 31); /* VLW (Virtual Legacy Wire?) */ - reg32 = MCHBAR32(0x6120); - reg32 &= ~(1 << 0); - MCHBAR32(0x6120) = reg32; + MCHBAR32_AND(0x6120, ~(1 << 0)); - reg32 = MCHBAR32(INTRDIRCTL); - reg32 |= (1 << 4) | (1 << 5); - MCHBAR32(INTRDIRCTL) = reg32; + MCHBAR32_OR(INTRDIRCTL, (1 << 4) | (1 << 5)); } static void start_peg_link_training(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/42151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If16d8c4aef3dfd1dbeaf48d6855dd4c0ef328168 Gerrit-Change-Number: 42151 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Use PCI bitwise ops
by Angel Pons (Code Review) 09 Jun '20

09 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42150 ) Change subject: nb/intel/sandybridge: Use PCI bitwise ops ...................................................................... nb/intel/sandybridge: Use PCI bitwise ops Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: If7f3f06cd3524790b0ec96121ed0353c89eac595 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/romstage.c 3 files changed, 15 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/42150/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 59f0504..0c9325d 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -64,7 +64,7 @@ { u32 reg32; u16 reg16; - u8 reg8, gfxsize; + u8 gfxsize; reg16 = pci_read_config16(PCI_DEV(0, 2, 0), PCI_DEVICE_ID); switch (reg16) { @@ -103,10 +103,7 @@ pci_write_config16(HOST_BRIDGE, GGC, reg16); /* Enable 256MB aperture */ - reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC); - reg8 &= ~0x06; - reg8 |= 0x02; - pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8); + pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02); /* Erratum workarounds */ reg32 = MCHBAR32(SAPMCTL); @@ -134,7 +131,7 @@ static void start_peg_link_training(void) { - u32 tmp, deven; + u32 deven; const u16 base_rev = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID) & BASE_REV_MASK; /* @@ -150,31 +147,22 @@ * For each PEG device, set bit 5 to use three retries for OC (Offset Calibration). * We also clear DEFER_OC (bit 16) in order to start PEG training. */ - if (deven & DEVEN_PEG10) { - tmp = pci_read_config32(PCI_DEV(0, 1, 0), AFE_PWRON) & ~(1 << 16); - pci_write_config32(PCI_DEV(0, 1, 0), AFE_PWRON, tmp | (1 << 5)); - } + if (deven & DEVEN_PEG10) + pci_update_config32(PCI_DEV(0, 1, 0), AFE_PWRON, ~(1 << 16), 1 << 5); - if (deven & DEVEN_PEG11) { - tmp = pci_read_config32(PCI_DEV(0, 1, 1), AFE_PWRON) & ~(1 << 16); - pci_write_config32(PCI_DEV(0, 1, 1), AFE_PWRON, tmp | (1 << 5)); - } + if (deven & DEVEN_PEG11) + pci_update_config32(PCI_DEV(0, 1, 1), AFE_PWRON, ~(1 << 16), 1 << 5); - if (deven & DEVEN_PEG12) { - tmp = pci_read_config32(PCI_DEV(0, 1, 2), AFE_PWRON) & ~(1 << 16); - pci_write_config32(PCI_DEV(0, 1, 2), AFE_PWRON, tmp | (1 << 5)); - } + if (deven & DEVEN_PEG12) + pci_update_config32(PCI_DEV(0, 1, 2), AFE_PWRON, ~(1 << 16), 1 << 5); - if (deven & DEVEN_PEG60) { - tmp = pci_read_config32(PCI_DEV(0, 6, 0), AFE_PWRON) & ~(1 << 16); - pci_write_config32(PCI_DEV(0, 6, 0), AFE_PWRON, tmp | (1 << 5)); - } + if (deven & DEVEN_PEG60) + pci_update_config32(PCI_DEV(0, 6, 0), AFE_PWRON, ~(1 << 16), 1 << 5); } void systemagent_early_init(void) { u32 capid0_a; - u32 deven; u8 reg8; /* Device ID Override Enable should be done very early */ @@ -201,8 +189,7 @@ systemagent_vtd_init(); /* Device Enable, don't touch PEG bits */ - deven = pci_read_config32(HOST_BRIDGE, DEVEN) | DEVEN_IGD; - pci_write_config32(HOST_BRIDGE, DEVEN, deven); + pci_or_config32(HOST_BRIDGE, DEVEN, DEVEN_IGD); sandybridge_setup_graphics(); diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index aa66f4a..83a0279 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -636,12 +636,8 @@ /* Called by PCI set_vga_bridge function */ static void gma_func0_disable(struct device *dev) { - u16 reg16; - struct device *dev_host = pcidev_on_root(0, 0); - - reg16 = pci_read_config16(dev_host, GGC); - reg16 |= (1 << 1); /* Disable VGA decode */ - pci_write_config16(dev_host, GGC, reg16); + /* Disable VGA decode */ + pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1); dev->enabled = 0; } diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index dce024b..b9841b5 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -25,12 +25,8 @@ static void early_pch_reset_pmcon(void) { - u8 reg8; - /* Reset RTC power status */ - reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); - reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); + pci_and_config8(PCH_LPC_DEV, GEN_PMCON_3, ~(1 << 2)); } /* The romstage entry point for this platform is not mainboard-specific, hence the name */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7f3f06cd3524790b0ec96121ed0353c89eac595 Gerrit-Change-Number: 42150 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/gm45/iommu.c: Fix regression
by Angel Pons (Code Review) 09 Jun '20

09 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42148 ) Change subject: nb/intel/gm45/iommu.c: Fix regression ...................................................................... nb/intel/gm45/iommu.c: Fix regression Commit 5ac723e (nb/intel: Fix 16-bit read/write PCI_COMMAND register) uses `pci_read_config8` to read the PCI command register, which does not correspond with what has been stated in the commit message. Moreover, it potentially break things, as the upper byte of the PCI command register is now being cleared. So, restore the original behaviour of the code, using 16-bit accesses. Change-Id: Id2c42ea8551a2fa2fa5c64e8fff8940d8304fbe0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/iommu.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/42148/1 diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 10e0d02..439127d 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -43,9 +43,7 @@ memset(bar, 0, 2<<20); /* and now disable again */ - u16 cmd = pci_read_config8(igd, PCI_COMMAND); - cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config16(igd, PCI_COMMAND, cmd); + pci_and_config16(igd, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2c42ea8551a2fa2fa5c64e8fff8940d8304fbe0 Gerrit-Change-Number: 42148 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: pci_ops.h: Turn and/or ops into update wrappers
by Angel Pons (Code Review) 09 Jun '20

09 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42147 ) Change subject: pci_ops.h: Turn and/or ops into update wrappers ...................................................................... pci_ops.h: Turn and/or ops into update wrappers Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: I2d3779967f357dd380928869c630a1996fdd60ec Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/device/pci_ops.h 1 file changed, 66 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/42147/1 diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 680deb9..cdf02d6 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -82,78 +82,6 @@ #if ENV_PCI_SIMPLE_DEVICE static __always_inline -void pci_and_config8(pci_devfn_t dev, u16 reg, u8 andmask) -#else -static __always_inline -void pci_and_config8(const struct device *dev, u16 reg, u8 andmask) -#endif -{ - u8 value = pci_read_config8(dev, reg); - pci_write_config8(dev, reg, value & andmask); -} - -#if ENV_PCI_SIMPLE_DEVICE -static __always_inline -void pci_and_config16(pci_devfn_t dev, u16 reg, u16 andmask) -#else -static __always_inline -void pci_and_config16(const struct device *dev, u16 reg, u16 andmask) -#endif -{ - u16 value = pci_read_config16(dev, reg); - pci_write_config16(dev, reg, value & andmask); -} - -#if ENV_PCI_SIMPLE_DEVICE -static __always_inline -void pci_and_config32(pci_devfn_t dev, u16 reg, u32 andmask) -#else -static __always_inline -void pci_and_config32(const struct device *dev, u16 reg, u32 andmask) -#endif -{ - u32 value = pci_read_config32(dev, reg); - pci_write_config32(dev, reg, value & andmask); -} - -#if ENV_PCI_SIMPLE_DEVICE -static __always_inline -void pci_or_config8(pci_devfn_t dev, u16 reg, u8 ormask) -#else -static __always_inline -void pci_or_config8(const struct device *dev, u16 reg, u8 ormask) -#endif -{ - u8 value = pci_read_config8(dev, reg); - pci_write_config8(dev, reg, value | ormask); -} - -#if ENV_PCI_SIMPLE_DEVICE -static __always_inline -void pci_or_config16(pci_devfn_t dev, u16 reg, u16 ormask) -#else -static __always_inline -void pci_or_config16(const struct device *dev, u16 reg, u16 ormask) -#endif -{ - u16 value = pci_read_config16(dev, reg); - pci_write_config16(dev, reg, value | ormask); -} - -#if ENV_PCI_SIMPLE_DEVICE -static __always_inline -void pci_or_config32(pci_devfn_t dev, u16 reg, u32 ormask) -#else -static __always_inline -void pci_or_config32(const struct device *dev, u16 reg, u32 ormask) -#endif -{ - u32 value = pci_read_config32(dev, reg); - pci_write_config32(dev, reg, value | ormask); -} - -#if ENV_PCI_SIMPLE_DEVICE -static __always_inline void pci_update_config8(pci_devfn_t dev, u16 reg, u8 mask, u8 or) #else static __always_inline @@ -200,6 +128,72 @@ pci_write_config32(dev, reg, reg32); } +#if ENV_PCI_SIMPLE_DEVICE +static __always_inline +void pci_and_config8(pci_devfn_t dev, u16 reg, u8 andmask) +#else +static __always_inline +void pci_and_config8(const struct device *dev, u16 reg, u8 andmask) +#endif +{ + pci_update_config8(dev, reg, andmask, 0); +} + +#if ENV_PCI_SIMPLE_DEVICE +static __always_inline +void pci_and_config16(pci_devfn_t dev, u16 reg, u16 andmask) +#else +static __always_inline +void pci_and_config16(const struct device *dev, u16 reg, u16 andmask) +#endif +{ + pci_update_config16(dev, reg, andmask, 0); +} + +#if ENV_PCI_SIMPLE_DEVICE +static __always_inline +void pci_and_config32(pci_devfn_t dev, u16 reg, u32 andmask) +#else +static __always_inline +void pci_and_config32(const struct device *dev, u16 reg, u32 andmask) +#endif +{ + pci_update_config32(dev, reg, andmask, 0); +} + +#if ENV_PCI_SIMPLE_DEVICE +static __always_inline +void pci_or_config8(pci_devfn_t dev, u16 reg, u8 ormask) +#else +static __always_inline +void pci_or_config8(const struct device *dev, u16 reg, u8 ormask) +#endif +{ + pci_update_config8(dev, reg, 0xff, ormask); +} + +#if ENV_PCI_SIMPLE_DEVICE +static __always_inline +void pci_or_config16(pci_devfn_t dev, u16 reg, u16 ormask) +#else +static __always_inline +void pci_or_config16(const struct device *dev, u16 reg, u16 ormask) +#endif +{ + pci_update_config16(dev, reg, 0xffff, ormask); +} + +#if ENV_PCI_SIMPLE_DEVICE +static __always_inline +void pci_or_config32(pci_devfn_t dev, u16 reg, u32 ormask) +#else +static __always_inline +void pci_or_config32(const struct device *dev, u16 reg, u32 ormask) +#endif +{ + pci_update_config32(dev, reg, 0xffffffff, ormask); +} + u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last); u16 pci_s_find_capability(pci_devfn_t dev, u16 cap); -- To view, visit https://review.coreboot.org/c/coreboot/+/42147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d3779967f357dd380928869c630a1996fdd60ec Gerrit-Change-Number: 42147 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/device/pci_ops.h: Add bitwise AND ops
by Angel Pons (Code Review) 09 Jun '20

09 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42145 ) Change subject: include/device/pci_ops.h: Add bitwise AND ops ...................................................................... include/device/pci_ops.h: Add bitwise AND ops For the sake of completeness, we should provide these operations. Change-Id: Ia28af94ec86319c7380d8377f7e24e5cdf55dd9c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/device/pci_ops.h 1 file changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/42145/1 diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 3c28d48..680deb9 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -82,6 +82,42 @@ #if ENV_PCI_SIMPLE_DEVICE static __always_inline +void pci_and_config8(pci_devfn_t dev, u16 reg, u8 andmask) +#else +static __always_inline +void pci_and_config8(const struct device *dev, u16 reg, u8 andmask) +#endif +{ + u8 value = pci_read_config8(dev, reg); + pci_write_config8(dev, reg, value & andmask); +} + +#if ENV_PCI_SIMPLE_DEVICE +static __always_inline +void pci_and_config16(pci_devfn_t dev, u16 reg, u16 andmask) +#else +static __always_inline +void pci_and_config16(const struct device *dev, u16 reg, u16 andmask) +#endif +{ + u16 value = pci_read_config16(dev, reg); + pci_write_config16(dev, reg, value & andmask); +} + +#if ENV_PCI_SIMPLE_DEVICE +static __always_inline +void pci_and_config32(pci_devfn_t dev, u16 reg, u32 andmask) +#else +static __always_inline +void pci_and_config32(const struct device *dev, u16 reg, u32 andmask) +#endif +{ + u32 value = pci_read_config32(dev, reg); + pci_write_config32(dev, reg, value & andmask); +} + +#if ENV_PCI_SIMPLE_DEVICE +static __always_inline void pci_or_config8(pci_devfn_t dev, u16 reg, u8 ormask) #else static __always_inline -- To view, visit https://review.coreboot.org/c/coreboot/+/42145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia28af94ec86319c7380d8377f7e24e5cdf55dd9c Gerrit-Change-Number: 42145 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: fix MADT ACPI table
by Jonathan Zhang (Code Review) 08 Jun '20

08 Jun '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40383 ) Change subject: soc/intel/xeon_sp/cpx: fix MADT ACPI table ...................................................................... Patch Set 21: (2 comments) > Patch Set 20: > > (2 comments) https://review.coreboot.org/c/coreboot/+/40383/15//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40383/15//COMMIT_MSG@10 PS15, Line 10: > Verified how? Done https://review.coreboot.org/c/coreboot/+/40383/20/src/soc/intel/xeon_sp/cpx… File src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/40383/20/src/soc/intel/xeon_sp/cpx… PS20, Line 75: #define VTD_DEV 5 > one tab too much Done -- To view, visit https://review.coreboot.org/c/coreboot/+/40383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1bf6e39db545e227e9867aa8d24f7db1d820216 Gerrit-Change-Number: 40383 Gerrit-PatchSet: 21 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 08 Jun 2020 23:22:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Configure Type C1 Aux pins
by Nick Vaccaro (Code Review) 08 Jun '20

08 Jun '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42203 ) Change subject: mb/google/volteer: Configure Type C1 Aux pins ...................................................................... mb/google/volteer: Configure Type C1 Aux pins Configure Type C1 Aux pins as outputs: - GPP_E22 (C1_AUXP_DC): GPIO high - GPP_E23 (C1_AUXN_DC): GPIO low BUG=b:146233756 TEST="emerge-volteer coreboot chromeos-bootimage", flash and verify Volteer boots to kernel and that GPP_E22 and GPP_E23 are no longer floating. Change-Id: Ice1678630b53589ad22c4d22426f815a3203256f Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/volteer/gpio.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42203/1 diff --git a/src/mainboard/google/volteer/variants/volteer/gpio.c b/src/mainboard/google/volteer/variants/volteer/gpio.c index 33167e3..5412526 100644 --- a/src/mainboard/google/volteer/variants/volteer/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer/gpio.c @@ -116,6 +116,11 @@ PAD_CFG_GPI(GPP_E16, NONE, DEEP), /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ PAD_CFG_GPO(GPP_E17, 1, DEEP), + /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC */ + PAD_CFG_GPO(GPP_E22, 1, DEEP), + /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC */ + PAD_CFG_GPO(GPP_E23, 0, DEEP), + /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/42203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice1678630b53589ad22c4d22426f815a3203256f Gerrit-Change-Number: 42203 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Cache ramstage load
by Marshall Dawson (Code Review) 08 Jun '20

08 Jun '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37492 ) Change subject: soc/amd/picasso: Cache ramstage load ...................................................................... soc/amd/picasso: Cache ramstage load Set a variable MTRR to WB for the region where ramstage will be loaded. Only a single one is required now that SMM memory is in cbmem. Change-Id: I0a31802052ac7b20871f41c80d0416ee09f8f87c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/romstage.c 2 files changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37492/1 diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 9af4c0c..338e871 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -18,9 +18,6 @@ #include <device/device.h> -#define SOC_EARLY_VMTRR_FLASH 1 -#define SOC_EARLY_VMTRR_TEMPRAM 2 - #define CSTATE_BASE_REG 0xc0010073 void picasso_init_cpus(struct device *dev); diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 22b717d..f2e3375 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -16,6 +16,7 @@ #include <arch/acpi.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <arch/exception.h> #include <delay.h> @@ -34,6 +35,25 @@ /* By default, don't do anything */ } +static void set_mtrrs_for_ramstage(void) +{ + uintptr_t mem_top; + int mtrr; + + mem_top = (uintptr_t)cbmem_top(); + + /* Cache anticipated ramstage location through the top of cbmem. + * Unlike some other implementations, TSEG is in cbmem so it will + * be cached as well. + */ + mtrr = get_free_var_mtrr(); + if (mtrr < 0) { + printk(BIOS_WARNING, "Warning: Unable to make ramstage cacheable\n"); + return; + } + set_var_mtrr(mtrr, mem_top - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); +} + static void soc_romstage(uint32_t bist) { uintptr_t top_of_mem; @@ -68,6 +88,8 @@ printk(BIOS_ERR, "Failed to set romstage handoff data\n"); post_code(0x45); + set_mtrrs_for_ramstage(); + post_code(0x46); run_ramstage(); post_code(0x50); /* Should never see this post code. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a31802052ac7b20871f41c80d0416ee09f8f87c Gerrit-Change-Number: 37492 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Cache romstage in RAM
by Marshall Dawson (Code Review) 08 Jun '20

08 Jun '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38692 ) Change subject: soc/amd/picasso: Cache romstage in RAM ...................................................................... soc/amd/picasso: Cache romstage in RAM Picasso's romstage is non-XIP and therefore is not automatically cached by the WP type applied to the flash storage. Determine its location in RAM and type it with an MTRR. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I431c63553c6eabafc4f3512a2484f350cd07003b --- M src/soc/amd/picasso/romstage.c 1 file changed, 19 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/38692/1 diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 8b8d329..4655d95 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <program_loading.h> #include <romstage_handoff.h> +#include <symbols.h> #include <elog.h> #include <soc/romstage.h> @@ -29,34 +30,47 @@ /* By default, don't do anything */ } +static void cache_romstage(void) +{ + int mtrr; + + mtrr = get_free_var_mtrr(); + if (mtrr < 0) + return; + set_var_mtrr(mtrr, (unsigned int)_romstage, _eromstage - _romstage, MTRR_TYPE_WRBACK); +} + asmlinkage void car_stage_entry(void) { uintptr_t top_of_mem; int s3_resume; post_code(0x40); - console_init(); + cache_romstage(); post_code(0x41); + console_init(); + + post_code(0x42); s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); mainboard_romstage_entry_s3(s3_resume); elog_boot_notify(s3_resume); - post_code(0x42); + post_code(0x43); u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); - post_code(0x43); + post_code(0x44); top_of_mem = ALIGN_DOWN(rdmsr(TOP_MEM).lo, 8 * MiB); backup_top_of_low_cacheable(top_of_mem); - post_code(0x44); + post_code(0x45); if (cbmem_recovery(s3_resume)) printk(BIOS_CRIT, "Failed to recover cbmem\n"); if (romstage_handoff_init(s3_resume)) printk(BIOS_ERR, "Failed to set romstage handoff data\n"); - post_code(0x45); + post_code(0x46); run_ramstage(); post_code(0x50); /* Should never see this post code. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I431c63553c6eabafc4f3512a2484f350cd07003b Gerrit-Change-Number: 38692 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Default spk_en gpio to low
by Tim Wawrzynczak (Code Review) 08 Jun '20

08 Jun '20

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41853 ) Change subject: mb/google/dedede: Default spk_en gpio to low ...................................................................... mb/google/dedede: Default spk_en gpio to low The max98357a_platform_driver will turn on/off the speaker enable gpio based on use, so configure it low to save power. BUG=None TEST=Built dedede and tested speaker playback working. We are seeing a power saving of ~10mW. Change-Id: I070679457b06cb82633c1197b893a5d89c8b2cf0 Signed-off-by: Usha P <usha.p(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41853 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Ronak Kanabar: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index e62140e..71c0c14 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -175,7 +175,7 @@ /* D16 : HP_INT_ODL */ PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, EDGE_BOTH), /* D17 : EN_SPK */ - PAD_CFG_GPO(GPP_D17, 1, PLTRST), + PAD_CFG_GPO(GPP_D17, 0, PLTRST), /* D18 : I2S_MCLK */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* D19 : WWAN_WLAN_COEX1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070679457b06cb82633c1197b893a5d89c8b2cf0 Gerrit-Change-Number: 41853 Gerrit-PatchSet: 5 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit June 2020