coreboot-gerrit June 2020

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Change in coreboot[master]: util/amdfwtool: update to allow building in any location
by Martin Roth (Code Review) 08 Jun '20

08 Jun '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42043 ) Change subject: util/amdfwtool: update to allow building in any location ...................................................................... util/amdfwtool: update to allow building in any location For the verstage-on-PSP implementation, we need 2 additional copies of the AMD firmware tables at non-standard locations. These are for RW-A & RW-B fmap regions. This change allows us to build the AMD firmware tables into those regions. BUG=b:148767300 TEST=boot with psp_verstage, verify boot location Signed-off-by: Martin Roth <martin(a)coreboot.org> Original-Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Original-Reviewed-by: Simon Glass <sjg(a)chromium.org> Change-Id: I7f841db8617b953dc671a9c12576145f85263581 --- M util/amdfwtool/amdfwtool.c 1 file changed, 30 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/42043/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 71da6fb..e6fa220 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -211,6 +211,7 @@ MIN_ROM_KB); printf(" and must a multiple of 1024\n"); printf("-l | --location Location of Directory\n"); + printf("-q | --anywhere Use any 64-byte aligned addr for Directory\n"); printf("-h | --help show this help\n"); } @@ -1021,8 +1022,8 @@ fill_dir_header(biosdir, count, cookie); } -// Unused values: CDEPqR -static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:"; +// Unused values: CDEPR +static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:q"; static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1073,6 +1074,7 @@ {"output", required_argument, 0, 'o' }, {"flashsize", required_argument, 0, 'f' }, {"location", required_argument, 0, 'l' }, + {"anywhere", no_argument, 0, 'q' }, {"help", no_argument, 0, 'h' }, {NULL, 0, 0, 0 } }; @@ -1177,6 +1179,7 @@ uint8_t sub = 0, instance = 0; int abl_image = 0; uint32_t dir_location = 0; + uint8_t any_location = 0; uint32_t romsig_offset; uint32_t rom_base_address; int multi = 0; @@ -1392,6 +1395,9 @@ retval = 1; } break; + case 'q': + any_location = 1; + break; case 'h': usage(); @@ -1434,20 +1440,28 @@ return 1; } - switch (dir_location) { - case 0: /* Fall through */ - case 0xFFFA0000: /* Fall through */ - case 0xFFF20000: /* Fall through */ - case 0xFFE20000: /* Fall through */ - case 0xFFC20000: /* Fall through */ - case 0xFF820000: /* Fall through */ - case 0xFF020000: /* Fall through */ - break; - default: - printf("Error: Invalid Directory location.\n"); - printf(" Valid locations are 0xFFFA0000, 0xFFF20000,\n"); - printf(" 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); - return 1; + if (any_location) { + if (dir_location & 0x3f) { + printf("Error: Invalid Directory location.\n"); + printf(" Valid locations are 64-byte aligned\n"); + return 1; + } + } else { + switch (dir_location) { + case 0: /* Fall through */ + case 0xFFFA0000: /* Fall through */ + case 0xFFF20000: /* Fall through */ + case 0xFFE20000: /* Fall through */ + case 0xFFC20000: /* Fall through */ + case 0xFF820000: /* Fall through */ + case 0xFF020000: /* Fall through */ + break; + default: + printf("Error: Invalid Directory location.\n"); + printf(" Valid locations are 0xFFFA0000, 0xFFF20000,\n"); + printf(" 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); + return 1; + } } ctx.rom = malloc(ctx.rom_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/42043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f841db8617b953dc671a9c12576145f85263581 Gerrit-Change-Number: 42043 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: spi: Remove non_volatile flag from block protection interface
by Daniel Gröber (dxld) (Code Review) 08 Jun '20

08 Jun '20

Hello Daniel Gröber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41746 to review the following change. Change subject: spi: Remove non_volatile flag from block protection interface ...................................................................... spi: Remove non_volatile flag from block protection interface Only Winbond parts seem to support making status register writes volatile. So this flag should not be exposed in the generic interface. Change-Id: Idadb65ffaff0dd7809b18c53086a466122b37c12 Signed-off-by: Daniel Gröber <dxld(a)darkboxed.org> --- M src/drivers/spi/boot_device_rw_nommap.c M src/drivers/spi/spi_flash.c M src/drivers/spi/winbond.c M src/include/spi_flash.h 4 files changed, 3 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/41746/1 diff --git a/src/drivers/spi/boot_device_rw_nommap.c b/src/drivers/spi/boot_device_rw_nommap.c index a383f26..ba11d05 100644 --- a/src/drivers/spi/boot_device_rw_nommap.c +++ b/src/drivers/spi/boot_device_rw_nommap.c @@ -97,7 +97,7 @@ if (spi_flash_is_write_protected(boot_dev, region_device_region(rd)) != 1) { return spi_flash_set_write_protected(boot_dev, - region_device_region(rd), true, + region_device_region(rd), SPI_WRITE_PROTECTION_REBOOT); } diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 3ffb87e..a389bc4 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -556,7 +556,6 @@ int spi_flash_set_write_protected(const struct spi_flash *flash, const struct region *region, - const bool non_volatile, const enum spi_flash_status_reg_lockdown mode) { struct region flash_region = { 0 }; @@ -576,7 +575,7 @@ return -1; } - ret = flash->prot_ops->set_write(flash, region, non_volatile, mode); + ret = flash->prot_ops->set_write(flash, region, mode); if (ret == 0 && mode != SPI_WRITE_PROTECTION_PRESERVE) { printk(BIOS_INFO, "SPI: SREG lock-down was set to "); diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index d8d3cdc..0c8059d 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -422,7 +422,6 @@ * * @param flash: The flash to operate on * @param region: The region to write protect - * @param non_volatile: Make setting permanent * @param mode: Optional status register lock-down mode * * @return 0 on success @@ -430,7 +429,6 @@ static int winbond_set_write_protection(const struct spi_flash *flash, const struct region *region, - const bool non_volatile, const enum spi_flash_status_reg_lockdown mode) { const struct spi_flash_part_id *params; @@ -527,7 +525,7 @@ mask.reg2.srp1 = 1; } - ret = winbond_flash_cmd_status(flash, mask.u, val.u, non_volatile); + ret = winbond_flash_cmd_status(flash, mask.u, val.u, true); if (ret) return ret; diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 9d0e3ad..35b02db 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -74,7 +74,6 @@ int (*set_write)(const struct spi_flash *flash, const struct region *region, - const bool non_volatile, const enum spi_flash_status_reg_lockdown mode); }; @@ -170,7 +169,6 @@ * * @param flash : A SPI flash device * @param region: A subregion of the device's region - * @param non_volatile: Write status register non-volatile * @param mode: Optional lock-down of status register * @return 0 on success @@ -178,7 +176,6 @@ int spi_flash_set_write_protected(const struct spi_flash *flash, const struct region *region, - const bool non_volatile, const enum spi_flash_status_reg_lockdown mode); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/41746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idadb65ffaff0dd7809b18c53086a466122b37c12 Gerrit-Change-Number: 41746 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Gröber (dxld) Gerrit-Reviewer: Daniel Gröber <dxld(a)darkboxed.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: ec/google/chromeec: Append connector device to *-switch properties
by Tim Wawrzynczak (Code Review) 08 Jun '20

08 Jun '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42045 ) Change subject: ec/google/chromeec: Append connector device to *-switch properties ...................................................................... ec/google/chromeec: Append connector device to *-switch properties The orientation, etc. -switch properties are supposed to use the connector device (underneath the MUX device) that belongs to the port number in question. This patch finds the CONx device and uses that to pass to the acpigen API. TEST=on Volteer, dump SSDT and verify the *-switch properties point to \_SB.PCI0.PNC.MUX.CON0 and CON1 Change-Id: Ie65c2d750f3d9f83285e0e4cc9642110c804bbad Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/ec/google/chromeec/ec_acpi.c 1 file changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/42045/1 diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 0dbaa9c..a434b53 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -124,6 +124,17 @@ port_location_to_str(port_caps.port_location)); } +extern struct chip_operations drivers_intel_pmc_mux_con_ops; +static int con_id_to_match; + +/* A callback to match a port's connector for dev_find_matching_device_on_bus */ +static bool match_connector(DEVTREE_CONST struct device *dev) +{ + return (dev->chip_ops == &drivers_intel_pmc_mux_con_ops && + dev->path.type == DEVICE_PATH_GENERIC && + dev->path.generic.id == con_id_to_match); +} + static void fill_ssdt_typec_device(const struct device *dev) { int rv; @@ -132,6 +143,7 @@ struct device *usb3_port; struct device *usb4_port; const struct device *mux; + const struct device *con; if (google_chromeec_get_num_pd_ports(&num_ports)) return; @@ -147,7 +159,14 @@ if (rv) continue; + /* Get the MUX device, and find the matching connector on its bus */ + con = NULL; mux = soc_get_pmc_mux_device(i); + if (mux) { + con_id_to_match = i; + con = dev_find_matching_device_on_bus(mux->link_list, match_connector); + } + usb2_port = NULL; usb3_port = NULL; usb4_port = NULL; @@ -160,9 +179,9 @@ .usb2_port = usb2_port, .usb3_port = usb3_port, .usb4_port = usb4_port, - .orientation_switch = mux, - .usb_role_switch = mux, - .mode_switch = mux, + .orientation_switch = con, + .usb_role_switch = con, + .mode_switch = con, }; acpigen_write_typec_connector(&config, i, add_port_location); -- To view, visit https://review.coreboot.org/c/coreboot/+/42045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie65c2d750f3d9f83285e0e4cc9642110c804bbad Gerrit-Change-Number: 42045 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: superio/nuvoton/nct6776: Reflow `pnp_dev_info` array
by Angel Pons (Code Review) 08 Jun '20

08 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42132 ) Change subject: superio/nuvoton/nct6776: Reflow `pnp_dev_info` array ...................................................................... superio/nuvoton/nct6776: Reflow `pnp_dev_info` array Each PnP device now fits in a single 96-character line. With BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ice65ce2504877c40962de7c26e01529d53d75c8e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/superio/nuvoton/nct6776/superio.c 1 file changed, 27 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/42132/1 diff --git a/src/superio/nuvoton/nct6776/superio.c b/src/superio/nuvoton/nct6776/superio.c index 6fcb93e..4197d54 100644 --- a/src/superio/nuvoton/nct6776/superio.c +++ b/src/superio/nuvoton/nct6776/superio.c @@ -32,42 +32,33 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, NCT6776_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, - 0x0ff8, }, - { NULL, NCT6776_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, - 0x0ff8, }, - { NULL, NCT6776_SP1, PNP_IO0 | PNP_IRQ0, - 0x0ff8, }, - { NULL, NCT6776_SP2, PNP_IO0 | PNP_IRQ0, - 0x0ff8, }, - { NULL, NCT6776_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, - 0x0fff, 0x0fff, }, - { NULL, NCT6776_CIR, PNP_IO0 | PNP_IRQ0, - 0x0ff8, }, - { NULL, NCT6776_ACPI}, - { NULL, NCT6776_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, - 0x0ffe, 0x0ffe, }, - { NULL, NCT6776_VID}, - { NULL, NCT6776_CIRWKUP, PNP_IO0 | PNP_IRQ0, - 0x0ff8, }, - { NULL, NCT6776_GPIO_PP_OD}, - { NULL, NCT6776_SVID}, - { NULL, NCT6776_DSLP}, - { NULL, NCT6776_GPIOA_LDN}, - { NULL, NCT6776_WDT1}, - { NULL, NCT6776_GPIOBASE, PNP_IO0, - 0x0ff8, }, - { NULL, NCT6776_GPIO0}, - { NULL, NCT6776_GPIO1}, - { NULL, NCT6776_GPIO2}, - { NULL, NCT6776_GPIO3}, - { NULL, NCT6776_GPIO4}, - { NULL, NCT6776_GPIO5}, - { NULL, NCT6776_GPIO6}, - { NULL, NCT6776_GPIO7}, - { NULL, NCT6776_GPIO8}, - { NULL, NCT6776_GPIO9}, - { NULL, NCT6776_GPIOA}, + { NULL, NCT6776_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8 }, + { NULL, NCT6776_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8 }, + { NULL, NCT6776_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8 }, + { NULL, NCT6776_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8 }, + { NULL, NCT6776_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x0fff, 0x0fff }, + { NULL, NCT6776_CIR, PNP_IO0 | PNP_IRQ0, 0x0ff8 }, + { NULL, NCT6776_ACPI }, + { NULL, NCT6776_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ffe, 0x0ffe }, + { NULL, NCT6776_VID }, + { NULL, NCT6776_CIRWKUP, PNP_IO0 | PNP_IRQ0, 0x0ff8 }, + { NULL, NCT6776_GPIO_PP_OD }, + { NULL, NCT6776_SVID }, + { NULL, NCT6776_DSLP }, + { NULL, NCT6776_GPIOA_LDN }, + { NULL, NCT6776_WDT1 }, + { NULL, NCT6776_GPIOBASE, PNP_IO0, 0x0ff8 }, + { NULL, NCT6776_GPIO0 }, + { NULL, NCT6776_GPIO1 }, + { NULL, NCT6776_GPIO2 }, + { NULL, NCT6776_GPIO3 }, + { NULL, NCT6776_GPIO4 }, + { NULL, NCT6776_GPIO5 }, + { NULL, NCT6776_GPIO6 }, + { NULL, NCT6776_GPIO7 }, + { NULL, NCT6776_GPIO8 }, + { NULL, NCT6776_GPIO9 }, + { NULL, NCT6776_GPIOA }, }; static void enable_dev(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/42132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice65ce2504877c40962de7c26e01529d53d75c8e Gerrit-Change-Number: 42132 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: spd/lp4x: Set manufacturer part name to blank (0x20)
by Furquan Shaikh (Code Review) 08 Jun '20

08 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42023 ) Change subject: spd/lp4x: Set manufacturer part name to blank (0x20) ...................................................................... spd/lp4x: Set manufacturer part name to blank (0x20) As per JEDEC spec, manufacturer part name should be set to blank(0x20). This change updates gen_spd.go to set bytes 329-348 as 0x20 and regenerates SPDs for TGL and JSL. Change-Id: I6af18d89afd7264cec7e54b38e95df83d55aa058 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/jasperlake/spd/lp4x/spd-1.hex M src/soc/intel/jasperlake/spd/lp4x/spd-10.hex M src/soc/intel/jasperlake/spd/lp4x/spd-2.hex M src/soc/intel/jasperlake/spd/lp4x/spd-3.hex M src/soc/intel/jasperlake/spd/lp4x/spd-4.hex M src/soc/intel/jasperlake/spd/lp4x/spd-5.hex M src/soc/intel/jasperlake/spd/lp4x/spd-6.hex M src/soc/intel/jasperlake/spd/lp4x/spd-7.hex M src/soc/intel/jasperlake/spd/lp4x/spd-8.hex M src/soc/intel/jasperlake/spd/lp4x/spd-9.hex M src/soc/intel/tigerlake/spd/lp4x/spd-1.hex M src/soc/intel/tigerlake/spd/lp4x/spd-2.hex M src/soc/intel/tigerlake/spd/lp4x/spd-3.hex M src/soc/intel/tigerlake/spd/lp4x/spd-4.hex M src/soc/intel/tigerlake/spd/lp4x/spd-5.hex M src/soc/intel/tigerlake/spd/lp4x/spd-6.hex M src/soc/intel/tigerlake/spd/lp4x/spd-7.hex M src/soc/intel/tigerlake/spd/lp4x/spd-8.hex M util/spd_tools/intel/lp4x/gen_spd.go 19 files changed, 51 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/42023/1 diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-1.hex b/src/soc/intel/jasperlake/spd/lp4x/spd-1.hex index 8f5bd4e..77230e7 100644 --- a/src/soc/intel/jasperlake/spd/lp4x/spd-1.hex +++ b/src/soc/intel/jasperlake/spd/lp4x/spd-1.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-10.hex b/src/soc/intel/jasperlake/spd/lp4x/spd-10.hex index bbb9eea..1fe256a 100644 --- a/src/soc/intel/jasperlake/spd/lp4x/spd-10.hex +++ b/src/soc/intel/jasperlake/spd/lp4x/spd-10.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-2.hex b/src/soc/intel/jasperlake/spd/lp4x/spd-2.hex index 60fe2ab..114363a 100644 --- a/src/soc/intel/jasperlake/spd/lp4x/spd-2.hex +++ b/src/soc/intel/jasperlake/spd/lp4x/spd-2.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-3.hex b/src/soc/intel/jasperlake/spd/lp4x/spd-3.hex index 06a06e1..50f50e2 100644 --- a/src/soc/intel/jasperlake/spd/lp4x/spd-3.hex +++ b/src/soc/intel/jasperlake/spd/lp4x/spd-3.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-4.hex b/src/soc/intel/jasperlake/spd/lp4x/spd-4.hex index 7da85a5..6db2d80 100644 --- a/src/soc/intel/jasperlake/spd/lp4x/spd-4.hex +++ b/src/soc/intel/jasperlake/spd/lp4x/spd-4.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-5.hex b/src/soc/intel/jasperlake/spd/lp4x/spd-5.hex index f025cbd..8da34f1 100644 --- a/src/soc/intel/jasperlake/spd/lp4x/spd-5.hex +++ b/src/soc/intel/jasperlake/spd/lp4x/spd-5.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-6.hex b/src/soc/intel/jasperlake/spd/lp4x/spd-6.hex index 211c8ae..3277b0b 100644 --- a/src/soc/intel/jasperlake/spd/lp4x/spd-6.hex +++ b/src/soc/intel/jasperlake/spd/lp4x/spd-6.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-7.hex b/src/soc/intel/jasperlake/spd/lp4x/spd-7.hex index 6a929f3..2a83870 100644 --- a/src/soc/intel/jasperlake/spd/lp4x/spd-7.hex +++ b/src/soc/intel/jasperlake/spd/lp4x/spd-7.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-8.hex b/src/soc/intel/jasperlake/spd/lp4x/spd-8.hex index c26874c..e4821ba 100644 --- a/src/soc/intel/jasperlake/spd/lp4x/spd-8.hex +++ b/src/soc/intel/jasperlake/spd/lp4x/spd-8.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-9.hex b/src/soc/intel/jasperlake/spd/lp4x/spd-9.hex index dcb44f0..966e666 100644 --- a/src/soc/intel/jasperlake/spd/lp4x/spd-9.hex +++ b/src/soc/intel/jasperlake/spd/lp4x/spd-9.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-1.hex b/src/soc/intel/tigerlake/spd/lp4x/spd-1.hex index 55d327a..3fc7505 100644 --- a/src/soc/intel/tigerlake/spd/lp4x/spd-1.hex +++ b/src/soc/intel/tigerlake/spd/lp4x/spd-1.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-2.hex b/src/soc/intel/tigerlake/spd/lp4x/spd-2.hex index 1558f50..7995d4c 100644 --- a/src/soc/intel/tigerlake/spd/lp4x/spd-2.hex +++ b/src/soc/intel/tigerlake/spd/lp4x/spd-2.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-3.hex b/src/soc/intel/tigerlake/spd/lp4x/spd-3.hex index c4fd994..d4cf7ef 100644 --- a/src/soc/intel/tigerlake/spd/lp4x/spd-3.hex +++ b/src/soc/intel/tigerlake/spd/lp4x/spd-3.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-4.hex b/src/soc/intel/tigerlake/spd/lp4x/spd-4.hex index 4988cb4..c4e5b50 100644 --- a/src/soc/intel/tigerlake/spd/lp4x/spd-4.hex +++ b/src/soc/intel/tigerlake/spd/lp4x/spd-4.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-5.hex b/src/soc/intel/tigerlake/spd/lp4x/spd-5.hex index cf6bf52..5fe7762 100644 --- a/src/soc/intel/tigerlake/spd/lp4x/spd-5.hex +++ b/src/soc/intel/tigerlake/spd/lp4x/spd-5.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-6.hex b/src/soc/intel/tigerlake/spd/lp4x/spd-6.hex index 0627bb3..985e5fd 100644 --- a/src/soc/intel/tigerlake/spd/lp4x/spd-6.hex +++ b/src/soc/intel/tigerlake/spd/lp4x/spd-6.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-7.hex b/src/soc/intel/tigerlake/spd/lp4x/spd-7.hex index 9c56627..f330d4b 100644 --- a/src/soc/intel/tigerlake/spd/lp4x/spd-7.hex +++ b/src/soc/intel/tigerlake/spd/lp4x/spd-7.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-8.hex b/src/soc/intel/tigerlake/spd/lp4x/spd-8.hex index f9de66b..19cce27 100644 --- a/src/soc/intel/tigerlake/spd/lp4x/spd-8.hex +++ b/src/soc/intel/tigerlake/spd/lp4x/spd-8.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/util/spd_tools/intel/lp4x/gen_spd.go b/util/spd_tools/intel/lp4x/gen_spd.go index acdc265..2465815 100644 --- a/util/spd_tools/intel/lp4x/gen_spd.go +++ b/util/spd_tools/intel/lp4x/gen_spd.go @@ -494,6 +494,8 @@ SPDIndexTAAMinFineOffset = 123 SPDIndexTCKMaxFineOffset = 124 SPDIndexTCKMinFineOffset = 125 + SPDIndexManufacturerPartNumberStartByte = 329 + SPDIndexManufacturerPartNumberEndByte = 348 /* SPD Byte Value */ @@ -549,6 +551,9 @@ /* Write Latency Set A and Read Latency DBI-RD disabled. */ SPDValueReadWriteLatency = 0x00 + + /* As per JEDEC spec, unused digits of manufacturer part number are left as blank. */ + SPDValueManufacturerPartNumberBlank = 0x20 ) var SPDAttribTable = map[int]SPDAttribTableEntry { @@ -609,9 +614,19 @@ return ioutil.WriteFile(filepath.Join(SPDDirName, SPDManifestFileName), []byte(s), 0644) } +func isManufacturerPartNumberByte(index int) bool { + if index >= SPDIndexManufacturerPartNumberStartByte && index <= SPDIndexManufacturerPartNumberEndByte { + return true + } + return false +} + func getSPDByte(index int, memAttribs *memAttributes) byte { e, ok := SPDAttribTable[index] if ok == false { + if isManufacturerPartNumberByte(index) { + return SPDValueManufacturerPartNumberBlank + } return 0x00 } -- To view, visit https://review.coreboot.org/c/coreboot/+/42023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6af18d89afd7264cec7e54b38e95df83d55aa058 Gerrit-Change-Number: 42023 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

6 10

Change in coreboot[master]: device: Add a disbling PCIe device bus master function
by John Zhao (Code Review) 08 Jun '20

08 Jun '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41042 ) Change subject: device: Add a disbling PCIe device bus master function ...................................................................... device: Add a disbling PCIe device bus master function A function pci_dev_disable_bus_master() is created. This function can be used to disable Thunderbolt PCIe root ports, bridges and devices for Vt-d based security platform at end of boot service. BUG=None TEST=verified PCIe device bus master enable bit is cleared. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ie92a15bf2c66fdc311098acb81019d4fb7f68313 --- M src/device/pci_device.c M src/include/device/pci.h 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/41042/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 6fce761..7c1b9d8 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1568,4 +1568,20 @@ #endif } } + +/** + * Disable device bus master. + * + * This function is to disable device bus master. + * + * @param dev Pointer to the device. + */ +void pci_dev_disable_bus_master(struct device *dev) +{ + u16 reg; + + reg = pci_read_config16(dev, PCI_COMMAND); + reg &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg); +} #endif diff --git a/src/include/device/pci.h b/src/include/device/pci.h index f091105..2283359 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -127,6 +127,7 @@ return (attr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY; } +void pci_dev_disable_bus_master(struct device *dev); #endif /* CONFIG_PCI */ void pci_early_bridge_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/41042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie92a15bf2c66fdc311098acb81019d4fb7f68313 Gerrit-Change-Number: 41042 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

7 14

Change in coreboot[master]: mb/google/dedede: source soc_common_config from variant overridetree
by Maulik V Vaghela (Code Review) 08 Jun '20

08 Jun '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42125 ) Change subject: mb/google/dedede: source soc_common_config from variant overridetree ...................................................................... mb/google/dedede: source soc_common_config from variant overridetree All variants are overriding soc_common_config, so source it from overridetree and remove entry from baseboard devicetree. Only keeping chipset lockdown config in baseboard which will be common across all the variants. BUG=None BRANCH=None TEST=Checked code compilation and lockdown config is applied to all variants Change-Id: I23714b721a6bb0bac785f046586790a98dc5b646 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 5 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/42125/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index a856b22..ebff476 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -141,43 +141,11 @@ # Enable Speed Shift Technology support register "speed_shift_enable" = "1" - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | Trackpad | - #| I2C1 | Digitizer | - #| I2C2 | Touchscreen | - #| I2C3 | Camera | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - }, - }" + # chipset_lockdown configuration + # Use below format to override value in overridetree.cb if required + # format: + # register "common_soc_config.<variable_name>" = "value" + register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT device domain 0 on device pci 00.0 on end # Host Bridge -- To view, visit https://review.coreboot.org/c/coreboot/+/42125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23714b721a6bb0bac785f046586790a98dc5b646 Gerrit-Change-Number: 42125 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F
by Christian Walter (Code Review) 08 Jun '20

08 Jun '20

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F ...................................................................... Patch Set 51: (19 comments) https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/Kconfig: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 6: # select HAVE_ACPI_RESUME > Hmm? Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 22: Supermicro_X11_LGA1151V2_SERIES > This doesn't need underscores Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 39: : config MAINBOARD_VENDOR : string : default "Supermicro" > Not needed (if it is, then check src/mainboard/supermicro/Kconfig) Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 56: config CONSOLE_POST : bool : default n > Isn't this default already? Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/bootblock.c: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 18: const struct pad_config * early_gpio_table = get_early_gpio_table(&num); > "foo * bar" should be "foo *bar" Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 28: garbeled > garbled Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb: PS49: > No license header Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 10: device pci 02.0 on end # Integrated Graphics Device > Is it really on? Yup. https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 11: device pci 04.0 on end # SA Thermal device : device pci 04.0 on end # Intel Xeon E3 > Um, this is duplicated Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 62: > empty line Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/dsdt.asl: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 13: // Some generic macros > Please drop this comment Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 19: Scope (\_SB) { : Device (PCI0) > Device (\_SB. […] Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 27: // Chipset specific sleep states > Not chipset specific, this should also be dropped Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/memory.c: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 29: /* : * Baseboard Rcomp target values. : */ > This fits in a single line Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 44: const struct cnl_mb_cfg * variant_memcfg_config(void) > Should be fixed Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/ramstage.c: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 10: size_t num = 0; > Please fix the indentation Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/include/variant/gpio.h: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 3: PCH_GPIO_H > Um, not PCH? Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 15: > Do we need so many spaces? Done https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 68: register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" > I think we can drop one tab here Done -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 51 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 08 Jun 2020 11:45:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/amd: Clean up code smell
by Patrick Georgi (Code Review) 08 Jun '20

08 Jun '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42101 ) Change subject: vendorcode/amd: Clean up code smell ...................................................................... vendorcode/amd: Clean up code smell Change-Id: I8a39e862176cd1c8a14424eb6d2bf7edabd36adb Found-by: Silvio Cesare, https://twitter.com/silviocesare/status/1268784333029965824 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/42101/1 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c index 9d6ca3d..2a935b2 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c @@ -226,7 +226,6 @@ // Get Node count NodeCount = 1; - NodeCount = 1; // The worst-case buffer size to request is for the SRAT table header, one // entree for special region (base 640k block), two memory -- To view, visit https://review.coreboot.org/c/coreboot/+/42101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a39e862176cd1c8a14424eb6d2bf7edabd36adb Gerrit-Change-Number: 42101 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: acpi: Rename motherboard_fill_fadt() to mainboard_fill_fadt()
by Kyösti Mälkki (Code Review) 08 Jun '20

08 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42007 ) Change subject: acpi: Rename motherboard_fill_fadt() to mainboard_fill_fadt() ...................................................................... acpi: Rename motherboard_fill_fadt() to mainboard_fill_fadt() Change-Id: Ie576fd47301aa484cb1396e0c6f7260b7698af4d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/mainboard/facebook/fbg1701/acpi_tables.c M src/mainboard/intel/harcuvar/acpi_tables.c M src/mainboard/ocp/tiogapass/acpi_tables.c M src/mainboard/portwell/m107/acpi_tables.c M src/mainboard/protectli/vault_bsw/acpi_tables.c M src/mainboard/scaleway/tagada/acpi_tables.c 8 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/42007/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 2f4a2bb..fefa7bf 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1222,7 +1222,7 @@ #if CONFIG(COMMON_FADT) __weak void soc_fill_fadt(acpi_fadt_t *fadt) { } -__weak void motherboard_fill_fadt(acpi_fadt_t *fadt) { } +__weak void mainboard_fill_fadt(acpi_fadt_t *fadt) { } void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { @@ -1261,7 +1261,7 @@ acpi_fill_fadt(fadt); soc_fill_fadt(fadt); - motherboard_fill_fadt(fadt); + mainboard_fill_fadt(fadt); header->checksum = acpi_checksum((void *) fadt, header->length); diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 0691797..207e8dc 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -871,7 +871,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt); void soc_fill_fadt(acpi_fadt_t *fadt); -void motherboard_fill_fadt(acpi_fadt_t *fadt); +void mainboard_fill_fadt(acpi_fadt_t *fadt); void update_ssdt(void *ssdt); void update_ssdtx(void *ssdtx, int i); diff --git a/src/mainboard/facebook/fbg1701/acpi_tables.c b/src/mainboard/facebook/fbg1701/acpi_tables.c index 8492704..e98df14 100644 --- a/src/mainboard/facebook/fbg1701/acpi_tables.c +++ b/src/mainboard/facebook/fbg1701/acpi_tables.c @@ -38,7 +38,7 @@ return current; } -void motherboard_fill_fadt(acpi_fadt_t *fadt) +void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_MOBILE; fadt->iapc_boot_arch &= ~ACPI_FADT_8042; diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index 6f8bd07..4be3f6f 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -24,7 +24,7 @@ gnvs->tpmp = 0; } -void motherboard_fill_fadt(acpi_fadt_t *fadt) +void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; } diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c index 250ccad..85372e5 100644 --- a/src/mainboard/ocp/tiogapass/acpi_tables.c +++ b/src/mainboard/ocp/tiogapass/acpi_tables.c @@ -10,7 +10,7 @@ acpi_init_gnvs(gnvs); } -void motherboard_fill_fadt(acpi_fadt_t *fadt) +void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; } diff --git a/src/mainboard/portwell/m107/acpi_tables.c b/src/mainboard/portwell/m107/acpi_tables.c index 8492704..e98df14 100644 --- a/src/mainboard/portwell/m107/acpi_tables.c +++ b/src/mainboard/portwell/m107/acpi_tables.c @@ -38,7 +38,7 @@ return current; } -void motherboard_fill_fadt(acpi_fadt_t *fadt) +void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_MOBILE; fadt->iapc_boot_arch &= ~ACPI_FADT_8042; diff --git a/src/mainboard/protectli/vault_bsw/acpi_tables.c b/src/mainboard/protectli/vault_bsw/acpi_tables.c index 9ecb5ac..1724c71 100644 --- a/src/mainboard/protectli/vault_bsw/acpi_tables.c +++ b/src/mainboard/protectli/vault_bsw/acpi_tables.c @@ -28,7 +28,7 @@ return current; } -void motherboard_fill_fadt(acpi_fadt_t *fadt) +void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_MOBILE; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES; diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index 6f8bd07..4be3f6f 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -24,7 +24,7 @@ gnvs->tpmp = 0; } -void motherboard_fill_fadt(acpi_fadt_t *fadt) +void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; } -- To view, visit https://review.coreboot.org/c/coreboot/+/42007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie576fd47301aa484cb1396e0c6f7260b7698af4d Gerrit-Change-Number: 42007 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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