coreboot-gerrit June 2020

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Change in coreboot[master]: security/vboot: Add option to run verstage before bootblock
by Raul Rangel (Code Review) 08 Jun '20

08 Jun '20

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41814 ) Change subject: security/vboot: Add option to run verstage before bootblock ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/41814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4849777cb7ba9f90fe8428b82c21884d1e662b96 Gerrit-Change-Number: 41814 Gerrit-PatchSet: 5 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Mon, 08 Jun 2020 20:51:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: camera SSDT generation
by Matt Delco (Code Review) 08 Jun '20

08 Jun '20

Matt Delco has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41607 ) Change subject: drivers/intel/mipi_camera: camera SSDT generation ...................................................................... Patch Set 11: (3 comments) https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… File src/drivers/intel/mipi_camera/camera.c: https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 272: 0 > Is this always supposed to be 0? It's zero for all the existing systems in coreboot, though the docs in the Linux kernel have examples of devices where it's set to non-zero (e.g., ov7251 and ov5645). The 'head' of the Linux kernel seems to default to zero, so I did wonder if it's worthwhile to specify but I didn't read the code in detail nor check older kernel versions. https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 303: /* endpoint? */ > ? acpi_graph_get_remote_endpoint() seems to confirm my guess, where a comment says that port and endpoint indices are provided as arguments. https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 315: 180 > always 180? So far only nautilus's cam0.asl specifies a "rotation" and it uses 180. -- To view, visit https://review.coreboot.org/c/coreboot/+/41607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Gerrit-Change-Number: 41607 Gerrit-PatchSet: 11 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 08 Jun 2020 20:10:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Tim Wawrzynczak (Code Review) 08 Jun '20

08 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35403 ) Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... Patch Set 90: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 90 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 08 Jun 2020 19:17:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: solve MTRRs only from 4GiB and below
by Aaron Durbin (Code Review) 08 Jun '20

08 Jun '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41898 ) Change subject: soc/amd/picasso: solve MTRRs only from 4GiB and below ...................................................................... soc/amd/picasso: solve MTRRs only from 4GiB and below Use x86_setup_mtrrs_with_detect_no_above_4gb() to only solve the MTRR solution for memory up to 4GiB. This assumes 4GiB to TOM2 is marked as writeback in sys_cfg MSR. BUG=b:155426691 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ib8358b614682f6a97278f3a60b5ada5e607965af --- M src/soc/amd/picasso/cpu.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/41898/1 diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 55f9014..c1d598e 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -36,7 +36,7 @@ */ static void pre_mp_init(void) { - x86_setup_mtrrs_with_detect(); + x86_setup_mtrrs_with_detect_no_above_4gb(); x86_mtrr_check(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/41898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8358b614682f6a97278f3a60b5ada5e607965af Gerrit-Change-Number: 41898 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: remove save/restore MTRRs around FSP-M
by Aaron Durbin (Code Review) 08 Jun '20

08 Jun '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42104 ) Change subject: soc/amd/picasso: remove save/restore MTRRs around FSP-M ...................................................................... soc/amd/picasso: remove save/restore MTRRs around FSP-M AGESA FSP-M implementation is now not updating MTRRs out from under the caller. As such, remove the save/restore of MTRRs from the FSP-M call. BUG=b:155426691 Change-Id: I14f3b18dd373ce17957ef3857920e1c4e2901bbe Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/soc/amd/picasso/Makefile.inc D src/soc/amd/picasso/include/soc/mtrr.h D src/soc/amd/picasso/mtrr.c M src/soc/amd/picasso/romstage.c 4 files changed, 0 insertions(+), 138 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/42104/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index ce0a7a8..9f15557 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -30,7 +30,6 @@ romstage-y += southbridge.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += psp.c -romstage-y += mtrr.c romstage-y += config.c verstage-y += gpio.c diff --git a/src/soc/amd/picasso/include/soc/mtrr.h b/src/soc/amd/picasso/include/soc/mtrr.h deleted file mode 100644 index 8746e18..0000000 --- a/src/soc/amd/picasso/include/soc/mtrr.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __PICASSO_MTRR_H__ -#define __PICASSO_MTRR_H__ - -void picasso_save_mtrrs(void); -void picasso_restore_mtrrs(void); - -#endif /* __PICASSO_MTRR_H__ */ diff --git a/src/soc/amd/picasso/mtrr.c b/src/soc/amd/picasso/mtrr.c deleted file mode 100644 index d2f8ff3..0000000 --- a/src/soc/amd/picasso/mtrr.c +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <assert.h> -#include <commonlib/bsd/helpers.h> -#include <console/console.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> -#include <soc/mtrr.h> - -/* Picasso defines 8 Variable MTRRs */ -#define MAX_VARIABLE_MTRRS 8 -#define SYS_CFG_MTRR_BITS ( \ -SYSCFG_MSR_TOM2WB | \ -SYSCFG_MSR_TOM2En | \ -SYSCFG_MSR_MtrrVarDramEn | \ -SYSCFG_MSR_MtrrFixDramModEn | \ -SYSCFG_MSR_MtrrFixDramEn \ -) - -static const unsigned int fixed_mtrr_offsets[] = { - MTRR_FIX_64K_00000, - MTRR_FIX_16K_80000, - MTRR_FIX_16K_A0000, - MTRR_FIX_4K_C0000, - MTRR_FIX_4K_C8000, - MTRR_FIX_4K_D0000, - MTRR_FIX_4K_D8000, - MTRR_FIX_4K_E0000, - MTRR_FIX_4K_E8000, - MTRR_FIX_4K_F0000, - MTRR_FIX_4K_F8000, -}; - -static int mtrrs_saved; -static msr_t sys_cfg; -static msr_t mtrr_def; -static msr_t mtrr_base[MAX_VARIABLE_MTRRS]; -static msr_t mtrr_mask[MAX_VARIABLE_MTRRS]; -static msr_t fixed_mtrrs[ARRAY_SIZE(fixed_mtrr_offsets)]; - -void picasso_save_mtrrs(void) -{ - unsigned int i; - int mtrrs; - - mtrrs = get_var_mtrr_count(); - - ASSERT_MSG(mtrrs == MAX_VARIABLE_MTRRS, "Unexpected number of MTRRs\n"); - - for (i = 0; i < MAX_VARIABLE_MTRRS; ++i) { - mtrr_base[i] = rdmsr(MTRR_PHYS_BASE(i)); - mtrr_mask[i] = rdmsr(MTRR_PHYS_MASK(i)); - printk(BIOS_DEBUG, - "Saving Variable MTRR %d: Base: 0x%08x 0x%08x, Mask: 0x%08x 0x%08x\n", i, - mtrr_base[i].hi, mtrr_base[i].lo, mtrr_mask[i].hi, mtrr_mask[i].lo); - } - - for (i = 0; i < ARRAY_SIZE(fixed_mtrr_offsets); ++i) { - fixed_mtrrs[i] = rdmsr(fixed_mtrr_offsets[i]); - printk(BIOS_DEBUG, "Saving Fixed MTRR %u: 0x%08x 0x%08x\n", i, - fixed_mtrrs[i].hi, fixed_mtrrs[i].lo); - } - - mtrr_def = rdmsr(MTRR_DEF_TYPE_MSR); - printk(BIOS_DEBUG, "Saving Default Type MTRR: 0x%08x 0x%08x\n", mtrr_def.hi, - mtrr_def.lo); - - sys_cfg = rdmsr(SYSCFG_MSR); - printk(BIOS_DEBUG, "Saving SYS_CFG: 0x%08x 0x%08x\n", mtrr_def.hi, mtrr_def.lo); - - mtrrs_saved = 1; -} - -static void update_if_changed(unsigned int offset, msr_t expected) -{ - msr_t tmp = rdmsr(offset); - if (tmp.lo == expected.lo && tmp.hi == expected.hi) - return; - - printk(BIOS_INFO, "MSR %#x was modified: 0x%08x 0x%08x\n", offset, tmp.hi, tmp.lo); - wrmsr(offset, expected); -} - -void picasso_restore_mtrrs(void) -{ - unsigned int i; - msr_t tmp_sys_cfg; - - ASSERT_MSG(mtrrs_saved, "Must save MTRRs before restoring.\n"); - - for (i = 0; i < MAX_VARIABLE_MTRRS; ++i) { - update_if_changed(MTRR_PHYS_BASE(i), mtrr_base[i]); - update_if_changed(MTRR_PHYS_MASK(i), mtrr_mask[i]); - } - - for (i = 0; i < ARRAY_SIZE(fixed_mtrr_offsets); ++i) - update_if_changed(fixed_mtrr_offsets[i], fixed_mtrrs[i]); - - update_if_changed(MTRR_DEF_TYPE_MSR, mtrr_def); - - tmp_sys_cfg = rdmsr(SYSCFG_MSR); - - /* We only care about the MTRR bits in the SYSCFG register */ - if ((tmp_sys_cfg.lo & SYS_CFG_MTRR_BITS) != (sys_cfg.lo & SYS_CFG_MTRR_BITS)) { - printk(BIOS_INFO, "SYS_CFG was modified: 0x%08x 0x%08x\n", tmp_sys_cfg.hi, - tmp_sys_cfg.lo); - tmp_sys_cfg.lo &= ~SYS_CFG_MTRR_BITS; - tmp_sys_cfg.lo |= (sys_cfg.lo & SYS_CFG_MTRR_BITS); - wrmsr(SYSCFG_MSR, tmp_sys_cfg); - } -} diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 0bbceec..f3330dd 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -12,7 +12,6 @@ #include <program_loading.h> #include <elog.h> #include <soc/romstage.h> -#include <soc/mtrr.h> #include <types.h> #include "chip.h" #include <fsp/api.h> @@ -22,16 +21,6 @@ /* By default, don't do anything */ } -/* TODO(b/155426691): Make FSP AGESA leave MTRRs alone */ -static void clear_agesa_mtrrs(void) -{ - disable_cache(); - - picasso_restore_mtrrs(); - - enable_cache(); -} - void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *mcfg = &mupd->FspmConfig; @@ -94,15 +83,9 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); - post_code(0x43); - picasso_save_mtrrs(); - post_code(0x44); fsp_memory_init(s3_resume); - post_code(0x45); - clear_agesa_mtrrs(); - post_code(0x46); run_ramstage(); -- To view, visit https://review.coreboot.org/c/coreboot/+/42104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14f3b18dd373ce17957ef3857920e1c4e2901bbe Gerrit-Change-Number: 42104 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: establish full early caching memory map
by Aaron Durbin (Code Review) 08 Jun '20

08 Jun '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42103 ) Change subject: soc/amd/picasso: establish full early caching memory map ...................................................................... soc/amd/picasso: establish full early caching memory map The PSP does the memory training and setting up of MSRs for TOP_MEM and TOM2. Set caching up for all the DRAM areas: Enable WB caching for 1MiB->TOP_MEM, 4GiB->TOM2. Enable WC caching fro 0->1MiB except 0xa0000->0xc0000. BUG=b:155426691 Change-Id: I83916a220ea4016d4438dd4fb5be82dec5506f80 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/soc/amd/picasso/bootblock/bootblock.c 1 file changed, 58 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42103/1 diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 1ff6896..107303a 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -13,28 +13,72 @@ #include <soc/i2c.h> #include <amdblocks/amd_pci_mmconf.h> +/* PSP performs the memory training and setting up DRAM map prior to x86 cores + being released. Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, + route lower memory addresses covered by fixed MTRRs to DRAM except for + 0xa0000-0xc0000 . */ static void set_caching(void) { - msr_t deftype = {0, 0}; - int mtrr; + msr_t top_mem; + msr_t sys_cfg; + msr_t mtrr_def_type; + msr_t fixed_mtrr_ram; + msr_t fixed_mtrr_mmio; + struct var_mtrr_context mtrr_ctx; - /* Disable fixed and variable MTRRs while we setup */ - wrmsr(MTRR_DEF_TYPE_MSR, deftype); + var_mtrr_context_init(&mtrr_ctx, NULL); + top_mem = rdmsr(TOP_MEM); + /* Enable RdDram and WrDram attributes in fixed MTRRs. */ + sys_cfg = rdmsr(SYSCFG_MSR); + sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; + + /* Fixed MTRR constants. */ + fixed_mtrr_ram.lo = fixed_mtrr_ram.hi = + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 0) | + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 8) | + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) | + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24); + fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi = + ((MTRR_TYPE_UNCACHEABLE) << 0) | + ((MTRR_TYPE_UNCACHEABLE) << 8) | + ((MTRR_TYPE_UNCACHEABLE) << 16) | + ((MTRR_TYPE_UNCACHEABLE) << 24); + + /* Prep default MTRR type. */ + mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR); + mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK; + mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE; + mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; + + disable_cache(); + + wrmsr(SYSCFG_MSR, sys_cfg); clear_all_var_mtrr(); - mtrr = get_free_var_mtrr(); - if (mtrr >= 0) - set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK); + var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - mtrr = get_free_var_mtrr(); - if (mtrr >= 0) - set_var_mtrr(mtrr, (unsigned int)_bootblock, REGION_SIZE(bootblock), - MTRR_TYPE_WRBACK); + /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ + wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio); + wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram); - /* Enable variable MTRRs. Fixed MTRRs are left disabled since they are not used. */ - deftype.lo |= MTRR_DEF_TYPE_EN | MTRR_TYPE_UNCACHEABLE; - wrmsr(MTRR_DEF_TYPE_MSR, deftype); + wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type); + + /* Enable Fixed and Variable MTRRs. */ + sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn; + sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB; + sys_cfg.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, sys_cfg); enable_cache(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83916a220ea4016d4438dd4fb5be82dec5506f80 Gerrit-Change-Number: 42103 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Furquan Shaikh (Code Review) 08 Jun '20

08 Jun '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35403 ) Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... Patch Set 90: I will go through this change this week and post an update before end of the week. Thanks Sridhar! -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 90 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 08 Jun 2020 18:20:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 08 Jun '20

08 Jun '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35403 ) Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... Patch Set 90: (1 comment) https://review.coreboot.org/c/coreboot/+/35403/89//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35403/89//COMMIT_MSG@10 PS89, Line 10: > Please make this a list/enumeration. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 90 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 08 Jun 2020 18:19:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 08 Jun '20

08 Jun '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Sridhar Siricilla, Rizwan Qureshi, Subrata Banik, Balaji Manigandan, Aamir Bohra, Patrick Rudolph, V Sowmya, Andrey Petrov, Jamie Ryu, Martin Roth, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35403 to look at the new patch set (#90). Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... soc/intel/common/basecode: Implement CSE update flow The following changes have been done in this patch: 1. Get the CSE partition info containing version of CSE RW using GET_BOOT_PARTITION_INFO HECI command 2. Get the me_rw.version from the currently selected RW slot. 3. If the version from the above 2 locations don't match start the update - If CSE's current boot partition is not RO, then * Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. * Send global reset command to reset the system. - Enable HMRFPO (Host ME Region Flash Protection Override) operation mode using HMRFPO_ENABLE HECI command - Erase and Copy the CBFS CSE RW to CSE RW partition - Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command - Trigger global reset - The system should boot with the updated CSE RW partition. TEST=Verified basic update flows on hatch and helios. BUG=b:111330995 Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- A Documentation/soc/intel/cse_fw_update/Layout_after.svg A Documentation/soc/intel/cse_fw_update/Layout_before.svg A Documentation/soc/intel/cse_fw_update/cse_fw_update.md M Documentation/soc/intel/index.md M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse_lite.c 6 files changed, 700 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/90 -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 90 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/amdfwtool: Add option for setting PSP/FW shared memory location
by Martin Roth (Code Review) 08 Jun '20

08 Jun '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42044 ) Change subject: util/amdfwtool: Add option for setting PSP/FW shared memory location ...................................................................... util/amdfwtool: Add option for setting PSP/FW shared memory location This tells the PSP where in main memory to copy the vboot workbuf. BUG=b:152576063 TEST=Build sharedmem destination into AMDFW, verify shared memory gets placed at that location. Signed-off-by: Martin Roth <martin(a)coreboot.org> Original-Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519 Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Original-Reviewed-by: Simon Glass <sjg(a)chromium.org> Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0 --- M util/amdfwtool/amdfwtool.c 1 file changed, 31 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/42044/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index e6fa220..c3227b6 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -212,6 +212,8 @@ printf(" and must a multiple of 1024\n"); printf("-l | --location Location of Directory\n"); printf("-q | --anywhere Use any 64-byte aligned addr for Directory\n"); + printf("-R | --sharedmem Location of PSP/FW shared memory\n"); + printf("-P | --sharedmem-size Maximum size of the PSP/FW shared memory area\n"); printf("-h | --help show this help\n"); } @@ -225,6 +227,7 @@ AMD_BIOS_UCODE = 0x66, AMD_BIOS_APCB_BK = 0x68, AMD_BIOS_MP2_CFG = 0x6a, + AMD_BIOS_PSP_SHARED_MEM = 0x6b, AMD_BIOS_L2_PTR = 0x70, AMD_BIOS_INVALID, } amd_bios_type; @@ -395,6 +398,7 @@ { .type = AMD_BIOS_UCODE, .inst = 1, .level = BDT_LVL2 }, { .type = AMD_BIOS_UCODE, .inst = 2, .level = BDT_LVL2 }, { .type = AMD_BIOS_MP2_CFG, .level = BDT_LVL2 }, + { .type = AMD_BIOS_PSP_SHARED_MEM, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_INVALID }, }; @@ -480,7 +484,7 @@ bios_directory_entry entries[]; } bios_directory_table; -#define MAX_BIOS_ENTRIES 0x2e +#define MAX_BIOS_ENTRIES 0x2f typedef struct _context { char *rom; /* target buffer, size of flash device */ @@ -864,7 +868,8 @@ fw_table[i].type != AMD_BIOS_APOB && fw_table[i].type != AMD_BIOS_APOB_NV && fw_table[i].type != AMD_BIOS_L2_PTR && - fw_table[i].type != AMD_BIOS_BIN)) + fw_table[i].type != AMD_BIOS_BIN && + fw_table[i].type != AMD_BIOS_PSP_SHARED_MEM)) continue; /* BIOS Directory items may have additional requirements */ @@ -914,6 +919,11 @@ } } + /* PSP_SHARED_MEM needs a destination and size */ + if (fw_table[i].type == AMD_BIOS_PSP_SHARED_MEM && + (!fw_table[i].dest || !fw_table[i].size)) + continue; + biosdir->entries[count].type = fw_table[i].type; biosdir->entries[count].region_type = fw_table[i].region_type; biosdir->entries[count].dest = fw_table[i].dest ? @@ -973,6 +983,11 @@ ctx->current = ALIGN(ctx->current + bytes, 0x100U); break; + case AMD_BIOS_PSP_SHARED_MEM: + biosdir->entries[count].dest = fw_table[i].dest; + biosdir->entries[count].size = fw_table[i].size; + break; + default: /* everything else is copied from input */ if (fw_table[i].type == AMD_BIOS_APCB || fw_table[i].type == AMD_BIOS_APCB_BK) @@ -1022,8 +1037,8 @@ fill_dir_header(biosdir, count, cookie); } -// Unused values: CDEPR -static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:q"; +// Unused values: CDE +static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:"; static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1075,6 +1090,8 @@ {"flashsize", required_argument, 0, 'f' }, {"location", required_argument, 0, 'l' }, {"anywhere", no_argument, 0, 'q' }, + {"sharedmem", required_argument, 0, 'R' }, + {"sharedmem-size", required_argument, 0, 'P' }, {"help", no_argument, 0, 'h' }, {NULL, 0, 0, 0 } }; @@ -1398,6 +1415,16 @@ case 'q': any_location = 1; break; + case 'R': + /* shared memory destination */ + register_fw_addr(AMD_BIOS_PSP_SHARED_MEM, 0, optarg, 0); + sub = instance = 0; + break; + case 'P': + /* shared memory size */ + register_fw_addr(AMD_BIOS_PSP_SHARED_MEM, NULL, NULL, optarg); + sub = instance = 0; + break; case 'h': usage(); -- To view, visit https://review.coreboot.org/c/coreboot/+/42044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0 Gerrit-Change-Number: 42044 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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