Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 ......................................................................
mb/google/hatch/vr/puff: Setup PL2 and PsysPL2
This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ
For Type-C adapter, we don't have Pcritcial(10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power.
BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings is correct
Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc --- M src/mainboard/google/hatch/variants/puff/mainboard.c 1 file changed, 50 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/41555/1
diff --git a/src/mainboard/google/hatch/variants/puff/mainboard.c b/src/mainboard/google/hatch/variants/puff/mainboard.c index ef5df4a..8c33d4c 100644 --- a/src/mainboard/google/hatch/variants/puff/mainboard.c +++ b/src/mainboard/google/hatch/variants/puff/mainboard.c @@ -4,8 +4,11 @@ #include <chip.h> #include <delay.h> #include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> +#include <soc/pci_devs.h> #include <timer.h>
#define GPIO_HDMI_HPD GPP_E13 @@ -36,10 +39,10 @@ */ #define SET_PSYSPL2(w) (9 * (w) / 10)
-#define PUFF_PL2 (35) - -#define PUFF_PSYSPL2 (58) - +#define PUFF_U22_PL2 (35) +#define PUFF_U62_U42_PL2 (51) +#define PUFF_CELERON_PENTIUM_PSYSPL2 (65) +#define PUFF_CORE_CPU_PSYSPL2 (90) #define PUFF_MAX_TIME_WINDOW 6 #define PUFF_MIN_DUTYCYCLE 4
@@ -55,18 +58,15 @@ * +-------------+-----+---------+-----------+-------+ * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | * +-------------+-----+---------+-----------+-------+ - * | i7 U42 | 51 | 81 | x(.85PL4) | x(82) | - * | celeron U22 | 35 | 58 | x(.85PL4) | x(51) | + * | i7 U42 | 51 | 90 | x(.85PL4) | x(82) | + * | i3 U22 | 35 | 65 | x(.85PL4) | x(51) | * +-------------+-----+---------+-----------+-------+ * For USB C charger: - * +-------------+-----+---------+---------+-------+ - * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+---------+---------+-------+ - * | 60 (U42) | 44 | 54 | 54 | 54 | - * | 60 (U22) | 29 | 54 | 54 | x(43) | - * | n (U42) | 44 | .9n | .9n | .9n | - * | n (U22) | 29 | .9n | .9n | x(43) | - * +-------------+-----+---------+---------+-------+ + * +-------------+-----------------+---------+---------+-------+ + * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | + * +-------------+-----+-----------+---------+---------+-------+ + * | n | min(0.9n, PL2) | 0.9n | 0.9n | 0.9n | + * +-------------+-----+-----------+---------+---------+-------+ */
/* @@ -85,15 +85,22 @@ */ #define PSYS_IMAX 9600 #define BJ_VOLTS_MV 19000 +#define ROP_MAX (30)
static void mainboard_set_power_limits(config_t *conf) { enum usb_chg_type type; u32 watts; u16 volts_mv, current_ma; - u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22 + u32 psyspl2 = PUFF_CELERON_PENTIUM_PSYSPL2; // default BJ value + u32 pl2 = PUFF_U22_PL2; // default PL2 for U22 int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv);
+ struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + u16 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + dev = pcidev_path_on_root(SA_DEVFN_IGD); + u16 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ conf->tdp_psyspl3 = 0; conf->tdp_pl4 = 0; @@ -101,23 +108,44 @@ if (rv == 0 && type == USB_CHG_TYPE_PD) { /* Detected USB-PD. Base on max value of adapter */ watts = ((u32)current_ma * volts_mv) / 1000000; - psyspl2 = watts; - conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); + /* set psyspl2 to 90% of adapter rating */ + psyspl2 = SET_PSYSPL2(watts); + + /* Limit PL2 if the adapter is with lower capability */ + if (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT || + mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_6_2) + pl2 = (psyspl2 > PUFF_U62_U42_PL2) ? PUFF_U62_U42_PL2 : psyspl2; + else + pl2 = (psyspl2 > PUFF_U22_PL2) ? PUFF_U22_PL2 : psyspl2; + + conf->tdp_psyspl3 = psyspl2; /* set max possible time window */ conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; /* set minimum duty cycle */ conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; - conf->tdp_pl4 = SET_PSYSPL2(psyspl2); + /* No data about an arbitary Type-C adapter, set pl4 conservatively. */ + conf->tdp_pl4 = psyspl2; } else { - /* Input type is barrel jack */ + /*i + * Input type is barrel jack, from the SKU matrix: + * 1. i3/i5/i7 SKUs use 90W BJ + * 2. Celeron and Pentium use 65W BJ (default) + */ volts_mv = BJ_VOLTS_MV; + /* Use IGD ID to check if CPU is Core SKUs */ + if (igd_id != PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1 && + igd_id != PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5) { + psyspl2 = PUFF_CORE_CPU_PSYSPL2; + if (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT || + mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_6_2) + pl2 = PUFF_U62_U42_PL2; + } } /* voltage unit is milliVolts and current is in milliAmps */ conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000);
- conf->tdp_pl2_override = PUFF_PL2; - /* set psyspl2 to 90% of max adapter power */ - conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); + conf->tdp_pl2_override = pl2; + conf->tdp_psyspl2 = psyspl2; }
void variant_ramstage_init(void)
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41555/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/mainboard.c:
https://review.coreboot.org/c/coreboot/+/41555/1/src/mainboard/google/hatch/... PS1, Line 126: /* No data about an arbitary Type-C adapter, set pl4 conservatively. */ 'arbitary' may be misspelled - perhaps 'arbitrary'?
https://review.coreboot.org/c/coreboot/+/41555/1/src/mainboard/google/hatch/... PS1, Line 136: if (igd_id != PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1 && suspect code indent for conditional statements (16, 32)
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41555
to look at the new patch set (#2).
Change subject: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 ......................................................................
mb/google/hatch/vr/puff: Setup PL2 and PsysPL2
This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ
For Type-C adapter, we don't have Pcritcial(10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power.
BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings is correct
Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc --- M src/mainboard/google/hatch/variants/puff/mainboard.c 1 file changed, 50 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/41555/2
Hello Shelley Chen, build bot (Jenkins), Jamie Chen, Edward O'Callaghan, Ryan Lin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41555
to look at the new patch set (#3).
Change subject: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 ......................................................................
mb/google/hatch/vr/puff: Setup PL2 and PsysPL2
This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ
For Type-C adapter, we don't have Pcritcial(10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power.
BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings is correct
Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc --- M src/mainboard/google/hatch/variants/puff/mainboard.c 1 file changed, 50 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/41555/3
Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/41555/3/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/mainboard.c:
https://review.coreboot.org/c/coreboot/+/41555/3/src/mainboard/google/hatch/... PS3, Line 44: #define PUFF_U62_U42_PL2 (51) It's better to use the same indentation here.
https://review.coreboot.org/c/coreboot/+/41555/3/src/mainboard/google/hatch/... PS3, Line 89: It's better to use the same indentation here.
https://review.coreboot.org/c/coreboot/+/41555/3/src/mainboard/google/hatch/... PS3, Line 130: i Keep the first line of block comment empty.
Hello Shelley Chen, build bot (Jenkins), Jamie Chen, Edward O'Callaghan, Ryan Lin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41555
to look at the new patch set (#4).
Change subject: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 ......................................................................
mb/google/hatch/vr/puff: Setup PL2 and PsysPL2
This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ
For Type-C adapter, we don't have Pcritcial(10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power.
BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings is correct
Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc --- M src/mainboard/google/hatch/variants/puff/mainboard.c 1 file changed, 55 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/41555/4
Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/41555/3/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/mainboard.c:
https://review.coreboot.org/c/coreboot/+/41555/3/src/mainboard/google/hatch/... PS3, Line 44: #define PUFF_U62_U42_PL2 (51)
It's better to use the same indentation here.
Ack
https://review.coreboot.org/c/coreboot/+/41555/3/src/mainboard/google/hatch/... PS3, Line 89:
It's better to use the same indentation here.
Ack
https://review.coreboot.org/c/coreboot/+/41555/3/src/mainboard/google/hatch/... PS3, Line 130: i
Keep the first line of block comment empty.
Ack
Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41555/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/mainboard.c:
https://review.coreboot.org/c/coreboot/+/41555/4/src/mainboard/google/hatch/... PS4, Line 88: #define ROP_MAX (30) Why do you define ROP_MAX? It seems never be used.
Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41555/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/mainboard.c:
https://review.coreboot.org/c/coreboot/+/41555/4/src/mainboard/google/hatch/... PS4, Line 88: #define ROP_MAX (30)
Why do you define ROP_MAX? It seems never be used.
seems like I forgot to remove it.
Hello Shelley Chen, build bot (Jenkins), Jamie Chen, Edward O'Callaghan, Ryan Lin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41555
to look at the new patch set (#5).
Change subject: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 ......................................................................
mb/google/hatch/vr/puff: Setup PL2 and PsysPL2
This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ
For Type-C adapter, we don't have Pcritcial(10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power.
BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings is correct
Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc --- M src/mainboard/google/hatch/variants/puff/mainboard.c 1 file changed, 54 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/41555/5
Ryan Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 ......................................................................
Patch Set 5: Code-Review+1
verified on i7 and pentium sku
Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 ......................................................................
Patch Set 5: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/41555/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/mainboard.c:
https://review.coreboot.org/c/coreboot/+/41555/4/src/mainboard/google/hatch/... PS4, Line 88: #define ROP_MAX (30)
seems like I forgot to remove it.
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/41555/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41555/5//COMMIT_MSG@7 PS5, Line 7: Setup The verb is spelled with a space: Set up.
https://review.coreboot.org/c/coreboot/+/41555/5//COMMIT_MSG@15 PS5, Line 15: Pcritcial(10ms) Please add a space before the (.
https://review.coreboot.org/c/coreboot/+/41555/5//COMMIT_MSG@20 PS5, Line 20: is are
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Setup PL2 and PsysPL2 ......................................................................
Patch Set 5: Code-Review+2
Hello Shelley Chen, build bot (Jenkins), Jamie Chen, Edward O'Callaghan, Ryan Lin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41555
to look at the new patch set (#6).
Change subject: mb/google/hatch/vr/puff: Set up PL2 and PsysPL2 ......................................................................
mb/google/hatch/vr/puff: Set up PL2 and PsysPL2
This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ
For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power.
BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct
Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc --- M src/mainboard/google/hatch/variants/puff/mainboard.c 1 file changed, 54 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/41555/6
Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Set up PL2 and PsysPL2 ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/41555/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41555/5//COMMIT_MSG@7 PS5, Line 7: Setup
The verb is spelled with a space: Set up.
Done
https://review.coreboot.org/c/coreboot/+/41555/5//COMMIT_MSG@15 PS5, Line 15: Pcritcial(10ms)
Please add a space before the (.
Done
https://review.coreboot.org/c/coreboot/+/41555/5//COMMIT_MSG@20 PS5, Line 20: is
are
Done
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Set up PL2 and PsysPL2 ......................................................................
Patch Set 6: Code-Review+2
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Set up PL2 and PsysPL2 ......................................................................
Patch Set 6:
Patch Set 6: Code-Review+2
Can you apply this to the three Puff variants as well please.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Set up PL2 and PsysPL2 ......................................................................
Patch Set 6:
Patch Set 6:
Patch Set 6: Code-Review+2
Can you apply this to the three Puff variants as well please.
Do we need to wait for this before this can go in?
Ryan Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Set up PL2 and PsysPL2 ......................................................................
Patch Set 6:
Patch Set 6:
Patch Set 6:
Patch Set 6: Code-Review+2
Can you apply this to the three Puff variants as well please.
Do we need to wait for this before this can go in?
We will let partners to do the customization for Puff variants. We can have this CL be merged first.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41555 )
Change subject: mb/google/hatch/vr/puff: Set up PL2 and PsysPL2 ......................................................................
mb/google/hatch/vr/puff: Set up PL2 and PsysPL2
This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ
For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power.
BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct
Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/41555 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Edward O'Callaghan quasisec@chromium.org --- M src/mainboard/google/hatch/variants/puff/mainboard.c 1 file changed, 54 insertions(+), 28 deletions(-)
Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/puff/mainboard.c b/src/mainboard/google/hatch/variants/puff/mainboard.c index b5bc699..537e3df 100644 --- a/src/mainboard/google/hatch/variants/puff/mainboard.c +++ b/src/mainboard/google/hatch/variants/puff/mainboard.c @@ -4,9 +4,12 @@ #include <chip.h> #include <delay.h> #include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <intelblocks/power_limit.h> +#include <soc/pci_devs.h> #include <timer.h>
#define GPIO_HDMI_HPD GPP_E13 @@ -35,14 +38,13 @@ * For type-C chargers, set PL2 to 90% of max power to account for * cable loss and FET Rdson loss in the path from the source. */ -#define SET_PSYSPL2(w) (9 * (w) / 10) - -#define PUFF_PL2 (35) - -#define PUFF_PSYSPL2 (58) - -#define PUFF_MAX_TIME_WINDOW 6 -#define PUFF_MIN_DUTYCYCLE 4 +#define SET_PSYSPL2(w) (9 * (w) / 10) +#define PUFF_U22_PL2 (35) +#define PUFF_U62_U42_PL2 (51) +#define PUFF_CELERON_PENTIUM_PSYSPL2 (65) +#define PUFF_CORE_CPU_PSYSPL2 (90) +#define PUFF_MAX_TIME_WINDOW 6 +#define PUFF_MIN_DUTYCYCLE 4
/* * mainboard_set_power_limits @@ -56,18 +58,15 @@ * +-------------+-----+---------+-----------+-------+ * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | * +-------------+-----+---------+-----------+-------+ - * | i7 U42 | 51 | 81 | x(.85PL4) | x(82) | - * | celeron U22 | 35 | 58 | x(.85PL4) | x(51) | + * | i7 U42 | 51 | 90 | x(.85PL4) | x(82) | + * | i3 U22 | 35 | 65 | x(.85PL4) | x(51) | * +-------------+-----+---------+-----------+-------+ * For USB C charger: - * +-------------+-----+---------+---------+-------+ - * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+---------+---------+-------+ - * | 60 (U42) | 44 | 54 | 54 | 54 | - * | 60 (U22) | 29 | 54 | 54 | x(43) | - * | n (U42) | 44 | .9n | .9n | .9n | - * | n (U22) | 29 | .9n | .9n | x(43) | - * +-------------+-----+---------+---------+-------+ + * +-------------+-----------------+---------+---------+-------+ + * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | + * +-------------+-----+-----------+---------+---------+-------+ + * | n | min(0.9n, PL2) | 0.9n | 0.9n | 0.9n | + * +-------------+-----+-----------+---------+---------+-------+ */
/* @@ -84,17 +83,23 @@ * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W */ -#define PSYS_IMAX 9600 -#define BJ_VOLTS_MV 19000 +#define PSYS_IMAX 9600 +#define BJ_VOLTS_MV 19000
static void mainboard_set_power_limits(struct soc_power_limits_config *conf) { enum usb_chg_type type; u32 watts; u16 volts_mv, current_ma; - u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22 + u32 psyspl2 = PUFF_CELERON_PENTIUM_PSYSPL2; // default BJ value + u32 pl2 = PUFF_U22_PL2; // default PL2 for U22 int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv);
+ struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + u16 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + dev = pcidev_path_on_root(SA_DEVFN_IGD); + u16 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ conf->tdp_psyspl3 = 0; conf->tdp_pl4 = 0; @@ -102,23 +107,44 @@ if (rv == 0 && type == USB_CHG_TYPE_PD) { /* Detected USB-PD. Base on max value of adapter */ watts = ((u32)current_ma * volts_mv) / 1000000; - psyspl2 = watts; - conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); + /* set psyspl2 to 90% of adapter rating */ + psyspl2 = SET_PSYSPL2(watts); + + /* Limit PL2 if the adapter is with lower capability */ + if (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT || + mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_6_2) + pl2 = (psyspl2 > PUFF_U62_U42_PL2) ? PUFF_U62_U42_PL2 : psyspl2; + else + pl2 = (psyspl2 > PUFF_U22_PL2) ? PUFF_U22_PL2 : psyspl2; + + conf->tdp_psyspl3 = psyspl2; /* set max possible time window */ conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; /* set minimum duty cycle */ conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; - conf->tdp_pl4 = SET_PSYSPL2(psyspl2); + /* No data about an arbitrary Type-C adapter, set pl4 conservatively. */ + conf->tdp_pl4 = psyspl2; } else { - /* Input type is barrel jack */ + /* + * Input type is barrel jack, from the SKU matrix: + * 1. i3/i5/i7 SKUs use 90W BJ + * 2. Celeron and Pentium use 65W BJ (default) + */ volts_mv = BJ_VOLTS_MV; + /* Use IGD ID to check if CPU is Core SKUs */ + if (igd_id != PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1 && + igd_id != PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5) { + psyspl2 = PUFF_CORE_CPU_PSYSPL2; + if (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT || + mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_6_2) + pl2 = PUFF_U62_U42_PL2; + } } /* voltage unit is milliVolts and current is in milliAmps */ conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000);
- conf->tdp_pl2_override = PUFF_PL2; - /* set psyspl2 to 90% of max adapter power */ - conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); + conf->tdp_pl2_override = pl2; + conf->tdp_psyspl2 = psyspl2; }
void variant_ramstage_init(void)
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