Change in coreboot[master]: Revert "sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register"

[Nico Huber (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, HAOUAS Elyes,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/42163

to review the following change.

Change subject: Revert "sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register"
......................................................................

Revert "sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register"

This reverts commit 04506e2987162ec0f280afddd6f4acac070bbf15.

Turned out that `dev->command` is only a `u8` and the way it's used
here is wrong: It is not supposed to reflect the state of the register
but only gathers (lower) bits to be enabled during allocation.

Change-Id: Iacd2b753939e8adcf5aedd4b9cf101638a324aa6
Signed-off-by: Nico Huber 
---
M src/southbridge/amd/cimx/sb800/late.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/42163/1

diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index de91a9a..1cf3ae8 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -98,7 +98,7 @@
    }

dev->command |= PCI_COMMAND_MASTER;
-	pci_write_config16(dev, PCI_COMMAND, dev->command);
+	pci_write_config8(dev, PCI_COMMAND, dev->command);
    printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n");
 }

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42163 )

Change subject: Revert "sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register"
......................................................................

Patch Set 1: Code-Review+2

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42163 )

Change subject: Revert "sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register"
......................................................................

Patch Set 1: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42163 )

Change subject: Revert "sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register"
......................................................................

Revert "sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register"

This reverts commit 04506e2987162ec0f280afddd6f4acac070bbf15.

Turned out that `dev->command` is only a `u8` and the way it's used
here is wrong: It is not supposed to reflect the state of the register
but only gathers (lower) bits to be enabled during allocation.

Change-Id: Iacd2b753939e8adcf5aedd4b9cf101638a324aa6
Signed-off-by: Nico Huber 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42163
Reviewed-by: Angel Pons 
Reviewed-by: HAOUAS Elyes 
Tested-by: build bot (Jenkins) 
---
M src/southbridge/amd/cimx/sb800/late.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  HAOUAS Elyes: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index d57ce00..43a88b7 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -98,7 +98,7 @@
    }

dev->command |= PCI_COMMAND_MASTER;
-	pci_write_config16(dev, PCI_COMMAND, dev->command);
+	pci_write_config8(dev, PCI_COMMAND, dev->command);
    printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n");
 }