coreboot-gerrit May 2020

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Change in coreboot[master]: mainboard/clevo/n141cu: Add new mainboard
by Felix Singer (Code Review) 05 May '20

05 May '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40581 ) Change subject: mainboard/clevo/n141cu: Add new mainboard ...................................................................... Patch Set 27: (1 comment) https://review.coreboot.org/c/coreboot/+/40581/10/src/mainboard/clevo/cml-u… File src/mainboard/clevo/cml-u/ramstage.c: https://review.coreboot.org/c/coreboot/+/40581/10/src/mainboard/clevo/cml-u… PS10, Line 10: cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); > Why do it this early? in theory, we could end up with wrong values set […] I don't think this is still necessary. I mark this as done. -- To view, visit https://review.coreboot.org/c/coreboot/+/40581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 Gerrit-Change-Number: 40581 Gerrit-PatchSet: 27 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 May 2020 15:24:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/clevo/n141cu: Add new mainboard
by Felix Singer (Code Review) 05 May '20

05 May '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40581 to look at the new patch set (#27). Change subject: mainboard/clevo/n141cu: Add new mainboard ...................................................................... mainboard/clevo/n141cu: Add new mainboard Add a new mainboard with the following specs: - Intel i5-10210U (Comet Lake) - Intel UHD graphics - Intel HD audio - 1x Ethernet 1Gbit/s - 1x SATA3 - 1x M.2 slot x4 (PCIe/SATA) - 1x M.2 slot x1 (WLAN/BT) - 1x 3G/LTE - USB2/3 - Thunderbolt - HDMI, mDP - CCD camera + mic - SD card reader - TPM2 SLB9670 Tested: - All of the hardware above - SeaBIOS and TianoCore - vboot with RO, RO+A, RO+A+B - Booted Arch Linux - Linux 5.6.10 - Linux LTS 5.4.38 What works / What works not: - WLAN/BT does not work, but also not with vendor firmware - Everything else works Todos: - Missing libgfxinit support - Missing flashrom support - Different configuration switches mentioned in ramstage.c Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 --- M MAINTAINERS A src/mainboard/clevo/Kconfig A src/mainboard/clevo/Kconfig.name A src/mainboard/clevo/cml-u/Kconfig A src/mainboard/clevo/cml-u/Kconfig.name A src/mainboard/clevo/cml-u/Makefile.inc A src/mainboard/clevo/cml-u/acpi/ac.asl A src/mainboard/clevo/cml-u/acpi/battery.asl A src/mainboard/clevo/cml-u/acpi/buttons.asl A src/mainboard/clevo/cml-u/acpi/ec.asl A src/mainboard/clevo/cml-u/acpi/ec_ram.asl A src/mainboard/clevo/cml-u/acpi/gpe.asl A src/mainboard/clevo/cml-u/acpi/hid.asl A src/mainboard/clevo/cml-u/acpi/keyboard.asl A src/mainboard/clevo/cml-u/acpi/lid.asl A src/mainboard/clevo/cml-u/acpi/mainboard.asl A src/mainboard/clevo/cml-u/acpi/sleep.asl A src/mainboard/clevo/cml-u/acpi/tbt.asl A src/mainboard/clevo/cml-u/board_info.txt A src/mainboard/clevo/cml-u/dsdt.asl A src/mainboard/clevo/cml-u/fmds/vboot-ro.fmd A src/mainboard/clevo/cml-u/fmds/vboot-roa.fmd A src/mainboard/clevo/cml-u/fmds/vboot-roab.fmd A src/mainboard/clevo/cml-u/ramstage.c A src/mainboard/clevo/cml-u/romstage.c A src/mainboard/clevo/cml-u/variants/n141cu/data.vbt A src/mainboard/clevo/cml-u/variants/n141cu/devicetree.cb A src/mainboard/clevo/cml-u/variants/n141cu/gma-mainboard.ads A src/mainboard/clevo/cml-u/variants/n141cu/hda_verb.c A src/mainboard/clevo/cml-u/variants/n141cu/include/gpio_table.h 30 files changed, 1,861 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/40581/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/40581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 Gerrit-Change-Number: 40581 Gerrit-PatchSet: 27 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/clevo/n141cu: Add new mainboard
by Felix Singer (Code Review) 05 May '20

05 May '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40581 to look at the new patch set (#26). Change subject: mainboard/clevo/n141cu: Add new mainboard ...................................................................... mainboard/clevo/n141cu: Add new mainboard Add a new mainboard with the following specs: - Intel i5-10210U (Comet Lake) - Intel UHD graphics - Intel HD audio - 1x Ethernet 1Gbit/s - 1x SATA3 - 1x M.2 slot x4 (PCIe/SATA) - 1x M.2 slot x1 (WLAN/BT) - 1x 3G/LTE - USB2/3 - Thunderbolt - HDMI, mDP - CCD camera + mic - SD card reader - TPM2 SLB9670 Tested: - All of the hardware above - SeaBIOS and TianoCore - vboot with RO, RO+A, RO+A+B - Booted Arch Linux - Linux 5.6.10 - Linux LTS 5.4.38 What works / What works not: - WLAN/BT does not work, but also not with vendor firmware - Everything else works Todos: - Missing libgfxinit support - Missing flashrom support - Different configuration switches mentioned in ramstage.c Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 --- M MAINTAINERS A src/mainboard/clevo/Kconfig A src/mainboard/clevo/Kconfig.name A src/mainboard/clevo/cml-u/Kconfig A src/mainboard/clevo/cml-u/Kconfig.name A src/mainboard/clevo/cml-u/Makefile.inc A src/mainboard/clevo/cml-u/acpi/ac.asl A src/mainboard/clevo/cml-u/acpi/battery.asl A src/mainboard/clevo/cml-u/acpi/buttons.asl A src/mainboard/clevo/cml-u/acpi/ec.asl A src/mainboard/clevo/cml-u/acpi/ec_ram.asl A src/mainboard/clevo/cml-u/acpi/gpe.asl A src/mainboard/clevo/cml-u/acpi/hid.asl A src/mainboard/clevo/cml-u/acpi/keyboard.asl A src/mainboard/clevo/cml-u/acpi/lid.asl A src/mainboard/clevo/cml-u/acpi/mainboard.asl A src/mainboard/clevo/cml-u/acpi/sleep.asl A src/mainboard/clevo/cml-u/acpi/tbt.asl A src/mainboard/clevo/cml-u/board_info.txt A src/mainboard/clevo/cml-u/dsdt.asl A src/mainboard/clevo/cml-u/fmds/vboot-ro.fmd A src/mainboard/clevo/cml-u/fmds/vboot-roa.fmd A src/mainboard/clevo/cml-u/fmds/vboot-roab.fmd A src/mainboard/clevo/cml-u/ramstage.c A src/mainboard/clevo/cml-u/romstage.c A src/mainboard/clevo/cml-u/variants/n141cu/data.vbt A src/mainboard/clevo/cml-u/variants/n141cu/devicetree.cb A src/mainboard/clevo/cml-u/variants/n141cu/gma-mainboard.ads A src/mainboard/clevo/cml-u/variants/n141cu/hda_verb.c A src/mainboard/clevo/cml-u/variants/n141cu/include/gpio_table.h 30 files changed, 1,861 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/40581/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/40581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 Gerrit-Change-Number: 40581 Gerrit-PatchSet: 26 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/clevo/n141cu: Add new mainboard
by Felix Singer (Code Review) 05 May '20

05 May '20

1 0

Change in coreboot[master]: libpayload/drivers/usb/xhci: Allowing xHCI v1.2 in libpayload
by Dossym Nurmukhanov (Code Review) 05 May '20

05 May '20

Dossym Nurmukhanov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41039 ) Change subject: libpayload/drivers/usb/xhci: Allowing xHCI v1.2 in libpayload ...................................................................... libpayload/drivers/usb/xhci: Allowing xHCI v1.2 in libpayload The latest Intel FSP requires xHCI v1.2 support in libpayload, so updated the supported protocols. This was sufficient for the tests that I performed. BUG=b:155315876 TEST=booting from multiple USB sticks with the latest Intel FSP that requires xHCI v1.2 Change-Id: I236fed9beef86ff5e1bf7962d882fdae5817a1ff Signed-off-by: Dossym Nurmukhanov <dossym(a)google.com> --- M payloads/libpayload/drivers/usb/xhci.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/41039/1 diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 08a81ef..53dd782 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -198,7 +198,7 @@ xhci_debug("hciversion: %"PRIx8".%"PRIx8"\n", CAP_GET(CAPVER_HI, xhci->capreg), CAP_GET(CAPVER_LO, xhci->capreg)); if ((CAP_GET(CAPVER, xhci->capreg) < 0x96) || - (CAP_GET(CAPVER, xhci->capreg) > 0x110)) { + (CAP_GET(CAPVER, xhci->capreg) > 0x120)) { xhci_debug("Unsupported xHCI version\n"); goto _free_xhci; } -- To view, visit https://review.coreboot.org/c/coreboot/+/41039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I236fed9beef86ff5e1bf7962d882fdae5817a1ff Gerrit-Change-Number: 41039 Gerrit-PatchSet: 1 Gerrit-Owner: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sconfig: Allow `register` entries below devices, too
by Nico Huber (Code Review) 05 May '20

05 May '20

Hello Felix Singer, Furquan Shaikh, Angel Pons, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40803 to review the following change. Change subject: sconfig: Allow `register` entries below devices, too ...................................................................... sconfig: Allow `register` entries below devices, too Every device belongs to a chip. And we already keep that relation by inheriting the `.chip_info` pointer if downstream devices don't have another chip specified. So we can also allow to specify `register` settings at the device level. Change-Id: I44e6b95d0cd708fef69b152ebc46b869b2bb9205 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M util/sconfig/sconfig.y 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/40803/1 diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index d55b18b..4af6e18 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -37,7 +37,7 @@ chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ; -devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | devicechildren smbios_slot_desc | /* empty */ ; +devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | devicechildren smbios_slot_desc | devicechildren registers | /* empty */ ; chip: CHIP STRING /* == path */ { $<chip_instance>$ = new_chip_instance($<string>2); -- To view, visit https://review.coreboot.org/c/coreboot/+/40803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44e6b95d0cd708fef69b152ebc46b869b2bb9205 Gerrit-Change-Number: 40803 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Configure SoC specific gpios
by Maulik V Vaghela (Code Review) 05 May '20

05 May '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40572 ) Change subject: mb/intel/jasperlake_rvp: Configure SoC specific gpios ...................................................................... mb/intel/jasperlake_rvp: Configure SoC specific gpios This patch configures all SoC related gpios as per mainboard schematics. Till now, we were relying on FSP to do SoC specific gpio programming but now we'll program all gpios from mainboard. This will remove ambiguity of gpio programming done by FSP and coreboot will do full gpio programming Programming gpios of following IPs - I2C - Emmc - Display - CPU specific gpio (SLP lines) - Cnvi BUG=None BRANCH=None TEST=compile coreboot and checked that all IPs functionality working. Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c 1 file changed, 146 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40572/1 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index 9b86839..d9eb35f 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -7,14 +7,37 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { - /* ToDo: Fill other gpio configuration */ /* WWAN_WAKE_N */ PAD_CFG_GPI_SCI(GPP_A10, NONE, DEEP, LEVEL, INVERT), + /* DDSP_HPD_B */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* EDP_HPD */ + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + /* M.2_WWAN_DISABLE_N */ PAD_CFG_GPO(GPP_A19, 1, PLTRST), + /* VCCIN_AUX_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* VCCIN_AUX_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + + /* PCIE_X4_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + + /* AP_SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* M.2_WLAN_PERST_N */ PAD_CFG_GPO(GPP_B17, 1, PLTRST), @@ -30,7 +53,7 @@ /* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), - /*PCH_INT_ODL*/ + /* DDP_HDMI_HPD_C */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), /* WWAN_PERST_N */ @@ -60,18 +83,114 @@ /* I2S_MCLK */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* CNV_MFUART2_TXD */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + + /* CNV_PA_BLANKING */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + /* WWAN_FCP_OFF_N */ PAD_CFG_GPO(GPP_E3, 1, PLTRST), + /* DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + + /* DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), + + /* DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), + + /* DDPC_CTRLCLK */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + + /* DDPC_CTRLDATA */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + + /* CNV_BRI_DT_R */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + + /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + + /* CNV_RGI_DT_R */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + + /* CNV_RGI_RSP */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + + /* CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + + /* EMMC_CMD */ + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), + + /* EMMC_DATA0 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + + /* EMMC_DATA1 */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), + + /* EMMC_DATA2 */ + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + + /* EMMC_DATA3 */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + + /* EMMC_DATA4 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + + /* EMMC_DATA5 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + + /* EMMC_DATA6 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + + /* EMMC_DATA7 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + + /* EMMC_RCLK */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + + /* EMMC_CLK */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + + /* EMMC_RESET_N */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + + /* SD_CD# */ + PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), + + /* SD_WP */ + PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), + /*FPS_INT*/ PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, INVERT), + /* SD_PWR_EN_B */ + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1) + + /* CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), + /* WWAN EN GPIO */ PAD_CFG_GPO(GPP_H7, 1, PLTRST), + /* CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + /* M.2_BT_I2S2_SCLK */ PAD_CFG_GPI(GPP_H11, NONE, PLTRST), + /* CNV_RF_RESET */ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF2), + /*PCH_INT_ODL*/ PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT), @@ -103,10 +222,10 @@ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S1_SFRM */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1), /* I2S1_TXD */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1), /* WWAN RST_N */ PAD_CFG_GPO(GPP_S0, 1, DEEP), @@ -123,6 +242,29 @@ /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_S7, UP_20K, DEEP, NF2), + /* AP_BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + + /* GPP_GPD1/ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + + /* EC_AP_WAKE_ODL */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + + /* EC_AP_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), + + /* AP_SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + + /* AP_SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + + /* WLAN_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + + /* virtual GPIO for SD card detect */ + PAD_CFG_GPI_GPIO_DRIVER(VGPIO_39, NONE, DEEP), }; /* Early pad configuration in bootblock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb Gerrit-Change-Number: 40572 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Correct the EMMC PCR Port ID
by Patrick Georgi (Code Review) 05 May '20

05 May '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41028 ) Change subject: soc/intel/jasperlake: Correct the EMMC PCR Port ID ...................................................................... soc/intel/jasperlake: Correct the EMMC PCR Port ID Updating EMMC PCR PID from 0x52 to 0x51 for Jasperlake BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP from emmc Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Change-Id: I17d4e7b7e0fe5e0b18867b6481b5bc9227ae19e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41028 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: V Sowmya <v.sowmya(a)intel.com> Reviewed-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/jasperlake/include/soc/pcr_ids.h 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Aamir Bohra: Looks good to me, approved V Sowmya: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/intel/jasperlake/include/soc/pcr_ids.h b/src/soc/intel/jasperlake/include/soc/pcr_ids.h index 411a141..a423134 100644 --- a/src/soc/intel/jasperlake/include/soc/pcr_ids.h +++ b/src/soc/intel/jasperlake/include/soc/pcr_ids.h @@ -4,9 +4,9 @@ #ifndef SOC_JASPERLAKE_PCR_H #define SOC_JASPERLAKE_PCR_H /* - * Port ids + * Port IDs */ -#define PID_EMMC 0x52 +#define PID_EMMC 0x51 #define PID_SDX 0x53 #define PID_GPIOCOM0 0x6e -- To view, visit https://review.coreboot.org/c/coreboot/+/41028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17d4e7b7e0fe5e0b18867b6481b5bc9227ae19e3 Gerrit-Change-Number: 41028 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/jasperlake: Allow SD card power enable polarity configuration
by Patrick Georgi (Code Review) 05 May '20

05 May '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41027 ) Change subject: soc/intel/jasperlake: Allow SD card power enable polarity configuration ...................................................................... soc/intel/jasperlake: Allow SD card power enable polarity configuration SdCardPowerEnableActiveHigh is a UPD which controls polarity of SD card power enable pin. Setting it 1 will set polarity of this pin as Active high. This patch will allow to control it from devicetree so that it can be set as per each board's requirement. BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP, Verified UPD value from FSP log Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Change-Id: Id777a262651689952a217875e6606f67855fc2f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41027 Reviewed-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: V Sowmya <v.sowmya(a)intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Aamir Bohra: Looks good to me, approved V Sowmya: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index f525fd8..28dccab 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -136,10 +136,12 @@ /* SDCard related configuration */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); - if (!dev) + if (!dev) { params->ScsSdCardEnabled = 0; - else + } else { params->ScsSdCardEnabled = dev->enabled; + params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh; + } params->Device4Enable = config->Device4Enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/41027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id777a262651689952a217875e6606f67855fc2f4 Gerrit-Change-Number: 41027 Gerrit-PatchSet: 9 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: superio/fintek/f81216h: Rename pnp_enter_conf_state()
by Keith Hui (Code Review) 05 May '20

05 May '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40967 ) Change subject: superio/fintek/f81216h: Rename pnp_enter_conf_state() ...................................................................... superio/fintek/f81216h: Rename pnp_enter_conf_state() This one does require a version with non-standard signature. Rename to avoid conflict with upcoming standardization. Note: There is currently no mainboard in tree using this super I/O. Change-Id: I2d58d73eca0be1f4daf9106a1258274486f803a5 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/superio/fintek/f81216h/early_serial.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/40967/1 diff --git a/src/superio/fintek/f81216h/early_serial.c b/src/superio/fintek/f81216h/early_serial.c index d2fa0fe..d97dd86 100644 --- a/src/superio/fintek/f81216h/early_serial.c +++ b/src/superio/fintek/f81216h/early_serial.c @@ -9,14 +9,14 @@ #define FINTEK_EXIT_KEY 0xAA -static void pnp_enter_conf_state(pnp_devfn_t dev, u8 f81216h_entry_key) +static void f81216h_pnp_enter_conf_state(pnp_devfn_t dev, u8 f81216h_entry_key) { u16 port = dev >> 8; outb(f81216h_entry_key, port); outb(f81216h_entry_key, port); } -static void pnp_exit_conf_state(pnp_devfn_t dev) +void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(FINTEK_EXIT_KEY, port); @@ -43,7 +43,7 @@ key = 0x77; /* try the hw default */ break; } - pnp_enter_conf_state(dev, key); + f81216h_pnp_enter_conf_state(dev, key); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); -- To view, visit https://review.coreboot.org/c/coreboot/+/40967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d58d73eca0be1f4daf9106a1258274486f803a5 Gerrit-Change-Number: 40967 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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