Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40581
to look at the new patch set (#27).
Change subject: mainboard/clevo/n141cu: Add new mainboard
......................................................................
mainboard/clevo/n141cu: Add new mainboard
Add a new mainboard with the following specs:
- Intel i5-10210U (Comet Lake)
- Intel UHD graphics
- Intel HD audio
- 1x Ethernet 1Gbit/s
- 1x SATA3
- 1x M.2 slot x4 (PCIe/SATA)
- 1x M.2 slot x1 (WLAN/BT)
- 1x 3G/LTE
- USB2/3
- Thunderbolt
- HDMI, mDP
- CCD camera + mic
- SD card reader
- TPM2 SLB9670
Tested:
- All of the hardware above
- SeaBIOS and TianoCore
- vboot with RO, RO+A, RO+A+B
- Booted Arch Linux
- Linux 5.6.10
- Linux LTS 5.4.38
What works / What works not:
- WLAN/BT does not work, but also not with vendor firmware
- Everything else works
Todos:
- Missing libgfxinit support
- Missing flashrom support
- Different configuration switches mentioned in ramstage.c
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9
---
M MAINTAINERS
A src/mainboard/clevo/Kconfig
A src/mainboard/clevo/Kconfig.name
A src/mainboard/clevo/cml-u/Kconfig
A src/mainboard/clevo/cml-u/Kconfig.name
A src/mainboard/clevo/cml-u/Makefile.inc
A src/mainboard/clevo/cml-u/acpi/ac.asl
A src/mainboard/clevo/cml-u/acpi/battery.asl
A src/mainboard/clevo/cml-u/acpi/buttons.asl
A src/mainboard/clevo/cml-u/acpi/ec.asl
A src/mainboard/clevo/cml-u/acpi/ec_ram.asl
A src/mainboard/clevo/cml-u/acpi/gpe.asl
A src/mainboard/clevo/cml-u/acpi/hid.asl
A src/mainboard/clevo/cml-u/acpi/keyboard.asl
A src/mainboard/clevo/cml-u/acpi/lid.asl
A src/mainboard/clevo/cml-u/acpi/mainboard.asl
A src/mainboard/clevo/cml-u/acpi/sleep.asl
A src/mainboard/clevo/cml-u/acpi/tbt.asl
A src/mainboard/clevo/cml-u/board_info.txt
A src/mainboard/clevo/cml-u/dsdt.asl
A src/mainboard/clevo/cml-u/fmds/vboot-ro.fmd
A src/mainboard/clevo/cml-u/fmds/vboot-roa.fmd
A src/mainboard/clevo/cml-u/fmds/vboot-roab.fmd
A src/mainboard/clevo/cml-u/ramstage.c
A src/mainboard/clevo/cml-u/romstage.c
A src/mainboard/clevo/cml-u/variants/n141cu/data.vbt
A src/mainboard/clevo/cml-u/variants/n141cu/devicetree.cb
A src/mainboard/clevo/cml-u/variants/n141cu/gma-mainboard.ads
A src/mainboard/clevo/cml-u/variants/n141cu/hda_verb.c
A src/mainboard/clevo/cml-u/variants/n141cu/include/gpio_table.h
30 files changed, 1,861 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/40581/27
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9
Gerrit-Change-Number: 40581
Gerrit-PatchSet: 27
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40581
to look at the new patch set (#26).
Change subject: mainboard/clevo/n141cu: Add new mainboard
......................................................................
mainboard/clevo/n141cu: Add new mainboard
Add a new mainboard with the following specs:
- Intel i5-10210U (Comet Lake)
- Intel UHD graphics
- Intel HD audio
- 1x Ethernet 1Gbit/s
- 1x SATA3
- 1x M.2 slot x4 (PCIe/SATA)
- 1x M.2 slot x1 (WLAN/BT)
- 1x 3G/LTE
- USB2/3
- Thunderbolt
- HDMI, mDP
- CCD camera + mic
- SD card reader
- TPM2 SLB9670
Tested:
- All of the hardware above
- SeaBIOS and TianoCore
- vboot with RO, RO+A, RO+A+B
- Booted Arch Linux
- Linux 5.6.10
- Linux LTS 5.4.38
What works / What works not:
- WLAN/BT does not work, but also not with vendor firmware
- Everything else works
Todos:
- Missing libgfxinit support
- Missing flashrom support
- Different configuration switches mentioned in ramstage.c
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9
---
M MAINTAINERS
A src/mainboard/clevo/Kconfig
A src/mainboard/clevo/Kconfig.name
A src/mainboard/clevo/cml-u/Kconfig
A src/mainboard/clevo/cml-u/Kconfig.name
A src/mainboard/clevo/cml-u/Makefile.inc
A src/mainboard/clevo/cml-u/acpi/ac.asl
A src/mainboard/clevo/cml-u/acpi/battery.asl
A src/mainboard/clevo/cml-u/acpi/buttons.asl
A src/mainboard/clevo/cml-u/acpi/ec.asl
A src/mainboard/clevo/cml-u/acpi/ec_ram.asl
A src/mainboard/clevo/cml-u/acpi/gpe.asl
A src/mainboard/clevo/cml-u/acpi/hid.asl
A src/mainboard/clevo/cml-u/acpi/keyboard.asl
A src/mainboard/clevo/cml-u/acpi/lid.asl
A src/mainboard/clevo/cml-u/acpi/mainboard.asl
A src/mainboard/clevo/cml-u/acpi/sleep.asl
A src/mainboard/clevo/cml-u/acpi/tbt.asl
A src/mainboard/clevo/cml-u/board_info.txt
A src/mainboard/clevo/cml-u/dsdt.asl
A src/mainboard/clevo/cml-u/fmds/vboot-ro.fmd
A src/mainboard/clevo/cml-u/fmds/vboot-roa.fmd
A src/mainboard/clevo/cml-u/fmds/vboot-roab.fmd
A src/mainboard/clevo/cml-u/ramstage.c
A src/mainboard/clevo/cml-u/romstage.c
A src/mainboard/clevo/cml-u/variants/n141cu/data.vbt
A src/mainboard/clevo/cml-u/variants/n141cu/devicetree.cb
A src/mainboard/clevo/cml-u/variants/n141cu/gma-mainboard.ads
A src/mainboard/clevo/cml-u/variants/n141cu/hda_verb.c
A src/mainboard/clevo/cml-u/variants/n141cu/include/gpio_table.h
30 files changed, 1,861 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/40581/26
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9
Gerrit-Change-Number: 40581
Gerrit-PatchSet: 26
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40581 )
Change subject: mainboard/clevo/n141cu: Add new mainboard
......................................................................
Patch Set 25:
This change is ready for review.
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9
Gerrit-Change-Number: 40581
Gerrit-PatchSet: 25
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Comment-Date: Tue, 05 May 2020 14:58:31 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41027 )
Change subject: soc/intel/jasperlake: Allow SD card power enable polarity configuration
......................................................................
soc/intel/jasperlake: Allow SD card power enable polarity configuration
SdCardPowerEnableActiveHigh is a UPD which controls polarity of SD card
power enable pin. Setting it 1 will set polarity of this pin as Active
high. This patch will allow to control it from devicetree so that it
can be set as per each board's requirement.
BUG=b:155595624
BRANCH=None
TEST=Build, boot JSLRVP, Verified UPD value from FSP log
Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
Change-Id: Id777a262651689952a217875e6606f67855fc2f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41027
Reviewed-by: Aamir Bohra <aamir.bohra(a)intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
Reviewed-by: V Sowmya <v.sowmya(a)intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/jasperlake/fsp_params.c
1 file changed, 4 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Aamir Bohra: Looks good to me, approved
V Sowmya: Looks good to me, approved
Maulik V Vaghela: Looks good to me, approved
Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index f525fd8..28dccab 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -136,10 +136,12 @@
/* SDCard related configuration */
dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
- if (!dev)
+ if (!dev) {
params->ScsSdCardEnabled = 0;
- else
+ } else {
params->ScsSdCardEnabled = dev->enabled;
+ params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh;
+ }
params->Device4Enable = config->Device4Enable;
--
To view, visit https://review.coreboot.org/c/coreboot/+/41027
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id777a262651689952a217875e6606f67855fc2f4
Gerrit-Change-Number: 41027
Gerrit-PatchSet: 9
Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-MessageType: merged
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40967 )
Change subject: superio/fintek/f81216h: Rename pnp_enter_conf_state()
......................................................................
superio/fintek/f81216h: Rename pnp_enter_conf_state()
This one does require a version with non-standard signature. Rename
to avoid conflict with upcoming standardization.
Note: There is currently no mainboard in tree using this super I/O.
Change-Id: I2d58d73eca0be1f4daf9106a1258274486f803a5
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/superio/fintek/f81216h/early_serial.c
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/40967/1
diff --git a/src/superio/fintek/f81216h/early_serial.c b/src/superio/fintek/f81216h/early_serial.c
index d2fa0fe..d97dd86 100644
--- a/src/superio/fintek/f81216h/early_serial.c
+++ b/src/superio/fintek/f81216h/early_serial.c
@@ -9,14 +9,14 @@
#define FINTEK_EXIT_KEY 0xAA
-static void pnp_enter_conf_state(pnp_devfn_t dev, u8 f81216h_entry_key)
+static void f81216h_pnp_enter_conf_state(pnp_devfn_t dev, u8 f81216h_entry_key)
{
u16 port = dev >> 8;
outb(f81216h_entry_key, port);
outb(f81216h_entry_key, port);
}
-static void pnp_exit_conf_state(pnp_devfn_t dev)
+void pnp_exit_conf_state(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(FINTEK_EXIT_KEY, port);
@@ -43,7 +43,7 @@
key = 0x77; /* try the hw default */
break;
}
- pnp_enter_conf_state(dev, key);
+ f81216h_pnp_enter_conf_state(dev, key);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
--
To view, visit https://review.coreboot.org/c/coreboot/+/40967
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2d58d73eca0be1f4daf9106a1258274486f803a5
Gerrit-Change-Number: 40967
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newchange
John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38777 )
Change subject: soc/intel/tigerlake: PMC mux control
......................................................................
soc/intel/tigerlake: PMC mux control
PMC supports messages that can be used for configuring the USB
Type-C Multiplexer/Demultiplexer.
Change-Id: I00c5f929b2eea5de3f8eba794dbe9b36c8083c52
Signed-off-by: John Zhao <john.zhao(a)intel.com>
---
A src/soc/intel/tigerlake/acpi/pmc_mux.asl
M src/soc/intel/tigerlake/acpi/southbridge.asl
2 files changed, 74 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/38777/1
diff --git a/src/soc/intel/tigerlake/acpi/pmc_mux.asl b/src/soc/intel/tigerlake/acpi/pmc_mux.asl
new file mode 100644
index 0000000..c105fe8
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/pmc_mux.asl
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+External (\_SB.PCI0, DeviceObj)
+
+Scope (\_SB.PCI0){
+
+ Device (PMC)
+ {
+ Name (_HID, "INTC1026")
+ Name (_DDN, "Intel(R) Tiger Lake IPC1 Controller")
+
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xFE000000, 0x00010000)
+ })
+
+ /* The OS mux driver will be bind to this device node. */
+ Device (MUX)
+ {
+ Name (_HID, "INTC105C")
+ Name (_DDN, "Intel(R) Tiger Lake North Mux-Agent")
+ /*
+ * Each connector shall have its own ACPI device entry (node),
+ * under the actual Mux device.
+ *
+ * These nodes are the ones that the USB Type-C port/connector
+ * devices will refer to in order to configure the mux.
+ */
+ Device (CON0)
+ {
+ Name (_ADR, 0)
+ /*
+ * These properties should have the values that the driver
+ * needs to supply to the PMC via IPC when the muxes are
+ * being configured.
+ */
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package() {
+ Package () {"usb2-port", 6},
+ Package () {"usb3-port", 3},
+ },
+ })
+ }
+ Device (CON1)
+ {
+ Name (_ADR, 1)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package() {
+ Package () {"usb2-port", 5},
+ Package () {"usb3-port", 2},
+ },
+ })
+ }
+ }
+ }
+}
diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl
index 8593d07..64e9722 100644
--- a/src/soc/intel/tigerlake/acpi/southbridge.asl
+++ b/src/soc/intel/tigerlake/acpi/southbridge.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
+ * Copyright (C) 2019-2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -51,3 +51,6 @@
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>
+
+/* PMC mux control */
+#include "pmc_mux.asl"
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I00c5f929b2eea5de3f8eba794dbe9b36c8083c52
Gerrit-Change-Number: 38777
Gerrit-PatchSet: 1
Gerrit-Owner: John Zhao <john.zhao(a)intel.com>
Gerrit-MessageType: newchange