coreboot-gerrit May 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/puff: add a region to cache SPD data
by Jamie Chen (Code Review) 05 May '20

05 May '20

Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40415 ) Change subject: mb/google/puff: add a region to cache SPD data ...................................................................... Patch Set 7: (4 comments) https://review.coreboot.org/c/coreboot/+/40415/4/src/mainboard/google/hatch… File src/mainboard/google/hatch/romstage_spd_smbus.c: https://review.coreboot.org/c/coreboot/+/40415/4/src/mainboard/google/hatch… PS4, Line 40: get_spd_sn(blk.addr_map[i], SPD_DRAM_DDR4, sn); > my 2 cents […] Done https://review.coreboot.org/c/coreboot/+/40415/4/src/mainboard/google/hatch… PS4, Line 46: DDR4_SPD_SN_OFF > can you make it to DDR4_SPD_SN_OFFSET? I think keep the DDR4_SPD_SN_OFF is better because there is the same naming style in spd_bin.h https://review.coreboot.org/c/coreboot/+/40415/4/src/mainboard/google/hatch… PS4, Line 85: (uintptr_t)blk.spd_array[0]; > i guess you can add few more tabs to get closer to the `=` in previous line Done https://review.coreboot.org/c/coreboot/+/40415/4/src/mainboard/google/hatch… PS4, Line 96: (uintptr_t)blk.spd_array[1]; > i guess you can add few more tabs to get closer to the `=` in previous line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/40415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d07fddf113a767d62394cb31e33b56f22f74351 Gerrit-Change-Number: 40415 Gerrit-PatchSet: 7 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 May 2020 03:32:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/puff: add a region to cache SPD data
by Jamie Chen (Code Review) 05 May '20

05 May '20

Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40415 ) Change subject: mb/google/puff: add a region to cache SPD data ...................................................................... Patch Set 7: (3 comments) https://review.coreboot.org/c/coreboot/+/40415/5/src/mainboard/google/hatch… File src/mainboard/google/hatch/romstage_spd_smbus.c: https://review.coreboot.org/c/coreboot/+/40415/5/src/mainboard/google/hatch… PS5, Line 28: SPD_CACHE > You can remove the underline here. […] Done https://review.coreboot.org/c/coreboot/+/40415/5/src/mainboard/google/hatch… PS5, Line 47: if (need_update_cache) > oh, one false case is load_spd_cache error. We don't need to update SPD cache when we cannot load SPD cache successfully. If there is a project without RW_SPD_CACHE region, it will keep the original flow here. https://review.coreboot.org/c/coreboot/+/40415/5/src/mainboard/google/hatch… PS5, Line 47: if (need_update_cache) > If dimm_changed, we need update cache anyway, right? Any condition will be dimm_changed but doesn't […] We don't need to update SPD cache when we cannot load SPD cache successfully. If there is a project without RW_SPD_CACHE region, it will keep the original flow here. -- To view, visit https://review.coreboot.org/c/coreboot/+/40415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d07fddf113a767d62394cb31e33b56f22f74351 Gerrit-Change-Number: 40415 Gerrit-PatchSet: 7 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 May 2020 03:21:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/spd_bin: add get_spd_sn function
by Jamie Chen (Code Review) 05 May '20

05 May '20

Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40414 ) Change subject: lib/spd_bin: add get_spd_sn function ...................................................................... Patch Set 6: (17 comments) > Patch Set 2: > > (4 comments) > > Just some minor things I noticed Jamie that you could address on your next iteration. Thank you. https://review.coreboot.org/c/coreboot/+/40414/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40414/2//COMMIT_MSG@9 PS2, Line 9: added > adds Done https://review.coreboot.org/c/coreboot/+/40414/2//COMMIT_MSG@10 PS2, Line 10: number. > This is only implemented for Intel, isn’t it? Please mention that in the commit message. Done https://review.coreboot.org/c/coreboot/+/40414/2//COMMIT_MSG@11 PS2, Line 11: > Where and how should this be used? To fill SMBIOS tables? It's for SPD cache. https://review.coreboot.org/c/coreboot/+/40414/3/src/include/spd_bin.h File src/include/spd_bin.h: https://review.coreboot.org/c/coreboot/+/40414/3/src/include/spd_bin.h@51 PS3, Line 51: void get_spd_sn(u8 addr, u8 dram_type, u8 *sn); > There is SPD_SN_LEN, but that is very implicit. […] I checked the SPD serial number lengths are the same in DDR3 and DDR4. In the future, if there is new type added and the length is not 4 bytes. We can add it with new patch. It likes the SPD_PAGE_LEN and SPD_PAGE_LEN_DDR4 case. https://review.coreboot.org/c/coreboot/+/40414/3/src/include/spd_bin.h@51 PS3, Line 51: dram_type > There's enum spd_memory_type in spd. […] Thanks for the info. I will remove the dram_type parameter and use SPD data to detect dram_type. https://review.coreboot.org/c/coreboot/+/40414/2/src/soc/intel/common/block… File src/soc/intel/common/block/smbus/smbuslib.c: https://review.coreboot.org/c/coreboot/+/40414/2/src/soc/intel/common/block… PS2, Line 79: int > unsigned Done https://review.coreboot.org/c/coreboot/+/40414/2/src/soc/intel/common/block… PS2, Line 80: if ((do_smbus_read_byte(SMBUS_IO_BASE, addr, 0) & 0xff) == 0xff) { > Don’t we already know from RAM training/initialization, what slots are populated? I think that it can use SPD byte 2 to identify the Dram type. So I will do it in the new pathset. https://review.coreboot.org/c/coreboot/+/40414/2/src/soc/intel/common/block… PS2, Line 80: if ((do_smbus_read_byte(SMBUS_IO_BASE, addr, 0) & 0xff) == 0xff) { > oh, typo.. […] Done https://review.coreboot.org/c/coreboot/+/40414/2/src/soc/intel/common/block… PS2, Line 82: addr << 1); > I think you can fit this on the line above. Done https://review.coreboot.org/c/coreboot/+/40414/2/src/soc/intel/common/block… PS2, Line 94: > s/\t/ / Done https://review.coreboot.org/c/coreboot/+/40414/2/src/soc/intel/common/block… PS2, Line 100: > s/\t/ / Done https://review.coreboot.org/c/coreboot/+/40414/2/src/soc/intel/common/block… PS2, Line 101: } > Print an error, if it’s neither DDR4 nor DDR3. Done https://review.coreboot.org/c/coreboot/+/40414/3/src/soc/intel/common/block… File src/soc/intel/common/block/smbus/smbuslib.c: https://review.coreboot.org/c/coreboot/+/40414/3/src/soc/intel/common/block… PS3, Line 41: dimm_preset > dimm_present. It will be removed in next patchset. https://review.coreboot.org/c/coreboot/+/40414/3/src/soc/intel/common/block… PS3, Line 43: < 0 > So even if the host controller is busy, it will still return < 0. […] I checked the return value is -1 (CB_ERR) when dimm is not present. I will change it to return a CB_ERR when addr is a zero and dram_type is not supported. Also it reported dimm is not present by sn=0xffffffff when smbus return value < 0. https://review.coreboot.org/c/coreboot/+/40414/3/src/soc/intel/common/block… PS3, Line 44: addr << 1 > If it's passed in as addr, I don't see a reason why would you print it out shifted left 1. […] Done https://review.coreboot.org/c/coreboot/+/40414/3/src/soc/intel/common/block… PS3, Line 91: void > suggestion: this should return a bool, false for the !dimm_present or unsupported enum spd_memory_ty […] I will do this at the next patchset. https://review.coreboot.org/c/coreboot/+/40414/3/src/soc/intel/common/block… PS3, Line 95: if (!dimm_preset(addr)) { > Please add add check for non-zero like #77. If addr is 0, smbus will return 0xff. Add the code to check if addr is a zero in new patchset. -- To view, visit https://review.coreboot.org/c/coreboot/+/40414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I406bba7cc56debbd9851d430f069e4fb96ec937c Gerrit-Change-Number: 40414 Gerrit-PatchSet: 6 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 May 2020 03:18:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/puff: add a region to cache SPD data
by EricR Lai (Code Review) 05 May '20

05 May '20

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40415 ) Change subject: mb/google/puff: add a region to cache SPD data ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/40415/5/src/mainboard/google/hatch… File src/mainboard/google/hatch/romstage_spd_smbus.c: https://review.coreboot.org/c/coreboot/+/40415/5/src/mainboard/google/hatch… PS5, Line 47: if (need_update_cache) > Thinking of this, dimm_changed default true then […] oh, one false case is load_spd_cache error. -- To view, visit https://review.coreboot.org/c/coreboot/+/40415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d07fddf113a767d62394cb31e33b56f22f74351 Gerrit-Change-Number: 40415 Gerrit-PatchSet: 7 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 May 2020 03:16:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/spd_bin: add get_spd_sn function
by Jamie Chen (Code Review) 05 May '20

05 May '20

Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Edward O'Callaghan, Angel Pons, Arthur Heymans, Kane Chen, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40414 to look at the new patch set (#6). Change subject: lib/spd_bin: add get_spd_sn function ...................................................................... lib/spd_bin: add get_spd_sn function This patch adds the get_spd_sn function. It's for reading SODIMM serial number. In spd_cache implementation it can use to get serial number before reading whole SPD by smbus. BUG=b:146457985 BRANCH=None TEST=Wrote sample code to get the serial number and ran on puff. It can get the serial number correctly. Change-Id: I406bba7cc56debbd9851d430f069e4fb96ec937c Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/include/spd_bin.h M src/soc/intel/common/block/smbus/smbuslib.c 2 files changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/40414/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/40414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I406bba7cc56debbd9851d430f069e4fb96ec937c Gerrit-Change-Number: 40414 Gerrit-PatchSet: 6 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd_bin: add get_spd_sn function
by build bot (Jenkins) (Code Review) 05 May '20

05 May '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40414 ) Change subject: lib/spd_bin: add get_spd_sn function ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/40414/5/src/include/spd_bin.h File src/include/spd_bin.h: https://review.coreboot.org/c/coreboot/+/40414/5/src/include/spd_bin.h@52 PS5, Line 52: /* It uses to get SODIMM serial number, caller needs to provide at least 4 bytes buffer for sn. trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/40414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I406bba7cc56debbd9851d430f069e4fb96ec937c Gerrit-Change-Number: 40414 Gerrit-PatchSet: 5 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 May 2020 02:40:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/puff: add a region to cache SPD data
by Jamie Chen (Code Review) 05 May '20

05 May '20

Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Edward O'Callaghan, Kane Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40415 to look at the new patch set (#6). Change subject: mb/google/puff: add a region to cache SPD data ...................................................................... mb/google/puff: add a region to cache SPD data This patch adds a SPI rom region RW_SPD_CACHE on Puff and it can be used on spd_cache to reduce reading SPD data from SODIMM by smbus. It's for saving the boot time and it can be used to trigger MRC retraining when memory DIMM is changed. BUG=b:146457985 BRANCH=None TEST=Build puff successfully and verified below two items. 1. To change memory DIMM can trigger retraining. 2. one DIMM save the boot time : 158ms two DIMM save the boot time : 265ms Change-Id: I8d07fddf113a767d62394cb31e33b56f22f74351 Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/mainboard/google/hatch/Kconfig A src/mainboard/google/hatch/chromeos-16MiB-spd.fmd A src/mainboard/google/hatch/chromeos-spd.fmd M src/mainboard/google/hatch/romstage_spd_smbus.c 4 files changed, 131 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/40415/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/40415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d07fddf113a767d62394cb31e33b56f22f74351 Gerrit-Change-Number: 40415 Gerrit-PatchSet: 6 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd_bin: add get_spd_sn function
by Jamie Chen (Code Review) 05 May '20

05 May '20

Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Edward O'Callaghan, Angel Pons, Arthur Heymans, Kane Chen, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40414 to look at the new patch set (#5). Change subject: lib/spd_bin: add get_spd_sn function ...................................................................... lib/spd_bin: add get_spd_sn function This patch adds the get_spd_sn function. It's for reading SODIMM serial number. In spd_cache implementation it can use to get serial number before reading whole SPD by smbus. BUG=b:146457985 BRANCH=None TEST=Wrote sample code to get the serial number and ran on puff. It can get the serial number correctly. Change-Id: I406bba7cc56debbd9851d430f069e4fb96ec937c Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/include/spd_bin.h M src/soc/intel/common/block/smbus/smbuslib.c 2 files changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/40414/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/40414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I406bba7cc56debbd9851d430f069e4fb96ec937c Gerrit-Change-Number: 40414 Gerrit-PatchSet: 5 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: elog: Add new elog types for CSME-initiated host reset
by Tim Wawrzynczak (Code Review) 05 May '20

05 May '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40687 ) Change subject: elog: Add new elog types for CSME-initiated host reset ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddae1c7cbc71ce10b126a1e05abf9269e8187a38 Gerrit-Change-Number: 40687 Gerrit-PatchSet: 3 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 May 2020 02:08:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 05 May '20

05 May '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Sridhar Siricilla, Rizwan Qureshi, Subrata Banik, Balaji Manigandan, Aamir Bohra, Patrick Rudolph, V Sowmya, Andrey Petrov, Jamie Ryu, Martin Roth, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35403 to look at the new patch set (#81). Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... soc/intel/common/basecode: Implement CSE update flow The following changes have been done in this patch: Get the CSE partition info containing version of CSE RW using GET_BOOT_PARTITION_INFO HECI command Get the me_rw.version from the currently selected RW slot. If the version from the above 2 locations don't match start the update - If CSE's current boot partition is not RO, then * Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. * Send global reset command to reset the system. - Enable HMRFPO (Host ME Region Flash Protection Override) operation mode using HMRFPO_ENABLE HECI command - Erase and Copy the CBFS CSE RW to CSE RW partition - Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command - Trigger global reset The system should boot with the Updated CSE RW partition. TEST=Verified basic update flows on hatch and helios. BUG=b:111330995 Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- A Documentation/soc/intel/cse_fw_update/Layout_after.svg A Documentation/soc/intel/cse_fw_update/Layout_before.svg A Documentation/soc/intel/cse_fw_update/cse_fw_update.md M Documentation/soc/intel/index.md M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/custom_bp.c 6 files changed, 703 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/81 -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 81 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2020