coreboot-gerrit May 2020

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Change in coreboot[master]: mb/google/volteer: add generic SPDs
by Nick Vaccaro (Code Review) 06 May '20

06 May '20

Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Duncan Laurie, Dossym Nurmukhanov, Srinidhi N Kaushik, Raj Astekar, Shreesh Chhabbi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40463 to look at the new patch set (#19). Change subject: mb/google/volteer: add generic SPDs ...................................................................... mb/google/volteer: add generic SPDs Add SPDs created by Intel for different memory module options. NOTE: Renamed Intel's SPD_LPDDR4X_200b_2R_32Gb_QDP_4266.spd.hex to SPD_LPDDR4X_200b_2R_32Gb_87MinCAS_QDP_4267.spd.hex to remain consistent with regard to dram frequency in filename (speed is 4267, not 4266). BUG=b:147857288 TEST=none Change-Id: Ib4cd148e28efe458f2b312a7f1c5b6d71e8ef433 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- A src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_DDP_3733.spd.hex A src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_DDP_4267.spd.hex A src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_2R_32Gb_87MinCAS_QDP_4267.spd.hex A src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_2R_32Gb_QDP_3733.spd.hex A src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_2R_32Gb_QDP_4267.spd.hex A src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_2R_64Gb_ODP_3733.spd.hex A src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_2R_64Gb_ODP_4267.spd.hex A src/mainboard/google/volteer/spd/SPD_LPDDR4X_556b_1R_32Gb_QDP_3733.spd.hex A src/mainboard/google/volteer/spd/SPD_LPDDR4X_556b_1R_32Gb_QDP_4267.spd.hex A src/mainboard/google/volteer/spd/SPD_LPDDR4X_556b_2R_48Gb_ODP_3733.spd.hex A src/mainboard/google/volteer/spd/SPD_LPDDR4X_556b_2R_48Gb_ODP_4267.spd.hex A src/mainboard/google/volteer/spd/SPD_LPDDR4X_556b_2R_64Gb_ODP_3733.spd.hex A src/mainboard/google/volteer/spd/SPD_LPDDR4X_556b_2R_64Gb_ODP_4267.spd.hex 13 files changed, 416 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40463/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/40463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4cd148e28efe458f2b312a7f1c5b6d71e8ef433 Gerrit-Change-Number: 40463 Gerrit-PatchSet: 19 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: memrange: Add support for stealing required memory from given ranges
by Furquan Shaikh (Code Review) 06 May '20

06 May '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39484 ) Change subject: memrange: Add support for stealing required memory from given ranges ...................................................................... memrange: Add support for stealing required memory from given ranges This change adds support for memranges_steal() which allows the user to steal memory from the list of available ranges by providing a set of constraints (limit, size, alignment, tag). It tries to find the first big enough range that can satisfy the constraints, creates a hole as per the request and returns base of the stolen memory. BUG=b:149186922 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Ibe9cfae18fc6101ab2e7e27233e45324c8117708 --- M src/include/memrange.h M src/lib/memrange.c 2 files changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/39484/1 diff --git a/src/include/memrange.h b/src/include/memrange.h index fba77af..9b1d1d2 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -16,6 +16,7 @@ #define MEMRANGE_H_ #include <device/resource.h> +#include <stdbool.h> /* A memranges structure consists of a list of range_entry(s). The structure * is exposed so that a memranges can be used on the stack if needed. */ @@ -166,4 +167,17 @@ /* Returns next entry after the provided entry. NULL if r is last. */ struct range_entry *memranges_next_entry(struct memranges *ranges, const struct range_entry *r); + +/* Steals memory from the available list in given ranges as per the constraints: + * limit = Limit beyond which the stolen memory cannot grow. + * size = Requested size for the stolen memory. + * align = Alignment requirements for the starting address of the stolen memory. + * tag = Use a range that matches the given tag. + * + * If it is not possible to fulfill the request as per given constraints, this function returns + * false. Else, it sets the base address of stolen memory in stolen_base, creates a hole of + * required size at the stolen_base and returns true to indicate success. */ +bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, size_t align, + unsigned long tag, resource_t *stolen_base); + #endif /* MEMRANGE_H_ */ diff --git a/src/lib/memrange.c b/src/lib/memrange.c index a76f24c..b57c6cb 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -385,3 +385,49 @@ { return r->next; } + +/* Find a range entry that satisfies the given constraints to fit a hole that matches the + * required alignment, is big enough, does not exceed the limit and has a matching tag. */ +static const struct range_entry *memranges_find_entry(struct memranges *ranges, + resource_t limit, resource_t size, + size_t align, unsigned long tag) +{ + const struct range_entry *r; + resource_t base, end; + + memranges_each_entry(r, ranges) { + + if (r->tag != tag) + continue; + + base = ALIGN_UP(r->begin, align); + end = base + size - 1; + + if (end > r->end) + continue; + + if (end > limit) + continue; + + return r; + } + + return NULL; +} + +bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, size_t align, + unsigned long tag, resource_t *stolen_base) +{ + resource_t base; + const struct range_entry *r = memranges_find_entry(ranges, limit, size, align, tag); + + if (r == NULL) + return false; + + base = ALIGN_UP(r->begin, align); + + memranges_create_hole(ranges, base, size); + *stolen_base = base; + + return true; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe9cfae18fc6101ab2e7e27233e45324c8117708 Gerrit-Change-Number: 39484 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/n141cu: Add new Comet Lake mainboard
by Felix Singer (Code Review) 06 May '20

06 May '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40581 to look at the new patch set (#30). Change subject: mb/clevo/n141cu: Add new Comet Lake mainboard ...................................................................... mb/clevo/n141cu: Add new Comet Lake mainboard Add a new mainboard with the following specs: - Intel i5-10210U (Comet Lake) - Intel UHD graphics - Intel HD audio - 1x Ethernet 1Gbit/s - 1x SATA3 - 1x M.2 slot x4 (PCIe/SATA) - 1x M.2 slot x1 (WLAN/BT) - 1x 3G/LTE - USB2/3 - Thunderbolt - HDMI, mDP - CCD camera + mic - SD card reader - TPM2 SLB9670 The ACPI code has been taken from System76 CML-U mainboard series. Tested: - Clevo N141CU / TUXEDO InfinityBook Pro 14 v5 - SeaBIOS and TianoCore - vboot with RO, RO+A, RO+A+B - Booted Arch Linux - Linux 5.6.10 - Linux LTS 5.4.38 What works / What works not: - WLAN/BT does not work, but also not with vendor firmware - Everything else works Todos: - Missing libgfxinit support - Missing flashrom support - Different configuration switches mentioned in ramstage.c Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 --- M MAINTAINERS A src/mainboard/clevo/Kconfig A src/mainboard/clevo/Kconfig.name A src/mainboard/clevo/cml-u/Kconfig A src/mainboard/clevo/cml-u/Kconfig.name A src/mainboard/clevo/cml-u/Makefile.inc A src/mainboard/clevo/cml-u/acpi/ac.asl A src/mainboard/clevo/cml-u/acpi/battery.asl A src/mainboard/clevo/cml-u/acpi/buttons.asl A src/mainboard/clevo/cml-u/acpi/ec.asl A src/mainboard/clevo/cml-u/acpi/ec_ram.asl A src/mainboard/clevo/cml-u/acpi/gpe.asl A src/mainboard/clevo/cml-u/acpi/hid.asl A src/mainboard/clevo/cml-u/acpi/keyboard.asl A src/mainboard/clevo/cml-u/acpi/lid.asl A src/mainboard/clevo/cml-u/acpi/mainboard.asl A src/mainboard/clevo/cml-u/acpi/sleep.asl A src/mainboard/clevo/cml-u/acpi/tbt.asl A src/mainboard/clevo/cml-u/board_info.txt A src/mainboard/clevo/cml-u/dsdt.asl A src/mainboard/clevo/cml-u/fmds/vboot-ro.fmd A src/mainboard/clevo/cml-u/fmds/vboot-roa.fmd A src/mainboard/clevo/cml-u/fmds/vboot-roab.fmd A src/mainboard/clevo/cml-u/ramstage.c A src/mainboard/clevo/cml-u/romstage.c A src/mainboard/clevo/cml-u/variants/n141cu/data.vbt A src/mainboard/clevo/cml-u/variants/n141cu/devicetree.cb A src/mainboard/clevo/cml-u/variants/n141cu/gma-mainboard.ads A src/mainboard/clevo/cml-u/variants/n141cu/hda_verb.c A src/mainboard/clevo/cml-u/variants/n141cu/include/gpio_table.h 30 files changed, 1,705 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/40581/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/40581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 Gerrit-Change-Number: 40581 Gerrit-PatchSet: 30 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: Allow SataEnable to be filled from devicetree
by Furquan Shaikh (Code Review) 06 May '20

06 May '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41029 ) Change subject: soc/intel/jasperlake: Allow SataEnable to be filled from devicetree ...................................................................... Patch Set 6: (2 comments) https://review.coreboot.org/c/coreboot/+/41029/6/src/soc/intel/jasperlake/f… File src/soc/intel/jasperlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/41029/6/src/soc/intel/jasperlake/f… PS6, Line 139: dev->enabled If we can use dev->enabled, is there any point in using SataEnable config? Can we drop it and just use dev->enabled instead? https://review.coreboot.org/c/coreboot/+/41029/6/src/soc/intel/jasperlake/f… PS6, Line 140: SataEnable I believe there are generally more params that you would have to set when Sata is being enabled? Like SataMode, SataPortsDevSlp and so on. -- To view, visit https://review.coreboot.org/c/coreboot/+/41029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f7e7508b8cd483508293ee3e7b760574d8f025f Gerrit-Change-Number: 41029 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 May 2020 17:34:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Enable EARLY_EC_SYNC
by Nick Vaccaro (Code Review) 06 May '20

06 May '20

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41078 ) Change subject: mb/google/volteer: Enable EARLY_EC_SYNC ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/41078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb97c1d57220f7fd74131a5aee450b1ab4b1c982 Gerrit-Change-Number: 41078 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 May 2020 16:46:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: set GPP_B11 to be GPI
by Nick Vaccaro (Code Review) 06 May '20

06 May '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40107 ) Change subject: mb/google/volteer: set GPP_B11 to be GPI ...................................................................... mb/google/volteer: set GPP_B11 to be GPI Set the EC_WP_OD GPIO to be GPI. BUG=b:152876091 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel, then verify the following : cr50 console$ wp disable EC console$ gpioget EC_WP_L:1 servo$ dut-control fw_wp: fw_wp:off Probe PCH_WP_OD at R189: 0V crossystem wpsw_cur: 0 cr50 console$ wp enable EC console$ gpioget EC_WP_L: 0 servo$ dut-control fw_wp: fw_wp:on Probe PCH_WP_OD at R189: 3.18V crossystem wpsw_cur: 1 Change-Id: Ibeb8a0a9bad35b3682143b983e9dbd727fa0c189 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/40107/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index fff0381..c143540 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -78,7 +78,7 @@ /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* B11 : PMCALERT# ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + PAD_CFG_GPI(GPP_B11, NONE, DEEP), /* B12 : SLP_S0# ==> SLP_S0_L */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L */ @@ -410,7 +410,7 @@ PAD_CFG_GPI(GPP_A17, NONE, DEEP), /* B11 : PMCALERT# ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + PAD_CFG_GPI(GPP_B11, NONE, DEEP), /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/40107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeb8a0a9bad35b3682143b983e9dbd727fa0c189 Gerrit-Change-Number: 40107 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: TGL: Make the GPIO asl table in sync with kernel
by Shaunak Saha (Code Review) 06 May '20

06 May '20

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39801 ) Change subject: TGL: Make the GPIO asl table in sync with kernel ...................................................................... TGL: Make the GPIO asl table in sync with kernel Kernel pinctrl driver changed for Tiger lake and went to old scheme. Kernel patch: https://chromium-review.googlesource.com/c/chromiumos/ third_party/kernel/+/2116670 BRANCH=none TEST=Build and boot tgl board. In /sys/kernel/debug/pinctrl verify INTC34C5:00 listing all the pins. Change-Id: I9f1d399ff7380125ad5b935f9590a7d9cc442b04 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/ripto/gpio.c M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/include/soc/gpio.h 4 files changed, 149 insertions(+), 101 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/39801/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index fff0381..b332856 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -459,8 +459,8 @@ } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM1_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM1_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; const struct cros_gpio *__weak variant_cros_gpios(size_t *num) diff --git a/src/mainboard/google/volteer/variants/ripto/gpio.c b/src/mainboard/google/volteer/variants/ripto/gpio.c index 4159cb8..290aa3b 100644 --- a/src/mainboard/google/volteer/variants/ripto/gpio.c +++ b/src/mainboard/google/volteer/variants/ripto/gpio.c @@ -455,8 +455,8 @@ } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM0_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; const struct cros_gpio *variant_cros_gpios(size_t *num) diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl index 9bf0c60..344a096 100644 --- a/src/soc/intel/tigerlake/acpi/gpio.asl +++ b/src/soc/intel/tigerlake/acpi/gpio.asl @@ -17,101 +17,153 @@ #include <intelblocks/gpio.h> #include "gpio_op.asl" -Device (GCM0) -{ - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 0) - Name (_DDN, "GPIO Controller Community 0") - - Name (RBUF, ResourceTemplate() +#if CONFIG(SOC_INTEL_TIGERLAKE) + Device (GPIO) { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + Name (_HID, "INT34C5") + Name (_UID, 0) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE + + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE + + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } + } +#else + Device (GCM0) + { + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 0) + Name (_DDN, "GPIO Controller Community 0") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } + } + + Device (GCM1) + { + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 1) + Name (_DDN, "GPIO Controller Community 1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } + } + + Device (GCM4) + { + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 4) + Name (_DDN, "GPIO Controller Community 4") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } + } + + Device (GCM5) + { + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 5) + Name (_DDN, "GPIO Controller Community 5") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { - CreateDWordField (^RBUF, ^COM0._BAS, BAS0) - BAS0 = ^^PCRB (PID_GPIOCOM0) - Return (^RBUF) + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + BAS5 = ^^PCRB (PID_GPIOCOM5) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } } - Method (_STA) - { - Return (0xF) - } -} - -Device (GCM1) -{ - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 1) - Name (_DDN, "GPIO Controller Community 1") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { - CreateDWordField (^RBUF, ^COM1._BAS, BAS1) - BAS1 = ^^PCRB (PID_GPIOCOM1) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} - -Device (GCM4) -{ - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 4) - Name (_DDN, "GPIO Controller Community 4") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { - CreateDWordField (^RBUF, ^COM4._BAS, BAS4) - BAS4 = ^^PCRB (PID_GPIOCOM4) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} - -Device (GCM5) -{ - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 5) - Name (_DDN, "GPIO Controller Community 5") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { - CreateDWordField (^RBUF, ^COM5._BAS, BAS5) - BAS5 = ^^PCRB (PID_GPIOCOM5) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} +#endif /* * Get GPIO DW0 Address diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h index 7a6df7c..dee59a3 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio.h +++ b/src/soc/intel/tigerlake/include/soc/gpio.h @@ -20,11 +20,7 @@ #if CONFIG(SOC_INTEL_TIGERLAKE) - #define CROS_GPIO_NAME "INT34C5" - #define CROS_GPIO_COMM0_NAME "INT34C5:00" - #define CROS_GPIO_COMM1_NAME "INT34C5:01" - #define CROS_GPIO_COMM4_NAME "INT34C5:02" - #define CROS_GPIO_COMM5_NAME "INT34C5:03" + #define CROS_GPIO_DEVICE_NAME "INT34C5:00" #elif CONFIG(SOC_INTEL_JASPERLAKE) -- To view, visit https://review.coreboot.org/c/coreboot/+/39801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f1d399ff7380125ad5b935f9590a7d9cc442b04 Gerrit-Change-Number: 39801 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

6 38

Change in coreboot[master]: tests: Add lib/string-test test case
by Name of user not set (Code Review) 06 May '20

06 May '20

Name of user not set #1002873 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40538 ) Change subject: tests: Add lib/string-test test case ...................................................................... tests: Add lib/string-test test case This commit's purpose is to show basic example of how unit testing may be applied for coreboot project. It adds test harness for lib/string.c module. In order to run this example, one need to install (beside general coreboot dependencies) cmocka package: sudo apt-get install -y libcmocka-dev sudo emerge dev-util/cmocka yum install libcmocka-devel After invoking: make unit-tests report from unit test will be created and shown on the screen This test harness definitely isn't complete, as it only checks for some functions within module. Purpose of this code is only an example and a starting point for a discussion about implementation. Signed-off-by: Jan Dabros <jsd(a)semihalf.com> Change-Id: Ibf5554d1e99a393721a66bdd35af0122c2e412c4 --- A tests/include/mocks/assert.h A tests/lib/Makefile.inc A tests/lib/string-test.c 3 files changed, 152 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/40538/1 diff --git a/tests/include/mocks/assert.h b/tests/include/mocks/assert.h new file mode 100644 index 0000000..0b0499b --- /dev/null +++ b/tests/include/mocks/assert.h @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASSERT_H__ +#define __ASSERT_H__ + +#include <arch/hlt.h> +#include <console/console.h> + +/* TODO: Fix vendorcode headers to not define macros coreboot uses or to be more + properly isolated. */ +#ifdef ASSERT +#undef ASSERT +#endif + +/* GCC and CAR versions */ +#define ASSERT(x) { \ + if (!(x)) { \ + printk(BIOS_EMERG, "ASSERTION ERROR: file '%s'" \ + ", line %d\n", __FILE__, __LINE__); \ + if (CONFIG(FATAL_ASSERTS)) \ + hlt(); \ + } \ +} + +#define ASSERT_MSG(x, msg) { \ + if (!(x)) { \ + printk(BIOS_EMERG, "ASSERTION ERROR: file '%s'" \ + ", line %d\n", __FILE__, __LINE__); \ + printk(BIOS_EMERG, "%s", msg); \ + if (CONFIG(FATAL_ASSERTS)) \ + hlt(); \ + } \ +} + +/* Compile-out BUG() macro, since checkpatch is not happy with it, + * to be revised later. + */ +/* #define BUG() { \ + printk(BIOS_EMERG, "ERROR: BUG ENCOUNTERED at file '%s'"\ + ", line %d\n", __FILE__, __LINE__); \ + if (CONFIG(FATAL_ASSERTS)) \ + hlt(); \ +} */ + +#define assert(statement) ASSERT(statement) + +/* + * Original dead_code() from src/include/assert.h breaks compilation when + * non-intended code is compiled in. This is not suitable for unit testing, + * thus we are changing this macro to be run-time assert. mock_assert() allows + * Cmocka to expect such assert and pass test, when dead_code() is correctly + * called. + */ + +extern void mock_assert(const int result, const char * const expression, + const char * const file, const int line); + +#define dead_code() \ + mock_assert(0, "dead_code", __FILE__, __LINE__) + +#undef assert +#define assert(expression) \ + mock_assert((int)(expression), #expression, __FILE__, __LINE__) + +/* This can be used in the context of an expression of type 'type'. */ +#define dead_code_t(type) ({ \ + dead_code(); \ + *(type *)(uintptr_t)0; \ +}) + +#endif // __ASSERT_H__ diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc new file mode 100644 index 0000000..5f73446 --- /dev/null +++ b/tests/lib/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# object filest should be under build/tests/ build/test/src/ build/test/run/ +# two examples - first should be simply string.c, second should use -wrap + +tests += string-test + +string-test-srcs += tests/lib/string-test.c +string-test-srcs += src/lib/string.c diff --git a/tests/lib/string-test.c b/tests/lib/string-test.c new file mode 100644 index 0000000..3ce0563 --- /dev/null +++ b/tests/lib/string-test.c @@ -0,0 +1,49 @@ +#include <stdarg.h> +#include <stddef.h> +#include <setjmp.h> +#include <cmocka.h> + +#include <string.h> + +struct strings_t { + char *str; + size_t size; +} strings[] = { + {"coreboot", 8}, + {"is\0very", 2}, /* strlen should be 2 because of the embedded \0 */ + {"nice\n", 5} +}; + +static void test_strlen_strings(void **state) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(strings); i++) + assert_int_equal(strings[i].size, strlen(strings[i].str)); +} + +/* Since strdup() requires malloc() it may only be invoked during ramstage + * phase. Expect dead_code/assert invocation otherwise. + */ +static void test_strdup(void **state) +{ +#ifdef __RAMSTAGE__ + char str[] = "Hello coreboot\n"; + char *duplicate; + + duplicate = strdup(str); + assert_int_equal(0, memcmp(str, duplicate, strlen(str))); +#else + expect_assert_failure(strdup(NULL)); +#endif +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_strlen_strings), + cmocka_unit_test(test_strdup), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/40538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf5554d1e99a393721a66bdd35af0122c2e412c4 Gerrit-Change-Number: 40538 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002873 Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 28

Change in coreboot[master]: {arch,commonlib}/{Kconfig,Makefile.inc}: Use GPLv2 headers with SPDX ...
by HAOUAS Elyes (Code Review) 06 May '20

06 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41087 ) Change subject: {arch,commonlib}/{Kconfig,Makefile.inc}: Use GPLv2 headers with SPDX header ...................................................................... {arch,commonlib}/{Kconfig,Makefile.inc}: Use GPLv2 headers with SPDX header Change-Id: Ic67dd61165a901233e7bc3e838e3d5931c7ac385 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/Kconfig M src/arch/arm/armv4/Kconfig M src/arch/arm/armv7/Kconfig M src/arch/arm64/Kconfig M src/arch/arm64/armv8/Kconfig M src/arch/ppc64/Kconfig M src/arch/riscv/Kconfig M src/commonlib/Makefile.inc 8 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/41087/1 diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index ed838a5..f22d83c 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -1,3 +1,6 @@ +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only + config ARCH_ARM bool diff --git a/src/arch/arm/armv4/Kconfig b/src/arch/arm/armv4/Kconfig index 0b50165..621c173 100644 --- a/src/arch/arm/armv4/Kconfig +++ b/src/arch/arm/armv4/Kconfig @@ -1,3 +1,6 @@ +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only + config ARCH_BOOTBLOCK_ARMV4 bool select ARCH_BOOTBLOCK_ARM diff --git a/src/arch/arm/armv7/Kconfig b/src/arch/arm/armv7/Kconfig index 6d5fb9e..574b5e9 100644 --- a/src/arch/arm/armv7/Kconfig +++ b/src/arch/arm/armv7/Kconfig @@ -1,3 +1,6 @@ +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only + config ARCH_BOOTBLOCK_ARMV7 bool select ARCH_BOOTBLOCK_ARM diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index 588e8ce..2e95f4a 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -1,3 +1,6 @@ +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only + config ARCH_ARM64 bool diff --git a/src/arch/arm64/armv8/Kconfig b/src/arch/arm64/armv8/Kconfig index f70b529..520a863 100644 --- a/src/arch/arm64/armv8/Kconfig +++ b/src/arch/arm64/armv8/Kconfig @@ -1,3 +1,6 @@ +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only + config ARCH_BOOTBLOCK_ARMV8_64 bool select ARCH_BOOTBLOCK_ARM64 diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index 44dbb1d..e4045db 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -1,3 +1,6 @@ +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only + config ARCH_PPC64 bool diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 8369afe..d57fae5 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -1,3 +1,6 @@ +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only + config ARCH_RISCV_RV64 bool select ARCH_RISCV diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 5bd6cf9..aa6e510 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -1,3 +1,6 @@ +# This file is part of the coreboot project. +# SPDX-License-Identifier: GPL-2.0-only + subdirs-y += storage bootblock-y += mem_pool.c -- To view, visit https://review.coreboot.org/c/coreboot/+/41087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic67dd61165a901233e7bc3e838e3d5931c7ac385 Gerrit-Change-Number: 41087 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mb/clevo/n141cu: Add new Comet Lake mainboard
by Felix Singer (Code Review) 06 May '20

06 May '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40581 ) Change subject: mb/clevo/n141cu: Add new Comet Lake mainboard ...................................................................... Patch Set 28: (5 comments) https://review.coreboot.org/c/coreboot/+/40581/27//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40581/27//COMMIT_MSG@7 PS27, Line 7: mainboard/clevo/n141cu: Add new mainboard > Add new Comet Lake mainboard Done https://review.coreboot.org/c/coreboot/+/40581/27//COMMIT_MSG@7 PS27, Line 7: mainboard > mb Done https://review.coreboot.org/c/coreboot/+/40581/27//COMMIT_MSG@24 PS27, Line 24: > Mention that you base this on a System76 board? Done https://review.coreboot.org/c/coreboot/+/40581/27//COMMIT_MSG@26 PS27, Line 26: - All of the hardware above > It is a TUXEDO notebook indeed :) I will add that for reference later. Done https://review.coreboot.org/c/coreboot/+/40581/27/src/mainboard/clevo/cml-u… File src/mainboard/clevo/cml-u/acpi/ac.asl: https://review.coreboot.org/c/coreboot/+/40581/27/src/mainboard/clevo/cml-u… PS27, Line 15: * GNU General Public License for more details. > Use SPDX headers? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/40581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 Gerrit-Change-Number: 40581 Gerrit-PatchSet: 28 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 May 2020 13:55:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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