Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41037 )
Change subject: mb/google/dedede: Enable PMC, P2SB and PCH SPI devices
......................................................................
mb/google/dedede: Enable PMC, P2SB and PCH SPI devices
BUG=None
TEST=Build and boot the mainboard.
Change-Id: I1aae4adf1c13fd4ff58aa38a877f34e142f320f1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/41037/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index cfe221f..c891e6e 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -289,11 +289,11 @@
device pnp 0c09.0 on end
end
end # eSPI Interface
- device pci 1f.1 off end # P2SB
- device pci 1f.2 off end # Power Management Controller
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
device pci 1f.3 off end # Intel HDA/cAVS
device pci 1f.4 off end # SMBus
- device pci 1f.5 off end # PCH SPI
+ device pci 1f.5 on end # PCH SPI
device pci 1f.7 off end # Intel Trace Hub
end
end
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41038 )
Change subject: mb/purism/librem_{bdw,skl}: select MAINBOARD_HAS_TPM1
......................................................................
mb/purism/librem_{bdw,skl}: select MAINBOARD_HAS_TPM1
Current model Librems all have a TPM 1.2 module, so select
it at the board level to avoid having to do so in .config.
Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm>
Change-Id: Iab8b39c39aef2a3fc182f1a50091f84f2151a394
---
M src/mainboard/purism/librem_bdw/Kconfig
M src/mainboard/purism/librem_skl/Kconfig
2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/41038/1
diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig
index 27ae21f..dcfe78e 100644
--- a/src/mainboard/purism/librem_bdw/Kconfig
+++ b/src/mainboard/purism/librem_bdw/Kconfig
@@ -8,6 +8,7 @@
select INTEL_GMA_HAVE_VBT
select INTEL_INT15
select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_HAS_TPM1
select SOC_INTEL_BROADWELL
if BOARD_PURISM_BASEBOARD_LIBREM_BDW
diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig
index 7a73823..c1a9aec 100644
--- a/src/mainboard/purism/librem_skl/Kconfig
+++ b/src/mainboard/purism/librem_skl/Kconfig
@@ -6,6 +6,7 @@
select INTEL_GMA_HAVE_VBT
select MAINBOARD_HAS_LIBGFXINIT
select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_TPM1
select NO_UART_ON_SUPERIO
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_KABYLAKE if BOARD_PURISM_LIBREM13_V4 || BOARD_PURISM_LIBREM15_V4
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Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40308 )
Change subject: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data
......................................................................
Patch Set 28:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40308/27/src/drivers/ocp/dmi/smbio…
File src/drivers/ocp/dmi/smbios.c:
https://review.coreboot.org/c/coreboot/+/40308/27/src/drivers/ocp/dmi/smbio…
PS27, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
> maybe : […]
Done
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Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Jonathan Zhang, Maxim Polyakov, David Hendricks, Jingle Hsu, Morgan Jang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40308
to look at the new patch set (#28).
Change subject: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data
......................................................................
drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data
It implements the SMBIOS IPMI FRU mapping table defined in
https://www.opencompute.org/documents/facebook-xeon-motherboard-v31
22.3 SMBIOS FRU mapping table.
Need to configure the correct values for FRU_DEVICE_ID and BMC_KCS_BASE.
Tested on OCP Tioga Pass.
Change-Id: I08c958dfad83216cd12545760a19d205efc2515b
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
---
A src/drivers/ocp/dmi/Kconfig
A src/drivers/ocp/dmi/Makefile.inc
A src/drivers/ocp/dmi/ocp_dmi.h
A src/drivers/ocp/dmi/smbios.c
4 files changed, 242 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/40308/28
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HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40308 )
Change subject: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data
......................................................................
Patch Set 27:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40308/27/src/drivers/ocp/dmi/smbio…
File src/drivers/ocp/dmi/smbios.c:
https://review.coreboot.org/c/coreboot/+/40308/27/src/drivers/ocp/dmi/smbio…
PS27, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
maybe :
/* This file is part of the coreboot project. */
/* SPDX-License-Identifier: GPL-2.0-or-later */
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Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40414 )
Change subject: lib/spd_bin: add get_spd_sn function
......................................................................
Patch Set 6:
(5 comments)
https://review.coreboot.org/c/coreboot/+/40414/4/src/soc/intel/common/block…
File src/soc/intel/common/block/smbus/smbuslib.c:
https://review.coreboot.org/c/coreboot/+/40414/4/src/soc/intel/common/block…
PS4, Line 85: return sn == 0x00000000, if addr is 0x0.
: return sn == 0xffffffff, if dimm is not present. */
> How about just return values from the function?
In new patchset, it will return a CB_ERR and sn will become u32 pointer.
return CB_SUCCESS, sn is the serial number and sn=0xffffffff if the dimm is not present.
return CB_ERR, if dram_type is not supported or addr is a zero.
Is it good for you?
https://review.coreboot.org/c/coreboot/+/40414/4/src/soc/intel/common/block…
PS4, Line 87: u8 *sn
> This still looks weird. […]
In new patchset, it will return a CB_ERR and sn will become u32 pointer.
return CB_SUCCESS, sn is the serial number and sn=0xffffffff if the dimm is not present.
return CB_ERR, if dram_type is not supported or addr is a zero.
Is it good for you?
https://review.coreboot.org/c/coreboot/+/40414/4/src/soc/intel/common/block…
PS4, Line 92: /* smbus will return 0xff if addr is zero */
: if (addr == 0x00) {
: memset(sn, 0, SPD_SN_LEN);
: return;
: }
> do_smbus_read_byte not check the address 0x00 but will return 0xff.. […]
As Eric mentioned, I saw return value -1(0xffffffff) when I removed the DIMM. And it returns 0x000000ff when addr is a zero.
Now I added the code for checking if addr is a zero, but I also thought if we can just put assert here.
assert(addr != 0x00);
How do you think?
https://review.coreboot.org/c/coreboot/+/40414/4/src/soc/intel/common/block…
PS4, Line 99: dram_type
> This is a u8, but do_dmbus_read_byte returns an int (where negative numbers are the error values), s […]
Done
https://review.coreboot.org/c/coreboot/+/40414/4/src/soc/intel/common/block…
PS4, Line 120: Unsupport
> Unsupported
Done
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Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41078 )
Change subject: mb/google/volteer: Enable EARLY_EC_SYNC
......................................................................
Patch Set 1:
This change is ready for review.
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EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40415 )
Change subject: mb/google/puff: add a region to cache SPD data
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40415/5/src/mainboard/google/hatch…
File src/mainboard/google/hatch/romstage_spd_smbus.c:
https://review.coreboot.org/c/coreboot/+/40415/5/src/mainboard/google/hatch…
PS5, Line 47: if (need_update_cache)
> We don't need to update SPD cache when we cannot load SPD cache successfully. […]
yes, I figured out this after :0
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Change subject: mb/google/puff: add a region to cache SPD data
......................................................................
Patch Set 7:
(4 comments)
https://review.coreboot.org/c/coreboot/+/40415/4/src/mainboard/google/hatch…
File src/mainboard/google/hatch/romstage_spd_smbus.c:
https://review.coreboot.org/c/coreboot/+/40415/4/src/mainboard/google/hatch…
PS4, Line 40: get_spd_sn(blk.addr_map[i], SPD_DRAM_DDR4, sn);
> my 2 cents […]
Done
https://review.coreboot.org/c/coreboot/+/40415/4/src/mainboard/google/hatch…
PS4, Line 46: DDR4_SPD_SN_OFF
> can you make it to DDR4_SPD_SN_OFFSET?
I think keep the DDR4_SPD_SN_OFF is better because there is the same naming style in spd_bin.h
https://review.coreboot.org/c/coreboot/+/40415/4/src/mainboard/google/hatch…
PS4, Line 85: (uintptr_t)blk.spd_array[0];
> i guess you can add few more tabs to get closer to the `=` in previous line
Done
https://review.coreboot.org/c/coreboot/+/40415/4/src/mainboard/google/hatch…
PS4, Line 96: (uintptr_t)blk.spd_array[1];
> i guess you can add few more tabs to get closer to the `=` in previous line
Done
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