Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41037 )
Change subject: mb/google/dedede: Enable PMC, P2SB and PCH SPI devices ......................................................................
mb/google/dedede: Enable PMC, P2SB and PCH SPI devices
BUG=None TEST=Build and boot the mainboard.
Change-Id: I1aae4adf1c13fd4ff58aa38a877f34e142f320f1 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/41037/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index cfe221f..c891e6e 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -289,11 +289,11 @@ device pnp 0c09.0 on end end end # eSPI Interface - device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller device pci 1f.3 off end # Intel HDA/cAVS device pci 1f.4 off end # SMBus - device pci 1f.5 off end # PCH SPI + device pci 1f.5 on end # PCH SPI device pci 1f.7 off end # Intel Trace Hub end end
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41037 )
Change subject: mb/google/dedede: Enable PMC, P2SB and PCH SPI devices ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41037/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41037/1//COMMIT_MSG@7 PS1, Line 7: devices ... in the devicetree ?
Hello build bot (Jenkins), Furquan Shaikh, Justin TerAvest, Tim Wawrzynczak, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41037
to look at the new patch set (#2).
Change subject: mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetree ......................................................................
mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetree
BUG=None TEST=Build and boot the mainboard.
Change-Id: I1aae4adf1c13fd4ff58aa38a877f34e142f320f1 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/41037/2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41037 )
Change subject: mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetree ......................................................................
Patch Set 2: Code-Review+2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41037 )
Change subject: mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41037/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41037/1//COMMIT_MSG@7 PS1, Line 7: devices
... […]
Done
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41037 )
Change subject: mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetree ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41037 )
Change subject: mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetree ......................................................................
mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetree
BUG=None TEST=Build and boot the mainboard.
Change-Id: I1aae4adf1c13fd4ff58aa38a877f34e142f320f1 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41037 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Aamir Bohra aamir.bohra@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Aamir Bohra: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index cfe221f..c891e6e 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -289,11 +289,11 @@ device pnp 0c09.0 on end end end # eSPI Interface - device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller device pci 1f.3 off end # Intel HDA/cAVS device pci 1f.4 off end # SMBus - device pci 1f.5 off end # PCH SPI + device pci 1f.5 on end # PCH SPI device pci 1f.7 off end # Intel Trace Hub end end
-
Aamir Bohra (Code Review) -
Karthik Ramasubramanian (Code Review)
-
Patrick Georgi (Code Review)
-
Tim Wawrzynczak (Code Review)