[coreboot-gerrit] Change in coreboot[master]: mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetree

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41037 )

Change subject: mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetree
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mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetree

BUG=None
TEST=Build and boot the mainboard.

Change-Id: I1aae4adf1c13fd4ff58aa38a877f34e142f320f1
Signed-off-by: Karthikeyan Ramasubramanian 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41037
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Aamir Bohra 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aamir Bohra: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index cfe221f..c891e6e 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -289,11 +289,11 @@
    			device pnp 0c09.0 on end
    		end
    	end # eSPI Interface
-		device pci 1f.1 off end # P2SB
-		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.1 on  end # P2SB
+		device pci 1f.2 on  end # Power Management Controller
    	device pci 1f.3 off end # Intel HDA/cAVS
    	device pci 1f.4 off end # SMBus
-		device pci 1f.5 off end # PCH SPI
+		device pci 1f.5 on  end # PCH SPI
    	device pci 1f.7 off end # Intel Trace Hub
    end
 end