Change in coreboot[master]: mb/intel/jasperlake_rvp: Configure SoC specific gpios

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40572 )

Change subject: mb/intel/jasperlake_rvp: Configure SoC specific gpios
......................................................................

mb/intel/jasperlake_rvp: Configure SoC specific gpios

This patch configures all SoC related gpios as per mainboard schematics.
Till now, we were relying on FSP to do SoC specific gpio programming but
now we'll program all gpios from mainboard. This will remove ambiguity of
gpio programming done by FSP and coreboot will do full gpio programming

Programming gpios of following IPs
- I2C
- Emmc
- Display
- CPU specific gpio (SLP lines)
- Cnvi

BUG=None
BRANCH=None
TEST=compile coreboot and checked that all IPs functionality working.

Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb
Signed-off-by: Maulik V Vaghela 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
1 file changed, 146 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40572/1

diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
index 9b86839..d9eb35f 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
@@ -7,14 +7,37 @@

/* Pad configuration in ramstage*/
 static const struct pad_config gpio_table[] = {
-	/* ToDo: Fill other gpio configuration */

/* WWAN_WAKE_N */
    PAD_CFG_GPI_SCI(GPP_A10, NONE, DEEP, LEVEL, INVERT),

+	/* DDSP_HPD_B */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+
+	/* EDP_HPD */
+	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
+
    /* M.2_WWAN_DISABLE_N */
    PAD_CFG_GPO(GPP_A19, 1, PLTRST),

+	/* VCCIN_AUX_VID0 */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+
+	/* VCCIN_AUX_VID1 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+
+	/* WLAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+
+	/* PCIE_X4_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+
+	/* AP_SLP_S0_L */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+
+	/* PLT_RST_L */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+
    /* M.2_WLAN_PERST_N */
    PAD_CFG_GPO(GPP_B17, 1, PLTRST),

@@ -30,7 +53,7 @@
    /* GSPI1_MOSI */
    PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),

-	/*PCH_INT_ODL*/
+	/* DDP_HDMI_HPD_C */
    PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),

/* WWAN_PERST_N */
@@ -60,18 +83,114 @@
    /* I2S_MCLK */
    PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),

+	/* CNV_MFUART2_RXD */
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+
+	/* CNV_MFUART2_TXD */
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+
+	/* CNV_PA_BLANKING */
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+
    /* WWAN_FCP_OFF_N */
    PAD_CFG_GPO(GPP_E3, 1, PLTRST),

+	/* DDPA_CTRLCLK */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+
+	/* DDPA_CTRLDATA */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+
+	/* DDPB_CTRLCLK */
+	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
+
+	/* DDPB_CTRLDATA */
+	PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
+
+	/* DDPC_CTRLCLK */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+
+	/* DDPC_CTRLDATA */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+
+	/* CNV_BRI_DT_R */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+
+	/* CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+
+	/* CNV_RGI_DT_R */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
+
+	/* CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
+
+	/* CNV_RF_RST_L */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+
+	/* EMMC_CMD */
+	PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
+
+	/* EMMC_DATA0 */
+	PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
+
+	/* EMMC_DATA1 */
+	PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
+
+	/* EMMC_DATA2 */
+	PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1),
+
+	/* EMMC_DATA3 */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
+
+	/* EMMC_DATA4 */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+
+	/* EMMC_DATA5 */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+
+	/* EMMC_DATA6 */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+
+	/* EMMC_DATA7 */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+
+	/* EMMC_RCLK */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+
+	/* EMMC_CLK */
+	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+
+	/* EMMC_RESET_N */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+
+	/* SD_CD# */
+	PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1),
+
+	/* SD_WP */
+	PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1),
+
    /*FPS_INT*/
    PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, INVERT),

+	/* SD_PWR_EN_B */
+	PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1)
+
+	/* CNV_CLKREQ0 */
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
+
    /* WWAN EN GPIO */
    PAD_CFG_GPO(GPP_H7, 1, PLTRST),

+	/* CPU_C10_GATE_L */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+
    /* M.2_BT_I2S2_SCLK */
    PAD_CFG_GPI(GPP_H11, NONE, PLTRST),

+	/* CNV_RF_RESET */
+	PAD_CFG_NF(GPP_H12, NONE, DEEP, NF2),
+
    /*PCH_INT_ODL*/
    PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT),

@@ -103,10 +222,10 @@
    PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),

/* I2S1_SFRM */
-	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1),

/* I2S1_TXD */
-	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1),

/* WWAN RST_N */
    PAD_CFG_GPO(GPP_S0, 1, DEEP),
@@ -123,6 +242,29 @@
    /* DMIC_DATA_0 */
    PAD_CFG_NF(GPP_S7, UP_20K, DEEP, NF2),

+	/* AP_BATLOW_L */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+
+	/* GPP_GPD1/ACPRESENT */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+
+	/* EC_AP_WAKE_ODL */
+	PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+
+	/* EC_AP_PWR_BTN_ODL */
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+
+	/* AP_SLP_S3_L */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+
+	/* AP_SLP_S4_L */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+
+	/* WLAN_SUSCLK */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+
+	/* virtual GPIO for SD card detect */
+	PAD_CFG_GPI_GPIO_DRIVER(VGPIO_39, NONE, DEEP),
 };

/* Early pad configuration in bootblock */

[Maulik V Vaghela (Code Review)]

Hello build bot (Jenkins), Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Ronak Kanabar, Aamir Bohra,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40572

to look at the new patch set (#2).

Change subject: mb/intel/jasperlake_rvp: Configure SoC specific gpios
......................................................................

mb/intel/jasperlake_rvp: Configure SoC specific gpios

This patch configures all SoC related gpios as per mainboard schematics.
Till now, we were relying on FSP to do SoC specific gpio programming but
now we'll program all gpios from mainboard. This will remove ambiguity of
gpio programming done by FSP and coreboot will do full gpio programming

Programming gpios of following IPs
- I2C
- Emmc
- Display
- CPU specific gpio (SLP lines)
- Cnvi

BUG=None
BRANCH=None
TEST=compile coreboot and checked that all IPs functionality working.

Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb
Signed-off-by: Maulik V Vaghela 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
1 file changed, 146 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40572/2

[Maulik V Vaghela (Code Review)]

Hello build bot (Jenkins), Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Ronak Kanabar, Aamir Bohra,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40572

to look at the new patch set (#5).

Change subject: mb/intel/jasperlake_rvp: Configure SoC specific gpios
......................................................................

mb/intel/jasperlake_rvp: Configure SoC specific gpios

This patch configures all SoC related gpios as per mainboard schematics.
Till now, we were relying on FSP to do SoC specific gpio programming but
now we'll program all gpios from mainboard. This will remove ambiguity of
gpio programming done by FSP and coreboot will do full gpio programming

Programming gpios of following IPs
- I2C
- Emmc
- Display
- CPU specific gpio (SLP lines)
- Cnvi
- SD

BUG=None
BRANCH=None
TEST=compile coreboot and checked that all IPs functionality working.

Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb
Signed-off-by: Maulik V Vaghela 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
1 file changed, 146 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40572/5

[Rizwan Qureshi (Code Review)]

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40572 )

Change subject: mb/intel/jasperlake_rvp: Configure SoC specific gpios
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40572/5/src/mainboard/intel/jasperl... 
File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c:

https://review.coreboot.org/c/coreboot/+/40572/5/src/mainboard/intel/jasperl... 
PS5, Line 23: /* VCCIN_AUX_VID0 */
            : 	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
            : 
            : 	/* VCCIN_AUX_VID1 */
            : 	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
            : 
            : 	/* WLAN_CLKREQ_ODL */
            : 	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
            : 
            : 	/* PCIE_X4_CLKREQ_ODL */
            : 	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
            : 
            : 	/* AP_SLP_S0_L */
            : 	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
            : 
            : 	/* PLT_RST_L */
            : 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
I think these configuration are better to be handled on SoC code. And mainboard will only specify the IP that it wants to use. Just like in FSP.

With this kind of configuration we will end up copying these in multiple boards.

I suggest
1. define configs (in chip.h) for each IP supported by the SoC or use the PCI device on/off definition
2. Define the GPIO Pad configuration for each IP in SoC code
3. Based on devictree configure the GPIO pads

[Varshit B Pandya (Code Review)]

Varshit B Pandya has uploaded a new patch set (#6) to the change originally created by Maulik V Vaghela. ( https://review.coreboot.org/c/coreboot/+/40572 )

Change subject: mb/intel/jasperlake_rvp: Configure SoC specific gpios
......................................................................

mb/intel/jasperlake_rvp: Configure SoC specific gpios

This patch configures all SoC related gpios as per mainboard schematics.
Till now, we were relying on FSP to do SoC specific gpio programming but
now we'll program all gpios from mainboard. This will remove ambiguity of
gpio programming done by FSP and coreboot will do full gpio programming

Programming gpios of following IPs
- I2C
- Emmc
- Display
- CPU specific gpio (SLP lines)
- Cnvi
- SD

BUG=None
BRANCH=None
TEST=compile coreboot and checked that all IPs functionality working.

Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb
Signed-off-by: Maulik V Vaghela 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
1 file changed, 146 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40572/6

[Maulik V Vaghela (Code Review)]

Hello Varshit B Pandya, build bot (Jenkins), Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Ronak Kanabar, Aamir Bohra,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40572

to look at the new patch set (#8).

Change subject: mb/intel/jasperlake_rvp: Configure SoC specific gpios
......................................................................

mb/intel/jasperlake_rvp: Configure SoC specific gpios

This patch configures all SoC related gpios as per mainboard schematics.
Till now, we were relying on FSP to do SoC specific gpio programming but
now we'll program all gpios from mainboard. This will remove ambiguity of
gpio programming done by FSP and coreboot will do full gpio programming

Programming gpios of following IPs
- I2C
- Emmc
- Display
- CPU specific gpio (SLP lines)
- Cnvi
- SD

BUG=None
BRANCH=None
TEST=compile coreboot and checked that all IPs functionality working.

Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb
Signed-off-by: Maulik V Vaghela 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
1 file changed, 140 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40572/8

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40572 )

Change subject: mb/intel/jasperlake_rvp: Configure SoC specific gpios
......................................................................

Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40572/5/src/mainboard/intel/jasperl... 
File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c:

https://review.coreboot.org/c/coreboot/+/40572/5/src/mainboard/intel/jasperl... 
PS5, Line 23: /* VCCIN_AUX_VID0 */
            : 	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
            : 
            : 	/* VCCIN_AUX_VID1 */
            : 	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
            : 
            : 	/* WLAN_CLKREQ_ODL */
            : 	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
            : 
            : 	/* PCIE_X4_CLKREQ_ODL */
            : 	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
            : 
            : 	/* AP_SLP_S0_L */
            : 	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
            : 
            : 	/* PLT_RST_L */
            : 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
> I think these configuration are better to be handled on SoC code. […]

Ack
Hi Rizwan,

Thank you for suggestion. Can we check in this patch and work on moving SoC specific gpios into soc code later?
I'll put to do in file and commit msg.

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40572 )

Change subject: mb/intel/jasperlake_rvp: Configure SoC specific gpios
......................................................................

Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40572/8//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40572/8//COMMIT_MSG@7 
PS8, Line 7: SoC specific
lets not use this works as SoC Specific. everything is SOC specific 😊

Change in coreboot[master]: mb/intel/jasperlake_rvp: Configure IP specific GPIOs

[Maulik V Vaghela (Code Review)]

Hello Varshit B Pandya, build bot (Jenkins), Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Ronak Kanabar, Aamir Bohra,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40572

to look at the new patch set (#9).

Change subject: mb/intel/jasperlake_rvp: Configure IP specific GPIOs
......................................................................

mb/intel/jasperlake_rvp: Configure IP specific GPIOs

This patch configures all IP related GPIOs as per mainboard schematics.
Till now, we were relying on FSP to do IP specific GPIO programming but
now we'll program all GPIOs from mainboard.
This will remove ambiguity of GPIO programming done by FSP and coreboot
will do full GPIO programming

Programming GPIOs of following IPs
- I2C
- Emmc
- Display
- CPU specific gpio (SLP lines)
- Cnvi
- SD

BUG=None
BRANCH=None
TEST=compile coreboot and checked that all IP functionality working.

Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb
Signed-off-by: Maulik V Vaghela 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
1 file changed, 140 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40572/9

Change in coreboot[master]: mb/intel/jasperlake_rvp: Configure IP specific GPIOs

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40572 )

Change subject: mb/intel/jasperlake_rvp: Configure IP specific GPIOs
......................................................................

Patch Set 9:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40572/8//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40572/8//COMMIT_MSG@7 
PS8, Line 7: SoC specific
> lets not use this works as SoC Specific. […]

Ack

Change in coreboot[master]: mb/intel/jasperlake_rvp: Configure IP specific GPIOs

[Maulik V Vaghela (Code Review)]

Hello Varshit B Pandya, build bot (Jenkins), Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Ronak Kanabar, Aamir Bohra,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40572

to look at the new patch set (#10).

Change subject: mb/intel/jasperlake_rvp: Configure IP specific GPIOs
......................................................................

mb/intel/jasperlake_rvp: Configure IP specific GPIOs

This patch configures all IP related GPIOs as per mainboard schematics.
Till now, we were relying on FSP to do IP specific GPIO programming but
now we'll program all GPIOs from mainboard.
This will remove ambiguity of GPIO programming done by FSP and coreboot
will do full GPIO programming

Programming GPIOs of following IPs
- I2C
- Emmc
- Display
- CPU specific gpio (SLP lines)
- Cnvi
- SD

BUG=None
BRANCH=None
TEST=compile coreboot and checked that all IP functionality working.

Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb
Signed-off-by: Maulik V Vaghela 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
1 file changed, 158 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40572/10

Change in coreboot[master]: mb/intel/jasperlake_rvp: Configure IP specific GPIOs

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40572 )

Change subject: mb/intel/jasperlake_rvp: Configure IP specific GPIOs
......................................................................

Patch Set 11: Code-Review+2

Change in coreboot[master]: mb/intel/jasperlake_rvp: Configure IP specific GPIOs

[Ronak Kanabar (Code Review)]

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40572 )

Change subject: mb/intel/jasperlake_rvp: Configure IP specific GPIOs
......................................................................

Patch Set 11: Code-Review+2

Change in coreboot[master]: mb/intel/jasperlake_rvp: Configure IP specific GPIOs

[Maulik V Vaghela (Code Review)]

Hello Varshit B Pandya, build bot (Jenkins), Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Ronak Kanabar, Aamir Bohra,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40572

to look at the new patch set (#12).

Change subject: mb/intel/jasperlake_rvp: Configure IP specific GPIOs
......................................................................

mb/intel/jasperlake_rvp: Configure IP specific GPIOs

This patch configures all IP related GPIOs as per mainboard schematics.
Till now, we were relying on FSP to do IP specific GPIO programming but
now we'll program all GPIOs from mainboard.
This will remove ambiguity of GPIO programming done by FSP and coreboot
will do full GPIO programming

Programming GPIOs of following IPs
- I2C
- Emmc
- Display
- CPU specific gpio (SLP lines)
- Cnvi
- SD

BUG=None
BRANCH=None
TEST=compile coreboot and checked that all IP functionality working.

Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb
Signed-off-by: Maulik V Vaghela 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
1 file changed, 173 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40572/12

Change in coreboot[master]: mb/intel/jasperlake_rvp: Configure IP specific GPIOs

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40572 )

Change subject: mb/intel/jasperlake_rvp: Configure IP specific GPIOs
......................................................................

Patch Set 12: Code-Review+2

Change in coreboot[master]: mb/intel/jasperlake_rvp: Configure IP specific GPIOs

[V Sowmya (Code Review)]

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40572 )

Change subject: mb/intel/jasperlake_rvp: Configure IP specific GPIOs
......................................................................

Patch Set 12: Code-Review+2

Change in coreboot[master]: mb/intel/jasperlake_rvp: Configure IP specific GPIOs

[Ronak Kanabar (Code Review)]

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40572 )

Change subject: mb/intel/jasperlake_rvp: Configure IP specific GPIOs
......................................................................

Patch Set 12: Code-Review+2

Change in coreboot[master]: mb/intel/jasperlake_rvp: Configure IP specific GPIOs

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40572 )

Change subject: mb/intel/jasperlake_rvp: Configure IP specific GPIOs
......................................................................

mb/intel/jasperlake_rvp: Configure IP specific GPIOs

This patch configures all IP related GPIOs as per mainboard schematics.
Till now, we were relying on FSP to do IP specific GPIO programming but
now we'll program all GPIOs from mainboard.
This will remove ambiguity of GPIO programming done by FSP and coreboot
will do full GPIO programming

Programming GPIOs of following IPs
- I2C
- Emmc
- Display
- CPU specific gpio (SLP lines)
- Cnvi
- SD

BUG=None
BRANCH=None
TEST=compile coreboot and checked that all IP functionality working.

Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb
Signed-off-by: Maulik V Vaghela 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40572
Tested-by: build bot (Jenkins) 
Reviewed-by: Aamir Bohra 
Reviewed-by: V Sowmya 
Reviewed-by: Ronak Kanabar 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
1 file changed, 173 insertions(+), 19 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aamir Bohra: Looks good to me, approved
  V Sowmya: Looks good to me, approved
  Ronak Kanabar: Looks good to me, approved

diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
index 9b86839..39c1470 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
@@ -7,18 +7,35 @@

/* Pad configuration in ramstage*/
 static const struct pad_config gpio_table[] = {
-	/* ToDo: Fill other gpio configuration */

/* WWAN_WAKE_N */
    PAD_CFG_GPI_SCI(GPP_A10, NONE, DEEP, LEVEL, INVERT),

+	/* DDI1_HPD */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+
+	/* DDI0_HPD */
+	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
+
    /* M.2_WWAN_DISABLE_N */
    PAD_CFG_GPO(GPP_A19, 1, PLTRST),

+	/* PMC_CORE_VID0 */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+
+	/* PMC_CORE_VID1 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+
+	/* PMC_SLP_S0_N */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+
+	/* PMC_PLT_RST_N */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+
    /* M.2_WLAN_PERST_N */
    PAD_CFG_GPO(GPP_B17, 1, PLTRST),

-	/* GSPI1_CS# */
+	/* GSPI1_CS0_N */
    PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),

/* GSPI1_CLK */
@@ -30,7 +47,7 @@
    /* GSPI1_MOSI */
    PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),

-	/*PCH_INT_ODL*/
+	/* DDI2_HPD */
    PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),

/* WWAN_PERST_N */
@@ -39,7 +56,7 @@
    /* M2_WWAN_SSD_SKT2_CFG2 */
    PAD_CFG_GPI(GPP_C3, NONE, PLTRST),

-	/*SLP_LAN_N*/
+	/* SLP_LAN_N */
    PAD_CFG_GPO(GPP_C7, 0, PLTRST),

/* I2C0_SDA */
@@ -54,31 +71,145 @@
    /* BT_RF_KILL_N */
    PAD_CFG_GPO(GPP_D1, 1, PLTRST),

-	/*LAN_RST_N*/
+	/* LAN_RST_N */
    PAD_CFG_GPO(GPP_D6, 1, PLTRST),

-	/* I2S_MCLK */
+	/* AVS_I2S_MCLK */
    PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),

+	/* CNV_MFUART2_RXD */
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+
+	/* CNV_MFUART2_TXD */
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+
+	/* CNV_PA_BLANKING */
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+
    /* WWAN_FCP_OFF_N */
    PAD_CFG_GPO(GPP_E3, 1, PLTRST),

-	/*FPS_INT*/
+	/* DDI0_DDC_SCL */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+
+	/* DDI0_DDC_SDA */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+
+	/* DDI1_DDC_SCL */
+	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
+
+	/* DDI1_DDC_SDA */
+	PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
+
+	/* DDI2_DDC_SCL */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+
+	/* DDI2_DDC_SDA */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+
+	/* CNV_BRI_DT */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+
+	/* CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+
+	/* CNV_RGI_DT */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
+
+	/* CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
+
+	/* CNV_RF_RESET_B */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+
+	/* EMMC_CMD */
+	PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
+
+	/* EMMC_DATA0 */
+	PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
+
+	/* EMMC_DATA1 */
+	PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
+
+	/* EMMC_DATA2 */
+	PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1),
+
+	/* EMMC_DATA3 */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
+
+	/* EMMC_DATA4 */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+
+	/* EMMC_DATA5 */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+
+	/* EMMC_DATA6 */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+
+	/* EMMC_DATA7 */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+
+	/* EMMC_RCLK */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+
+	/* EMMC_CLK */
+	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+
+	/* EMMC_RESET_N */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+
+	/* SD_SDIO_CMD */
+	PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
+
+	/* SD_SDIO_D0 */
+	PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
+
+	/* SD_SDIO_D1 */
+	PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
+
+	/* SD_SDIO_D2 */
+	PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
+
+	/* SD_SDIO_D3 */
+	PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
+
+	/* SD_SDIO_CD_N */
+	PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1),
+
+	/* SD_SDIO_CLK */
+	PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
+
+	/* SD_SDIO_WP */
+	PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1),
+
+	/* FPS_INT */
    PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, INVERT),

+	/* SD_SDIO_PWR_EN_N */
+	PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
+
+	/* MODEM_CLKREQ0 */
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
+
    /* WWAN EN GPIO */
    PAD_CFG_GPO(GPP_H7, 1, PLTRST),

+	/* CPU_C10_GATE_N */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+
    /* M.2_BT_I2S2_SCLK */
    PAD_CFG_GPI(GPP_H11, NONE, PLTRST),

-	/*PCH_INT_ODL*/
+	/* CNV_RF_RESET_N */
+	PAD_CFG_NF(GPP_H12, NONE, DEEP, NF2),
+
+	/* PCH_INT_ODL */
    PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT),

/* M.2_BT_I2S2_RXD */
    PAD_CFG_GPI(GPP_H14, NONE, PLTRST),

-	/* I2S1_SCLK */
+	/* AVS_I2S1_SCLK */
    PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),

/* Audio Jack Detection */
@@ -87,26 +218,26 @@
    /* M2_CNVI_EN_N */
    PAD_CFG_GPO(GPP_H19, 0, PLTRST),

-	/* I2S0_SCLK */
+	/* AVS_I2S0_SCLK */
    PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),

-	/* I2S0_SFRM */
+	/* AVS_I2S0_SFRM */
    PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),

-	/* I2S0_TXD */
+	/* AVS_I2S0_TXD */
    PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),

-	/* I2S0_RXD */
+	/* AVS_I2S0_RXD */
    PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),

-	/* I2S1_RXD */
+	/* AVS_I2S1_RXD */
    PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),

-	/* I2S1_SFRM */
-	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
+	/* AVS_I2S1_SFRM */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1),

-	/* I2S1_TXD */
-	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
+	/* AVS_I2S1_TXD */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1),

/* WWAN RST_N */
    PAD_CFG_GPO(GPP_S0, 1, DEEP),
@@ -123,6 +254,29 @@
    /* DMIC_DATA_0 */
    PAD_CFG_NF(GPP_S7, UP_20K, DEEP, NF2),

+	/* PMC_BATLOW_N */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+
+	/* PMC_ACPRESENT */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+
+	/* LAN_WAKE_N */
+	PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+
+	/* PMC_PWR_BTN_N */
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+
+	/* PMC_SLP_S3_N */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+
+	/* PMC_SLP_S4_N */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+
+	/* PMC_SUSCLK */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+
+	/* virtual GPIO for SD card detect */
+	PAD_CFG_GPI_GPIO_DRIVER(VGPIO_39, NONE, DEEP),
 };

/* Early pad configuration in bootblock */
@@ -140,7 +294,7 @@
    /* GSPI1_MOSI */
    PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),

-	/*PCH_INT_ODL*/
+	/* PCH_INT_ODL */
    PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT),
 };

Change in coreboot[master]: mb/intel/jasperlake_rvp: Configure IP specific GPIOs

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40572 )

Change subject: mb/intel/jasperlake_rvp: Configure IP specific GPIOs
......................................................................

Patch Set 13:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3213
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3212
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3211
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3210

Please note: This test is under development and might not be accurate at all!