Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40572 )
Change subject: mb/intel/jasperlake_rvp: Configure SoC specific gpios ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40572/5/src/mainboard/intel/jasperl... File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c:
https://review.coreboot.org/c/coreboot/+/40572/5/src/mainboard/intel/jasperl... PS5, Line 23: /* VCCIN_AUX_VID0 */ : PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), : : /* VCCIN_AUX_VID1 */ : PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), : : /* WLAN_CLKREQ_ODL */ : PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), : : /* PCIE_X4_CLKREQ_ODL */ : PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), : : /* AP_SLP_S0_L */ : PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), : : /* PLT_RST_L */ : PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), I think these configuration are better to be handled on SoC code. And mainboard will only specify the IP that it wants to use. Just like in FSP.
With this kind of configuration we will end up copying these in multiple boards.
I suggest 1. define configs (in chip.h) for each IP supported by the SoC or use the PCI device on/off definition 2. Define the GPIO Pad configuration for each IP in SoC code 3. Based on devictree configure the GPIO pads