coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

1 participants
1797 discussions

Change in coreboot[master]: src/Kconfig: enable USE_BLOBS by default
by Felix Held (Code Review) 14 Apr '20

14 Apr '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37972 ) Change subject: src/Kconfig: enable USE_BLOBS by default ...................................................................... src/Kconfig: enable USE_BLOBS by default To provide sane defaults for most of the user base, this patch switches on the USE_BLOBS option by default. Since it only changes the default, this behaviour can stil be easily disabled. Change-Id: Ia0632b9ae7a1f212a8640b3faec2695d17d238c5 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/37972/1 diff --git a/src/Kconfig b/src/Kconfig index 762cf89..c89e49f 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -228,6 +228,7 @@ config USE_BLOBS bool "Allow use of binary-only repository" + default y help This draws in the blobs repository, which contains binary files that might be required for some chipsets or boards. -- To view, visit https://review.coreboot.org/c/coreboot/+/37972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0632b9ae7a1f212a8640b3faec2695d17d238c5 Gerrit-Change-Number: 37972 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

8 22

Change in coreboot[master]: mainboard: add Supermicro X9SCL/X9SCM
by Jonathan Kollasch (Code Review) 14 Apr '20

14 Apr '20

Jonathan Kollasch has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38346 ) Change subject: mainboard: add Supermicro X9SCL/X9SCM ...................................................................... mainboard: add Supermicro X9SCL/X9SCM Still has ME issues near the end of raminit. ME firmware fails to run completely, and somehow inhibits further progress out of romstage. This condition impacts both the NRI and MRC code paths. This can be partially worked around: - short JPME1 for Recovery mode; - power on, wait for boot to hang; - power off (including ATX standby); - unshort JPME1; - power on; however, rebooting after that doesn't always work. But it's enough to boot and possibly explore getting the ME going more. - Slot 7 (x8 on 0:01.0) works as x8 of x16 - Slot 6 (x8 on 0:01.1) does not work (these lanes may be bundled for Slot 7) - Slot 5 (x4 on 0:06.0) is untested (only applicable to X9SCM, testing performed on X9SCL) - Slot 4 (x4 on 0:1c.0) works FIXME: - ME firmware startup issue - PEG PCIe lanes - SuperIO ASL in DSDT - SuperIO hardware monitor setup for PECI - fan control Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one) Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 --- A src/mainboard/supermicro/x9scl/Kconfig A src/mainboard/supermicro/x9scl/Kconfig.name A src/mainboard/supermicro/x9scl/Makefile.inc A src/mainboard/supermicro/x9scl/acpi/ec.asl A src/mainboard/supermicro/x9scl/acpi/platform.asl A src/mainboard/supermicro/x9scl/acpi/superio.asl A src/mainboard/supermicro/x9scl/acpi_tables.c A src/mainboard/supermicro/x9scl/board_info.txt A src/mainboard/supermicro/x9scl/devicetree.cb A src/mainboard/supermicro/x9scl/dsdt.asl A src/mainboard/supermicro/x9scl/early_init.c A src/mainboard/supermicro/x9scl/gpio.c A src/mainboard/supermicro/x9scl/hda_verb.c A src/mainboard/supermicro/x9scl/superio.h 14 files changed, 765 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38346/1 diff --git a/src/mainboard/supermicro/x9scl/Kconfig b/src/mainboard/supermicro/x9scl/Kconfig new file mode 100644 index 0000000..01bc702 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/Kconfig @@ -0,0 +1,53 @@ +if BOARD_SUPERMICRO_X9SCL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select SUPERIO_NUVOTON_WPCM450 + select MAINBOARD_USES_IFD_GBE_REGION + +config MAINBOARD_DIR + string + default supermicro/x9scl + +config MAINBOARD_PART_NUMBER + string + default "X9SCL/X9SCM" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 1 + +config VGA_BIOS_FILE + string + default "pci102b,0532.rom" + +config VGA_BIOS_ID + string + depends on VGA_BIOS + default "102b,0532" + +config PXE_ROM_ID + string + depends on PXE + default "8086:10d3" + +config CBFS_SIZE + hex + default 0x400000 + +config SUPERMICRO_BOARDID + string + default "0624" + +endif diff --git a/src/mainboard/supermicro/x9scl/Kconfig.name b/src/mainboard/supermicro/x9scl/Kconfig.name new file mode 100644 index 0000000..e0e91f1 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SUPERMICRO_X9SCL + bool "X9SCL/X9SCM" diff --git a/src/mainboard/supermicro/x9scl/Makefile.inc b/src/mainboard/supermicro/x9scl/Makefile.inc new file mode 100644 index 0000000..3465dfe --- /dev/null +++ b/src/mainboard/supermicro/x9scl/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c diff --git a/src/mainboard/supermicro/x9scl/acpi/ec.asl b/src/mainboard/supermicro/x9scl/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi/ec.asl diff --git a/src/mainboard/supermicro/x9scl/acpi/platform.asl b/src/mainboard/supermicro/x9scl/acpi/platform.asl new file mode 100644 index 0000000..0222986 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi/platform.asl @@ -0,0 +1,8 @@ +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/supermicro/x9scl/acpi/superio.asl b/src/mainboard/supermicro/x9scl/acpi/superio.asl new file mode 100644 index 0000000..f248ca1 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi/superio.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Finish this. */ +#if 0 +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#undef NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include <superio/nuvoton/nct6776/acpi/superio.asl> +#endif diff --git a/src/mainboard/supermicro/x9scl/acpi_tables.c b/src/mainboard/supermicro/x9scl/acpi_tables.c new file mode 100644 index 0000000..6727616 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi_tables.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/supermicro/x9scl/board_info.txt b/src/mainboard/supermicro/x9scl/board_info.txt new file mode 100644 index 0000000..a14680e --- /dev/null +++ b/src/mainboard/supermicro/x9scl/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Board URL: +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb new file mode 100644 index 0000000..0057a1e --- /dev/null +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -0,0 +1,150 @@ +chip northbridge/intel/sandybridge + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + subsystemid 0x15d9 0x0624 inherit + device pci 00.0 on # Host bridge + end + device pci 01.0 on # PEG + end + device pci 01.1 on # PEG + end + device pci 06.0 on # PEG + end + device pci 02.0 off # iGPU + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) + register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) + register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) + register "gen4_dec" = "0x001c03e1" # 3rd UART (0x03e0-03ff) + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 off # Management Engine Interface 1 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet (not for X9SCL+-F) + subsystemid 0x15d9 0x1502 + end + device pci 1a.0 on # USB2 EHCI #2 + end + device pci 1b.0 off # High Definition Audio + end + device pci 1c.0 on # PCIe Port #1 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 (primary 574 GigE) + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 on # PCIe Port #7 (secondary 574 GigE on X9SCL+-F) + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + end + device pci 1e.0 on # PCI bridge + end + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2, IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x060 + io 0x62 = 0x064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.307 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 on # GPIOBASE + io 0x60 = 0xa80 + end + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 on # GPIO2 + end + device pnp 2e.309 on # GPIO3 + end + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, front panel LED + io 0x60 = 0xa30 + io 0x62 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + chip drivers/ipmi + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/nuvoton/wpcm450 + device pnp 164e.2 on + io 0x60 = 0x03e8 + irq 0x70 = 10 + end + device pnp 164e.3 off end + device pnp 164e.6 off end + end + end + device pci 1f.2 on # SATA Controller 1 + end + device pci 1f.3 on # SMBus + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + end +end diff --git a/src/mainboard/supermicro/x9scl/dsdt.asl b/src/mainboard/supermicro/x9scl/dsdt.asl new file mode 100644 index 0000000..b00a7ff --- /dev/null +++ b/src/mainboard/supermicro/x9scl/dsdt.asl @@ -0,0 +1,29 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/supermicro/x9scl/early_init.c b/src/mainboard/supermicro/x9scl/early_init.c new file mode 100644 index 0000000..8887c0f --- /dev/null +++ b/src/mainboard/supermicro/x9scl/early_init.c @@ -0,0 +1,189 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#if CONFIG(USE_NATIVE_RAMINIT) +#include <northbridge/intel/sandybridge/raminit_native.h> +#else +#include <northbridge/intel/sandybridge/raminit.h> +#endif +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <superio/nuvoton/wpcm450/wpcm450.h> +#include "superio.h" + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* 0:1d.0? */ + { 1, 0, 0 }, /* ? USB0 1d.0 port 1 */ + { 1, 0, 0 }, /* ? USB1 1d.0 port 2 */ + { 1, 0, 1 }, /* ? USB2 1d.0 port 3 */ + { 1, 0, 1 }, /* ? USB3 1d.0 port 4 */ + { 1, 0, 2 }, /* ? USB4 1d.0 port 5 */ + { 1, 0, 2 }, /* ? USB5 1d.0 port 6 */ + /* 0:1a.0? */ + { 1, 0, 3 }, /* ? ??? 1a.0 port 1 */ + { 1, 0, 3 }, /* ? BMC 1a.0 port 2 */ + { 1, 0, 4 }, /* ? ??? 1a.0 port 3 */ + { 1, 0, 4 }, /* ? USB11 1a.0 port 4 */ + { 1, 0, 6 }, /* ? USB12 1a.0 port 5 */ + { 1, 0, 5 }, /* ? USB13 1a.0 port 6 */ + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +static const u16 superio_initvals[] = { + /* Global config registers */ + SUPERIO_INITVAL(0x1a, 0xc8), + SUPERIO_INITVAL(0x1b, 0x68), + SUPERIO_INITVAL(0x1c, 0x83), + SUPERIO_INITVAL(0x24, 0x24), + SUPERIO_INITVAL(0x2a, 0x00), + SUPERIO_INITVAL(0x2b, 0x42), + SUPERIO_INITVAL(0x2c, 0x80), + + SUPERIO_BANK(8), + SUPERIO_INITVAL(0x30, 0x0a), + SUPERIO_INITVAL(0x60, GPIO_PORT >> 8), + SUPERIO_INITVAL(0x61, GPIO_PORT & 0xff), + SUPERIO_INITVAL(0xe1, 0xf9), + + SUPERIO_BANK(9), + SUPERIO_INITVAL(0x30, 0x0c), + SUPERIO_INITVAL(0xe0, 0xcf), + SUPERIO_INITVAL(0xe4, 0xbd), + SUPERIO_INITVAL(0xe5, 0x42), + SUPERIO_INITVAL(0xe9, 0x10), + SUPERIO_INITVAL(0xea, 0x40), + + SUPERIO_BANK(0xa), + SUPERIO_INITVAL(0xe4, 0x60), + + SUPERIO_BANK(0xb), /* HWM & LED */ + SUPERIO_INITVAL(0x30, 0x01), + SUPERIO_INITVAL(0x60, HWM_PORT >> 8), + SUPERIO_INITVAL(0x61, HWM_PORT & 0xff), + SUPERIO_INITVAL(0xf7, 0x07), +}; + + +static void superio_init(void) +{ + SUPERIO_UNLOCK; + for (int i = 0; i < ARRAY_SIZE(superio_initvals); i++) + SUPERIO_WRITE_INITVAL(superio_initvals[i]); + SUPERIO_LOCK; +} + +void bootblock_mainboard_early_init(void) +{ + superio_init(); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + //wpcm450_enable_dev(WPCM450_SP2, 0x164e, 0x03e8); +} + +#if CONFIG(USE_NATIVE_RAMINIT) +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} +#endif + + +void mainboard_early_init(int s3resume) +{ + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, + pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | + DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG60); +} + +#if !CONFIG(USE_NATIVE_RAMINIT) +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct pei_data pd = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = (uintptr_t)DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 1, /* 0=Mobile, 1=Desktop/Server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 0, + .gbe_enable = 1, /* Boards sometimes uses PCH Intel GbE */ + .dimm_channel0_disabled = 0, /* Both DIMM enabled */ + .dimm_channel1_disabled = 0, /* Both DIMM enabled */ + .max_ddr3_freq = 1333, /* 1333=Sandy; 1600=Ivy */ + .usb_port_config = { + /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 3, 0x0040 }, + { 1, 3, 0x0040 }, + { 1, 4, 0x0040 }, + { 1, 4, 0x0040 }, + { 1, 6, 0x0040 }, + { 1, 5, 0x0040 }, + { 1, 5, 0x0040 }, + { 1, 6, 0x0040 } + }, + /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it, + * but might cause some system instability ! + */ + .pcie_init = 1, + }; + + /* copy the data to output PEI */ + *pei_data = pd; + +} +#endif diff --git a/src/mainboard/supermicro/x9scl/gpio.c b/src/mainboard/supermicro/x9scl/gpio.c new file mode 100644 index 0000000..5824720 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/gpio.c @@ -0,0 +1,197 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio7 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/supermicro/x9scl/hda_verb.c b/src/mainboard/supermicro/x9scl/hda_verb.c new file mode 100644 index 0000000..dff7f11 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/hda_verb.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = {}; +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/supermicro/x9scl/superio.h b/src/mainboard/supermicro/x9scl/superio.h new file mode 100644 index 0000000..2ce69e2 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/superio.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef X9SCL_SUPERIO_H +#define X9SCL_SUPERIO_H + +#include <arch/io.h> +#include <superio/hwm5_conf.h> + +#define NUVOTON_PORT 0x2e +#define HWM_PORT 0x0a30 +#define GPIO_PORT 0x0a80 + +#define SUPERIO_BANK(x) (0x0700 | x) +#define SUPERIO_INITVAL(reg, data) ((reg << 8) | (data)) +#define HWM_BANK(x) (0x4e00 | x) +#define HWM_INITVAL SUPERIO_INITVAL + +#define SUPERIO_UNLOCK do { \ + outb(0x87, NUVOTON_PORT); \ + outb(0x87, NUVOTON_PORT); \ +} while (0) + +#define SUPERIO_LOCK do { \ + outb(0xaa, NUVOTON_PORT); \ +} while (0) + +#define SUPERIO_WRITE(reg, data) do { \ + outb((reg), NUVOTON_PORT); \ + outb((data), NUVOTON_PORT + 1); \ +} while (0) + +#define SUPERIO_WRITE_INITVAL(val) SUPERIO_WRITE((val) >> 8, (val) & 0xff) + +#define HWM_WRITE_INITVAL(val) pnp_write_hwm5_index(HWM_PORT, (val) >> 8, (val) & 0xff) + +#endif /* X9SCL_SUPERIO_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 Gerrit-Change-Number: 38346 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-MessageType: newchange

3 20

Change in coreboot[master]: mb/lenovo: Add additional FMAPs on 8MiB devices
by Patrick Rudolph (Code Review) 14 Apr '20

14 Apr '20

Hello Marcello Sylvester Bauer, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39161 to review the following change. Change subject: mb/lenovo: Add additional FMAPs on 8MiB devices ...................................................................... mb/lenovo: Add additional FMAPs on 8MiB devices * Add FMAP for measured boot only, with a single RO partition. * Add FMAP for measured boot only, with a single RO partition but where the ME has been stripped. Tested on X220 using VBOOT+measured boot: * Used patched IFD and ME, boots into OS Change-Id: I04c1add13198444638c669deec1e05159b1a09c9 Signed-off-by: Marcello Sylvester Bauer <sylv(a)sylv.io> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd A src/mainboard/lenovo/t420/vboot-ro.fmd A src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd A src/mainboard/lenovo/t420s/vboot-ro.fmd A src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd A src/mainboard/lenovo/t520/vboot-ro.fmd A src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd A src/mainboard/lenovo/x220/vboot-ro.fmd 8 files changed, 176 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/39161/1 diff --git a/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd new file mode 100644 index 0000000..d1cbff7 --- /dev/null +++ b/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x7e0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t420/vboot-ro.fmd b/src/mainboard/lenovo/t420/vboot-ro.fmd new file mode 100644 index 0000000..51df8a5 --- /dev/null +++ b/src/mainboard/lenovo/t420/vboot-ro.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME 0x4ed000 + } + SI_BIOS 0x300000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd new file mode 100644 index 0000000..d1cbff7 --- /dev/null +++ b/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x7e0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t420s/vboot-ro.fmd b/src/mainboard/lenovo/t420s/vboot-ro.fmd new file mode 100644 index 0000000..51df8a5 --- /dev/null +++ b/src/mainboard/lenovo/t420s/vboot-ro.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME 0x4ed000 + } + SI_BIOS 0x300000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd new file mode 100644 index 0000000..d1cbff7 --- /dev/null +++ b/src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x7e0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t520/vboot-ro.fmd b/src/mainboard/lenovo/t520/vboot-ro.fmd new file mode 100644 index 0000000..51df8a5 --- /dev/null +++ b/src/mainboard/lenovo/t520/vboot-ro.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME 0x4ed000 + } + SI_BIOS 0x300000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd new file mode 100644 index 0000000..d1cbff7 --- /dev/null +++ b/src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x7e0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/x220/vboot-ro.fmd b/src/mainboard/lenovo/x220/vboot-ro.fmd new file mode 100644 index 0000000..51df8a5 --- /dev/null +++ b/src/mainboard/lenovo/x220/vboot-ro.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME 0x4ed000 + } + SI_BIOS 0x300000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04c1add13198444638c669deec1e05159b1a09c9 Gerrit-Change-Number: 39161 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Marcello Sylvester Bauer <sylv(a)sylv.io> Gerrit-MessageType: newchange

6 14

Change in coreboot[master]: 4.12 release notes: Add some explanation behind depreciations
by Arthur Heymans (Code Review) 14 Apr '20

14 Apr '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37064 ) Change subject: 4.12 release notes: Add some explanation behind depreciations ...................................................................... 4.12 release notes: Add some explanation behind depreciations Some features are made mandatory, meaning that some platforms have been dropped from master. This also explains that further development on these popular platforms can happen on the 4.11 branch. TODO is this really the right place or is it too technical for release notes? Change-Id: I95e01c301e7db6f81ef88a89d709ebab35c9ccfb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/releases/coreboot-4.12-relnotes.md 1 file changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/37064/1 diff --git a/Documentation/releases/coreboot-4.12-relnotes.md b/Documentation/releases/coreboot-4.12-relnotes.md index f9c5f7e..67bef34 100644 --- a/Documentation/releases/coreboot-4.12-relnotes.md +++ b/Documentation/releases/coreboot-4.12-relnotes.md @@ -10,6 +10,67 @@ * The chip and board additions and removals will be updated right before the release, so those do not need to be added. +Deprecations +------------ + +For the 4.12 release a few features on x86 became mandatory. These are +relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK. + +### Relocatable ramstage + +Relocatable stages are a feature only implemented only on x86, where +stages can be relocated at runtime. This is used to place ramstage in +a better location that does not collide with memory the OS tends to +use. The rationale behind making this mandatory is that you always +want cbmem to be cached so it's a good location to run ramstage from. +It avoids using lower memory altogether so the OS can make use +of it and no backing up needs to happen on S3 resume. + +### Postcar stage + +With Postcar stage tearing down Cache-as-Ram is done in a separate +stage. This means that romstage has a clean program boundary and +that all variables in romstage can be accessed via their initial +reference at all times. There is no need to link global and static +variables via the CAR\_GLOBAL macro and no need to access them with +car\_set/get\_var/ptr functions. + +### C\_ENVIRONMENT\_BOOTBLOCK + +Historically the bootblock on x86 platforms has been compiled with +romcc. This means that the generated code only uses CPU registers +and therefore no stack. This 20K+ LOC compiler is limited and hard +to maintain. A different solution is to set up Cache-as-Ram in the +bootblock and run GCC compiled code in the bootblock. The advantages +are increased flexibility: e.g. printing to console is possible and +VBOOT can run before romstage, making romstage updatable via RW FMAP +regions. + +### Platforms dropped from master + +The following platforms did not implement those feature are dropped +from master to allow the master branch to move on: +- AMDFAM10 +- all FSP1.0 platforms: BROADWELL_DE, FSP_BAYTRAIL, RANGELEY +- VIA VX900 +- TODO (AMD?) + +In particular on FSP1.0 it is impossible to implement POSTCAR stage. +The reason is that FSP1.0 relocates the CAR region to the HOB before +returning to coreboot. This means that after FSP returns to coreboot +accessing variables via their original address is not possible. One +way of obtaining that behavior would be to set up Cache-as-Ram again +(but with open source code) and copy the relocated data from the HOB +there. This solution is deemed too hacky. Maybe a lesson can be +learned from this: blobs should not interfere with the execution +environment, as this makes proper integration much harder. + +### 4.11_branch + +Given that some platforms supported by FSP1.0 are being produced and +popular, the 4.11 release was made into a branch in which further +development can happen. + Significant changes ------------------- -- To view, visit https://review.coreboot.org/c/coreboot/+/37064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95e01c301e7db6f81ef88a89d709ebab35c9ccfb Gerrit-Change-Number: 37064 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

8 22

Change in coreboot[master]: Signed-off-by: dalao <dalao@tutanota.com>
by DaLao (Code Review) 14 Apr '20

14 Apr '20

DaLao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36371 ) Change subject: Signed-off-by: dalao <dalao(a)tutanota.com> ...................................................................... Signed-off-by: dalao <dalao(a)tutanota.com> src/mainboard/lenovo: Use the original lenovo hardware id for touchpad Currently the coreboot's touchpad hardware id is different from the original lenovo ones, and this causes some problems. On Windows, the touchpad driver can't automatically be matched and installed through Windows Update. On Linux, there also maybe some strange issues (https://bugzilla.kernel.org/show_bug.cgi?id=91541). So it's better to use the original lenovo hardware id for each model than the PNP-id. By searching for dmesg logs, I found the following hardware ids for these thinkpad models: LEN0015 T510: https://bbs.archlinux.org/viewtopic.php?id=120287 T410: ? T420: ? T420s: https://bbs.archlinux.org/viewtopic.php?id=191510 T520: ? T430: https://github.com/farjump/fwtr/blob/master/lenovo/thinkpad-t430/2347ds2/le… T430s: ? T530: ? LEN0020 X220: https://bbs.archlinux.org/viewtopic.php?id=237669 X230: https://forums.bunsenlabs.org/viewtopic.php?id=2460 LEN0036 T540: https://bugzilla.kernel.org/show_bug.cgi?id=91541 Then I made several copies of the ps2_controller.asl changed the superio.asl to include their correct ones. Then reboot to Windows and the touchpad driver is automatically installed. Done. But I still have some querstions: 1, Is making copies of the ps2_controller.asl a good way? Are there any better methods for doing this? 2, Is there any website that collect dmesg logs so I can search the hardware ids? 3, The keyboard's hardware id maybe different like the touchpad as well. But they are working ok, so I haven't looked into it. Change-Id: Ifb635da99c5e05f987aaf4f172108d788dcc2932 --- A src/drivers/pc80/pc/ps2_controller_len0015.asl A src/drivers/pc80/pc/ps2_controller_len0020.asl A src/drivers/pc80/pc/ps2_controller_len0036.asl M src/mainboard/lenovo/t410/acpi/superio.asl M src/mainboard/lenovo/t420/acpi/superio.asl M src/mainboard/lenovo/t420s/acpi/superio.asl M src/mainboard/lenovo/t430/acpi/superio.asl M src/mainboard/lenovo/t430s/acpi/superio.asl M src/mainboard/lenovo/t520/acpi/superio.asl M src/mainboard/lenovo/t530/acpi/superio.asl M src/mainboard/lenovo/x220/acpi/superio.asl M src/mainboard/lenovo/x230/acpi/superio.asl 12 files changed, 145 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/36371/1 diff --git a/src/drivers/pc80/pc/ps2_controller_len0015.asl b/src/drivers/pc80/pc/ps2_controller_len0015.asl new file mode 100644 index 0000000..750b24f --- /dev/null +++ b/src/drivers/pc80/pc/ps2_controller_len0015.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + Device (PS2K) // Keyboard + { + Name(_HID, EISAID("PNP0303")) + Name(_CID, EISAID("PNP030B")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1 + }) + + Method (_STA, 0) + { + Return (0xf) + } + } + + Device (PS2M) // Mouse + { + Name(_HID, EISAID("LEN0015")) + Name(_CID, EISAID("PNP0F13")) + + Name(_CRS, ResourceTemplate() + { + IRQ (Edge, ActiveHigh, Exclusive) { 0x0c } // IRQ 12 + }) + + Method(_STA, 0) + { + Return (0xf) + } + } diff --git a/src/drivers/pc80/pc/ps2_controller_len0020.asl b/src/drivers/pc80/pc/ps2_controller_len0020.asl new file mode 100644 index 0000000..ba476a6 --- /dev/null +++ b/src/drivers/pc80/pc/ps2_controller_len0020.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + Device (PS2K) // Keyboard + { + Name(_HID, EISAID("PNP0303")) + Name(_CID, EISAID("PNP030B")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1 + }) + + Method (_STA, 0) + { + Return (0xf) + } + } + + Device (PS2M) // Mouse + { + Name(_HID, EISAID("LEN0020")) + Name(_CID, EISAID("PNP0F13")) + Name(_CRS, ResourceTemplate() + { + IRQ (Edge, ActiveHigh, Exclusive) { 0x0c } // IRQ 12 + }) + + Method(_STA, 0) + { + Return (0xf) + } + } diff --git a/src/drivers/pc80/pc/ps2_controller_len0036.asl b/src/drivers/pc80/pc/ps2_controller_len0036.asl new file mode 100644 index 0000000..4b10381 --- /dev/null +++ b/src/drivers/pc80/pc/ps2_controller_len0036.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + Device (PS2K) // Keyboard + { + Name(_HID, EISAID("PNP0303")) + Name(_CID, EISAID("PNP030B")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1 + }) + + Method (_STA, 0) + { + Return (0xf) + } + } + + Device (PS2M) // Mouse + { + Name(_HID, EISAID("LEN0036")) + Name(_CID, EISAID("PNP0F13")) + Name(_CRS, ResourceTemplate() + { + IRQ (Edge, ActiveHigh, Exclusive) { 0x0c } // IRQ 12 + }) + + Method(_STA, 0) + { + Return (0xf) + } + } diff --git a/src/mainboard/lenovo/t410/acpi/superio.asl b/src/mainboard/lenovo/t410/acpi/superio.asl index f2b35ba..24afccc 100644 --- a/src/mainboard/lenovo/t410/acpi/superio.asl +++ b/src/mainboard/lenovo/t410/acpi/superio.asl @@ -1 +1 @@ -#include <drivers/pc80/pc/ps2_controller.asl> +#include <drivers/pc80/pc/ps2_controller_len0015.asl> diff --git a/src/mainboard/lenovo/t420/acpi/superio.asl b/src/mainboard/lenovo/t420/acpi/superio.asl index f2b35ba..24afccc 100644 --- a/src/mainboard/lenovo/t420/acpi/superio.asl +++ b/src/mainboard/lenovo/t420/acpi/superio.asl @@ -1 +1 @@ -#include <drivers/pc80/pc/ps2_controller.asl> +#include <drivers/pc80/pc/ps2_controller_len0015.asl> diff --git a/src/mainboard/lenovo/t420s/acpi/superio.asl b/src/mainboard/lenovo/t420s/acpi/superio.asl index f2b35ba..24afccc 100644 --- a/src/mainboard/lenovo/t420s/acpi/superio.asl +++ b/src/mainboard/lenovo/t420s/acpi/superio.asl @@ -1 +1 @@ -#include <drivers/pc80/pc/ps2_controller.asl> +#include <drivers/pc80/pc/ps2_controller_len0015.asl> diff --git a/src/mainboard/lenovo/t430/acpi/superio.asl b/src/mainboard/lenovo/t430/acpi/superio.asl index 8964c36..4ba8af3 100644 --- a/src/mainboard/lenovo/t430/acpi/superio.asl +++ b/src/mainboard/lenovo/t430/acpi/superio.asl @@ -13,4 +13,4 @@ * GNU General Public License for more details. */ -#include <drivers/pc80/pc/ps2_controller.asl> +#include <drivers/pc80/pc/ps2_controller_len0015.asl> diff --git a/src/mainboard/lenovo/t430s/acpi/superio.asl b/src/mainboard/lenovo/t430s/acpi/superio.asl index f2b35ba..24afccc 100644 --- a/src/mainboard/lenovo/t430s/acpi/superio.asl +++ b/src/mainboard/lenovo/t430s/acpi/superio.asl @@ -1 +1 @@ -#include <drivers/pc80/pc/ps2_controller.asl> +#include <drivers/pc80/pc/ps2_controller_len0015.asl> diff --git a/src/mainboard/lenovo/t520/acpi/superio.asl b/src/mainboard/lenovo/t520/acpi/superio.asl index f2b35ba..24afccc 100644 --- a/src/mainboard/lenovo/t520/acpi/superio.asl +++ b/src/mainboard/lenovo/t520/acpi/superio.asl @@ -1 +1 @@ -#include <drivers/pc80/pc/ps2_controller.asl> +#include <drivers/pc80/pc/ps2_controller_len0015.asl> diff --git a/src/mainboard/lenovo/t530/acpi/superio.asl b/src/mainboard/lenovo/t530/acpi/superio.asl index f2b35ba..24afccc 100644 --- a/src/mainboard/lenovo/t530/acpi/superio.asl +++ b/src/mainboard/lenovo/t530/acpi/superio.asl @@ -1 +1 @@ -#include <drivers/pc80/pc/ps2_controller.asl> +#include <drivers/pc80/pc/ps2_controller_len0015.asl> diff --git a/src/mainboard/lenovo/x220/acpi/superio.asl b/src/mainboard/lenovo/x220/acpi/superio.asl index f2b35ba..069cdea 100644 --- a/src/mainboard/lenovo/x220/acpi/superio.asl +++ b/src/mainboard/lenovo/x220/acpi/superio.asl @@ -1 +1 @@ -#include <drivers/pc80/pc/ps2_controller.asl> +#include <drivers/pc80/pc/ps2_controller_len0020.asl> diff --git a/src/mainboard/lenovo/x230/acpi/superio.asl b/src/mainboard/lenovo/x230/acpi/superio.asl index f2b35ba..069cdea 100644 --- a/src/mainboard/lenovo/x230/acpi/superio.asl +++ b/src/mainboard/lenovo/x230/acpi/superio.asl @@ -1 +1 @@ -#include <drivers/pc80/pc/ps2_controller.asl> +#include <drivers/pc80/pc/ps2_controller_len0020.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/36371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb635da99c5e05f987aaf4f172108d788dcc2932 Gerrit-Change-Number: 36371 Gerrit-PatchSet: 1 Gerrit-Owner: DaLao <dalao(a)tutanota.com> Gerrit-MessageType: newchange

8 25

Change in coreboot[master]: soc/intel/cannonlake: Add tdc config for CML
by Marx Wang (Code Review) 14 Apr '20

14 Apr '20

Marx Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38741 ) Change subject: soc/intel/cannonlake: Add tdc config for CML ...................................................................... soc/intel/cannonlake: Add tdc config for CML Add tdc defaults for CML: 1.TdcEnable 2.TdcPowerLimit UG=b:148912093 BRANCH=None TEST=build coreboot and check FSP log. Signed-off-by: Marx Wang <marx.wang(a)intel.com> Change-Id: Ie4b17e5b4ce41c1adb436ae5646f0d8578a440e8 --- M src/soc/intel/cannonlake/include/soc/vr_config.h M src/soc/intel/cannonlake/vr_config.c 2 files changed, 114 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38741/1 diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h index 1390b17..ce6f0ab 100644 --- a/src/soc/intel/cannonlake/include/soc/vr_config.h +++ b/src/soc/intel/cannonlake/include/soc/vr_config.h @@ -53,10 +53,16 @@ /* AC and DC Loadline in 1/100 mOhms. Range is 0-6249 */ uint16_t ac_loadline; uint16_t dc_loadline; + + /* TDC Power Limit in 1/8 A units */ + uint16_t tdc_powerlimit; + + }; #define VR_CFG_AMP(i) (uint16_t)((i) * 4) #define VR_CFG_MOHMS(i) (uint16_t)((i) * 100) +#define VR_CFG_TDC_AMP(i) ((i) * 8) /* VrConfig Settings for 4 domains * 0 = System Agent, 1 = IA Core, @@ -85,6 +91,14 @@ [VR_GT_SLICED] = VR_CFG_MOHMS(gt_sl), \ } +#define VR_CFG_ALL_DOMAINS_TDC(sa, ia, gt_unsl, gt_sl) \ + { \ + [VR_SYSTEM_AGENT] = VR_CFG_TDC_AMP(sa), \ + [VR_IA_CORE] = VR_CFG_TDC_AMP(ia), \ + [VR_GT_UNSLICED] = VR_CFG_TDC_AMP(gt_unsl), \ + [VR_GT_SLICED] = VR_CFG_TDC_AMP(gt_sl), \ + } + void fill_vr_domain_config(void *params, int domain, const struct vr_config *cfg); diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 5fadcf4..58880b1 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -419,6 +419,98 @@ return 1520; } +static uint16_t get_sku_tdc_powerlimit(int domain) +{ + const uint16_t tdp = cpu_get_power_max(); + config_t *cfg = config_of_soc(); + + static uint16_t mch_id = 0; + if (!mch_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + } + + switch (mch_id) { + case PCI_DEVICE_ID_INTEL_CML_ULT: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_ULT_6_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(4, 58, 22, 22); + + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(48); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_ULT_2_2: { + const uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(4, 24, 22, 22); + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_4_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25); + + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(60); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 92, 25, 25); + + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(80); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_8_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 125, 25, 25); + + if (tdp >= 65) /* 65W */ + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(117); + else + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(146); + else /* 45W */ + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(86); + else + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(125); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 74, 28, 28); + + if (tdp >= 125) /* 125W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(132); + else if (tdp >= 65) /* 80W or 65W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(104); + else /* 35W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(74); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 100, 28, 28); + + if (tdp > 35) /* 125W or 80W or 65W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(175); + + return tdc[domain]; + } + default: + printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); + } + + return 0; +} + void fill_vr_domain_config(void *params, int domain, const struct vr_config *chip_cfg) { @@ -442,7 +534,6 @@ vr_params->Psi4Enable[domain] = cfg->psi4enable; vr_params->ImonSlope[domain] = cfg->imon_slope; vr_params->ImonOffset[domain] = cfg->imon_offset; - /* If board provided non-zero value, use it. */ if (cfg->voltage_limit) vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; @@ -463,4 +554,12 @@ vr_params->DcLoadline[domain] = cfg->dc_loadline; else vr_params->DcLoadline[domain] = get_sku_ac_dc_loadline(domain); + + if (cfg->tdc_powerlimit) + vr_params->TdcPowerLimit[domain] = cfg->tdc_powerlimit; + else + vr_params->TdcPowerLimit[domain] = get_sku_tdc_powerlimit(domain); + + vr_params->TdcEnable[domain] = 1; + } -- To view, visit https://review.coreboot.org/c/coreboot/+/38741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4b17e5b4ce41c1adb436ae5646f0d8578a440e8 Gerrit-Change-Number: 38741 Gerrit-PatchSet: 1 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com> Gerrit-MessageType: newchange

11 75

Change in coreboot[master]: mb/intel/tglrvp: Update FMAP and EC switches
by Ravishankar Sarawadi (Code Review) 14 Apr '20

14 Apr '20

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37927 ) Change subject: mb/intel/tglrvp: Update FMAP and EC switches ...................................................................... mb/intel/tglrvp: Update FMAP and EC switches - Update FMAP to reflect 32MB flash regions - Use LPC/ChromeEC controlled switches BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I3589cc6eb6e6f6ecc6d40e254b67ed3d15aff7aa --- M src/mainboard/intel/tglrvp/chromeos.c M src/mainboard/intel/tglrvp/chromeos.fmd 2 files changed, 9 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/37927/1 diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index 372f6ce..35ee3dd 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -30,17 +30,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_lid_switch(void) -{ - /* Lid always open */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - return 0; -} - int get_write_protect_state(void) { /* No write protect */ diff --git a/src/mainboard/intel/tglrvp/chromeos.fmd b/src/mainboard/intel/tglrvp/chromeos.fmd index f4db8b4..bfbd304 100644 --- a/src/mainboard/intel/tglrvp/chromeos.fmd +++ b/src/mainboard/intel/tglrvp/chromeos.fmd @@ -1,10 +1,10 @@ -FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x3F0000 { +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x1081000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x36F000 + SI_ME@0x81000 0x1000000 } - SI_BIOS@0x400000 0xC00000 { + SI_BIOS@0x1400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x2bffc0 @@ -20,18 +20,18 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 } - SMMSTORE(PRESERVE)@0x5d0000 0x40000 + SMMSTORE@0x5d0000 0x40000 RW_LEGACY(CBFS)@0x610000 0x1c0000 WP_RO@0x7d0000 0x430000 { - RO_VPD(PRESERVE)@0x0 0x4000 + RO_VPD@0x0 0x4000 RO_SECTION@0x4000 0x42c000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 -- To view, visit https://review.coreboot.org/c/coreboot/+/37927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3589cc6eb6e6f6ecc6d40e254b67ed3d15aff7aa Gerrit-Change-Number: 37927 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/intel/tglrvp: Update Kconfig
by Ravishankar Sarawadi (Code Review) 14 Apr '20

14 Apr '20

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37926 ) Change subject: mb/intel/tglrvp: Update Kconfig ...................................................................... mb/intel/tglrvp: Update Kconfig Update Kconfig to add Tigerlake RVP board specific configs. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I92a28592d9fbed9b858e14326de4f5921aa35016 --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/Kconfig.name 2 files changed, 80 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/37926/1 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index a45b29e..a4df59b 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -1,55 +1,89 @@ -if BOARD_INTEL_TGLRVP_UP3 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_16384 - select EC_ACPI - select GENERIC_SPD_BIN +config BOARD_INTEL_BASEBOARD_TGLRVP + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_I2C_MAX98373 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select GENERATE_SMBIOS_TABLES select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select MAINBOARD_INTEL_COMMON - select MAINBOARD_HAS_CHROMEOS - select GENERIC_SPD_BIN - select DRIVERS_I2C_HID - select DRIVERS_I2C_GENERIC - select DRIVERS_USB_ACPI - select SOC_INTEL_TIGERLAKE - select MAINBOARD_USES_IFD_EC_REGION select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_TIGERLAKE -config MAINBOARD_DIR - string - default "intel/tigerlake_rvp" - -config VARIANT_DIR - string - default "tglrvp" if BOARD_INTEL_TGLRVP_UP3 - -config MAINBOARD_PART_NUMBER - string - default "blackwall" - -config MAINBOARD_FAMILY - string - default "Intel_tigerlake_rvp" - -config MAX_CPUS - int - default 8 - -config DEVICETREE - string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +if BOARD_INTEL_BASEBOARD_TGLRVP config DIMM_SPD_SIZE int default 512 -config VBOOT - select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA +config GBB_HWID + string + depends on CHROMEOS + default "TGLRVP" if BOARD_INTEL_TGLRVP_UP3 + +config MAINBOARD_DIR + string + default "intel/tglrvp" + +config MAINBOARD_FAMILY + string + default "Intel_tglrvp" if BOARD_INTEL_TGLRVP_UP3 + +config MAINBOARD_PART_NUMBER + string + default "Tglrvp" if BOARD_INTEL_TGLRVP_UP3 + +config MAX_CPUS + int + default 8 + +config OEM_BIN_FILE + string "OEM ID table" + default "" config UART_FOR_CONSOLE int default 2 + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config VARIANT_DIR + string + default "tglrvp_up3" if BOARD_INTEL_TGLRVP_UP3 + +choice TGL_EC + prompt "ON BOARD EC" + default TGL_CHROME_EC + help + This option allows you to select the on board EC to use. + Select whether the board has Intel EC or Chrome EC + +config TGL_CHROME_EC + bool "Chrome EC" + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_ACPI + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + +config TGL_INTEL_EC + bool "Intel EC" + select EC_ACPI + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC +endchoice + +config VBOOT + select VBOOT_LID_SWITCH + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_MOCK_SECDATA + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN endif diff --git a/src/mainboard/intel/tglrvp/Kconfig.name b/src/mainboard/intel/tglrvp/Kconfig.name index 673a54c..42dc4d6 100644 --- a/src/mainboard/intel/tglrvp/Kconfig.name +++ b/src/mainboard/intel/tglrvp/Kconfig.name @@ -1,5 +1,6 @@ -config BOARD_INTEL_TGLRVP - bool "Tigerlake DDR4/LPDDR4 RVP" +comment "Tglrvp" -config BOARD_INTEL_TGLRVP_EXT_EC - bool "Tigerlake DDR4/LPDDR4 RVP with Chrome EC" +config BOARD_INTEL_TGLRVP_UP3 + bool "-> Tglrvp" + select BOARD_INTEL_BASEBOARD_TGLRVP + -- To view, visit https://review.coreboot.org/c/coreboot/+/37926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92a28592d9fbed9b858e14326de4f5921aa35016 Gerrit-Change-Number: 37926 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: [WIP]mb/intel/tglrvp: Add correct memory SPD settings
by Ravishankar Sarawadi (Code Review) 14 Apr '20

14 Apr '20

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37928 ) Change subject: [WIP]mb/intel/tglrvp: Add correct memory SPD settings ...................................................................... [WIP]mb/intel/tglrvp: Add correct memory SPD settings Add Tigerlake RVP supported SPDs and update FSP-M UPDs for MRC boot config. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: Id3fd54b051effb9eb2303e0db2217dd28f857368 --- M src/mainboard/intel/tglrvp/romstage_fsp_params.c A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex M src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex M src/mainboard/intel/tglrvp/spd/spd.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 8 files changed, 312 insertions(+), 289 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37928/1 diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index 0ab1f48..303f70a 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -12,11 +12,91 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include <assert.h> +#include <console/console.h> #include <fsp/api.h> #include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +/* DQ byte map */ +static const u8 dq_map[8][2][8] = { + //Controller 0 + { { 0, 1, 6, 7, 3, 2, 5, 4 }, // Byte 0 + { 15, 8, 9, 14, 12, 11, 10, 13 } }, // Byte 1 + { { 11, 12, 8, 15, 9, 14, 10, 13 }, // Byte 2 + { 3, 4, 7, 0, 6, 1, 5, 2 } }, // Byte 3 + { { 4, 5, 3, 2, 7, 1, 0, 6 }, // Byte 4 + { 11, 10, 12, 13, 8, 9, 14, 15 } }, // Byte 5 + { { 12, 11, 8, 13, 14, 15, 9, 10 }, // Byte 6 + { 4, 7, 3, 2, 1, 6, 0, 5 } }, // Byte 7 + //Controller 1 + { { 11, 10, 9, 8, 12, 13, 15, 14 }, // Byte 0 ChB! + { 4, 5, 6, 7, 3, 2, 0, 1 } }, // Byte 1 ChB! + { { 0, 7, 1, 6, 3, 5, 2, 4 }, // Byte 2 + { 9, 8, 10, 11, 14, 15, 13, 12 } }, // Byte 3 + { { 4, 5, 6, 1, 3, 2, 7, 0 }, // Byte 4 + { 10, 13, 12, 11, 14, 9, 15, 8 } }, // Byte 5 + { { 10, 12, 9, 15, 8, 11, 13, 14 }, // Byte 6 + { 3, 4, 1, 2, 6, 0, 5, 7 } } // Byte 7 + }; + +/* DQS CPU<>DRAM map */ +static const u8 dqs_map[8][2] = { + // Ch 0 1 2 3 + { 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 }, // Controller 0 + { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 } // Controller 1 + }; + +/* Rcomp resistor */ +static const u16 rcomp_resistor = 100; + +/* Rcomp target */ +static const u16 RcompTarget[] = { 60, 40, 40, 40, 30 }; void mainboard_memory_init_params(FSPM_UPD *mupd) { - /* ToDo : Fill FSP-M memory params */ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + u8 spd_index = 1;//get_spd_index(); + + if (spd_index > 0 && spd_index != 2) { + struct region_device spd_rdev; + uintptr_t spd_ptr; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + spd_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); +#if 0 + mem_cfg->MemorySpdPtr00 = spd_ptr; + mem_cfg->MemorySpdPtr02 = spd_ptr; + mem_cfg->MemorySpdPtr04 = spd_ptr; + mem_cfg->MemorySpdPtr06 = spd_ptr; +#endif + mem_cfg->MemorySpdPtr08 = spd_ptr; + mem_cfg->MemorySpdPtr10 = spd_ptr; + mem_cfg->MemorySpdPtr12 = spd_ptr; + mem_cfg->MemorySpdPtr14 = spd_ptr; + + mem_cfg->SpdAddressTable[0] = 0x0; + mem_cfg->SpdAddressTable[1] = 0x0; + mem_cfg->SpdAddressTable[2] = 0x0; + mem_cfg->SpdAddressTable[3] = 0x0; + } else { + mem_cfg->MemorySpdPtr00 = 0; + mem_cfg->MemorySpdPtr01 = 0; + mem_cfg->MemorySpdPtr10 = 0; + mem_cfg->MemorySpdPtr11 = 0; + + mem_cfg->SpdAddressTable[0] = 0xA0; + mem_cfg->SpdAddressTable[1] = 0xA2; + mem_cfg->SpdAddressTable[2] = 0xA4; + mem_cfg->SpdAddressTable[3] = 0xA6; + } + + memcpy(&mem_cfg->DqMapCpu2DramCh0, dq_map, sizeof(dq_map)); + memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); + mem_cfg->RcompResistor = rcomp_resistor; + memcpy(&mem_cfg->RcompTarget, RcompTarget, sizeof(RcompTarget)); } diff --git a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex new file mode 100644 index 0000000..6955f2c --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 1B 21 F0 08 00 40 00 00 0A 01 00 00 +00 00 05 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 92 00 A7 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 56 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/Makefile.inc b/src/mainboard/intel/tglrvp/spd/Makefile.inc index b8b059a..e24f576 100644 --- a/src/mainboard/intel/tglrvp/spd/Makefile.inc +++ b/src/mainboard/intel/tglrvp/spd/Makefile.inc @@ -13,8 +13,27 @@ ## GNU General Public License for more details. ## -romstage-y += spd_util.c - SPD_BIN = $(obj)/spd.bin -SPD_SOURCES = empty # 0b000 +SPD_SOURCES = empty # 0b000 +SPD_SOURCES += Micron-MT53D1G64D8SQ-046 +SPD_SOURCES += Samsung-K4UBE3D4AA-MGCL +SPD_SOURCES += Hynix-H9HKNNNEBMAV-4267 + +ifeq ($(SPD_SOURCES),) + SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) +else + SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) +endif + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex new file mode 100644 index 0000000..40fccaa --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex @@ -0,0 +1,32 @@ +23 10 11 0E 15 19 95 08 00 40 00 00 02 21 00 00 +48 00 05 FF 92 55 00 00 8C 00 90 A8 90 90 06 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex new file mode 100644 index 0000000..95a495e --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 16 21 95 08 00 40 00 00 0A 01 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/spd.h b/src/mainboard/intel/tglrvp/spd/spd.h index ed8b8b6..283a5c6 100644 --- a/src/mainboard/intel/tglrvp/spd/spd.h +++ b/src/mainboard/intel/tglrvp/spd/spd.h @@ -16,14 +16,17 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -#include <stdint.h> - #define RCOMP_TARGET_PARAMS 0x5 -void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr); -void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr); -void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr); -void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr); -void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr); -void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr); +/* SPD index definition should be matched with the order of SPD_SOURCES */ +#define SPD_ID_MICRON 0x0 +#define SPD_ID_SAMSUNG 0x1 +#define SPD_ID_HYNIX 0x2 + +void mainboard_fill_dq_map_ch0(void *dq_map_ptr); +void mainboard_fill_dq_map_ch1(void *dq_map_ptr); +void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); #endif diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc index 23bf160..2baf643 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc @@ -13,6 +13,11 @@ ## GNU General Public License for more details. ## +## Memory Options +SPD_SOURCES = Micron-MT53D1G64D8SQ-046 +SPD_SOURCES += Samsung-K4UBE3D4AA-MGCL +SPD_SOURCES += Hynix-H9HKNNNEBMAV-4267 + bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 76ceb30..2a1c49c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -4,37 +4,25 @@ device lapic 0 on end end - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - # FSP configuration - register "SaGv" = "SaGv_Enabled" + register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "SdCardPowerEnableActiveHigh" = "1" - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4 - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 - register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port1 - register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth + register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port3 + register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port4 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # USB3/USB2 Flex Connector # Enable Pch iSCLK register "pch_isclk" = "1" @@ -45,79 +33,20 @@ # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" + register "PrmrrSize" = "0x10000000" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "0" - register "PcieRpEnable[2]" = "0" - register "PcieRpEnable[3]" = "0" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" + register "PcieRpEnable[9]" = "1" - register "PcieClkSrcUsage[0]" = "2" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "0xC" - register "PcieClkSrcUsage[3]" = "0x70" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "0xE" - register "PcieClkSrcUsage[6]" = "0x80" - register "PcieClkSrcUsage[7]" = "0x80" - register "PcieClkSrcUsage[8]" = "0x80" - register "PcieClkSrcUsage[9]" = "0x80" - register "PcieClkSrcUsage[10]" = "0x80" - register "PcieClkSrcUsage[11]" = "0x80" - register "PcieClkSrcUsage[12]" = "0x80" - register "PcieClkSrcUsage[13]" = "0x80" - register "PcieClkSrcUsage[14]" = "0x80" - register "PcieClkSrcUsage[15]" = "0x80" - - register "PcieClkSrcClkReq[0]" = "0" register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieClkSrcClkReq[6]" = "6" - register "PcieClkSrcClkReq[7]" = "7" - register "PcieClkSrcClkReq[8]" = "8" - register "PcieClkSrcClkReq[9]" = "9" - register "PcieClkSrcClkReq[10]" = "10" - register "PcieClkSrcClkReq[11]" = "11" - register "PcieClkSrcClkReq[12]" = "12" - register "PcieClkSrcClkReq[13]" = "13" - register "PcieClkSrcClkReq[14]" = "14" - register "PcieClkSrcClkReq[15]" = "15" - register "SataEnable" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsEnable[3]" = "1" - register "SataPortsEnable[4]" = "1" - register "SataPortsEnable[5]" = "1" - register "SataPortsEnable[6]" = "1" - register "SataPortsEnable[7]" = "1" - - register "SataPortsDevSlp[0]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsDevSlp[2]" = "1" - register "SataPortsDevSlp[3]" = "1" - register "SataPortsDevSlp[4]" = "1" - register "SataPortsDevSlp[5]" = "1" - register "SataPortsDevSlp[6]" = "1" - register "SataPortsDevSlp[7]" = "1" + register "PcieClkSrcUsage[1]" = "0x2" + register "PcieClkSrcUsage[2]" = "0x3" + register "PcieClkSrcUsage[3]" = "0x8" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -130,208 +59,99 @@ register "SerialIoGSpiMode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" register "SerialIoGSpiCsMode" = "{ - [PchSerialIoIndexGSPI0] = 1, - [PchSerialIoIndexGSPI1] = 1, - [PchSerialIoIndexGSPI2] = 1, + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, }" register "SerialIoGSpiCsState" = "{ [PchSerialIoIndexGSPI0] = 0, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, }" register "SerialIoUartMode" = "{ [PchSerialIoIndexUART0] = PchSerialIoDisabled, [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoSkipInit, - }" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # Enable DPTF - register "dptf_enable" = "1" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - # Enable S0ix - register "s0ix_enable" = "0" - - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .gspi[1] = { - .speed_mhz = 1, - .early_init = 1, - }, + [PchSerialIoIndexUART2] = PchSerialIoPci, }" device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 12.0 off end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Lower"" - register "type" = "UPC_TYPE_A" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 2"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 3"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.5 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 4"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.6 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Upper"" - register "type" = "UPC_TYPE_A" - device usb 2.7 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Right Lower"" - register "type" = "UPC_TYPE_A" - device usb 2.8 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Right Upper"" - register "type" = "UPC_TYPE_A" - device usb 2.9 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Lower"" - register "type" = "UPC_TYPE_A" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Upper"" - register "type" = "UPC_TYPE_A" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""WLAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused1"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused2"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused3"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 off end # PMC SRAM - chip drivers/intel/wifi - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end - device pci 14.5 on end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""ALPS0000"" - register "generic.desc" = ""Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)" - register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end - end - end # I2C 0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_PCI_EXP" - device pci 00.0 on end - end - end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 on - chip drivers/spi/acpi - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""google,cr50"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - device spi 0 on end - end - end # GSPI #1 - device pci 1f.0 on end # eSPI Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + #From EDS(575683) + device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF 0x9A03 + device pci 05.0 on end # IPU 0x9A19 + device pci 06.0 on end # PEG60 0x9A09 + device pci 07.0 off end # TBT_PCIe0 0x9A23 + device pci 07.1 off end # TBT_PCIe1 0x9A25 + device pci 07.2 off end # TBT_PCIe2 0x9A27 + device pci 07.3 off end # TBT_PCIe3 0x9A29 + device pci 08.0 off end # GNA 0x9A11 + device pci 09.0 off end # NPK 0x9A33 + device pci 0a.0 off end # Crash-log SRAM 0x9A0D + device pci 0d.0 on end # USB xHCI 0x9A13 + device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 + device pci 0d.2 off end # TBT DMA0 0x9A1B + device pci 0d.3 off end # TBT DMA1 0x9A1D + device pci 0e.0 on end # VMD 0x9A0B + + # From PCH EDS(576591) + device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.6 off end # THC0 0xA0D0 + device pci 10.7 off end # THC1 0xA0D1 + device pci 12.0 off end # SensorHUB 0xA0FC + device pci 12.6 off end # GSPI2 0x34FB + device pci 13.0 off end # GSPI3 0xA0FD + device pci 14.0 on end # USB3.1 xHCI 0xA0ED + device pci 14.1 on end # USB3.1 xDCI 0xA0EE + device pci 14.2 on end # Shared RAM 0xA0EF + device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 + device pci 15.0 on end # I2C0 0xA0E8 + device pci 15.1 on end # I2C1 0xA0E9 + device pci 15.2 on end # I2C2 0xA0EA + device pci 15.3 on end # I2C3 0xA0EB + device pci 16.0 on end # HECI1 0xA0E0 + device pci 16.1 off end # HECI2 0xA0E1 + device pci 16.2 off end # CSME 0xA0E2 + device pci 16.3 off end # CSME 0xA0E3 + device pci 16.4 off end # HECI3 0xA0E4 + device pci 16.5 off end # HECI4 0xA0E5 + device pci 17.0 off end # SATA 0xA0D3 + device pci 19.0 off end # I2C4 0xA0C5 + device pci 19.1 on end # I2C5 0xA0C6 + device pci 19.2 on end # UART2 0xA0C7 + device pci 1c.0 off end # RP1 0xA0B8 + device pci 1c.1 off end # RP2 0xA0B9 + device pci 1c.2 on end # RP3 0xA0BA + device pci 1c.3 on end # RP4 0xA0BB + device pci 1c.4 off end # RP5 0xA0BC + device pci 1c.5 off end # RP6 0xA0BD + device pci 1c.6 off end # RP7 0xA0BE + device pci 1c.7 off end # RP8 0xA0BF + device pci 1d.0 on end # RP9 0xA0B0 + device pci 1d.1 off end # RP10 0xA0B1 + device pci 1d.2 on end # RP11 0xA0B2 + device pci 1d.3 off end # RP12 0xA0B3 + device pci 1e.0 off end # UART0 0xA0A8 + device pci 1e.1 off end # UART1 0xA0A9 + device pci 1e.2 off end # GSPI0 0xA0AA + device pci 1e.3 off end # GSPI1 0xA0AB + device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1f.1 on end # P2SB 0xA0A0 + device pci 1f.2 on end # PMC 0xA0A1 + device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF + device pci 1f.4 on end # SMBus 0xA0A3 + device pci 1f.5 on end # SPI 0xA0A4 + device pci 1f.6 off end # GbE 0x15E1/0x15E2 + device pci 1f.7 off end # TH 0xA0A6 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3fd54b051effb9eb2303e0db2217dd28f857368 Gerrit-Change-Number: 37928 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: src/mainboard/system76: Add System76 Lemur Pro (lemp9)
by Jeremy Soller (Code Review) 13 Apr '20

13 Apr '20

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38463 ) Change subject: src/mainboard/system76: Add System76 Lemur Pro (lemp9) ...................................................................... src/mainboard/system76: Add System76 Lemur Pro (lemp9) Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: Ib0a32bbc6f89a662085ab4a254676bc1fad7dc60 --- A src/mainboard/system76/Kconfig A src/mainboard/system76/Kconfig.name A src/mainboard/system76/lemp9/Kconfig A src/mainboard/system76/lemp9/Kconfig.name A src/mainboard/system76/lemp9/Makefile.inc A src/mainboard/system76/lemp9/acpi/ac.asl A src/mainboard/system76/lemp9/acpi/battery.asl A src/mainboard/system76/lemp9/acpi/buttons.asl A src/mainboard/system76/lemp9/acpi/ec.asl A src/mainboard/system76/lemp9/acpi/ec_ram.asl A src/mainboard/system76/lemp9/acpi/gpe.asl A src/mainboard/system76/lemp9/acpi/hid.asl A src/mainboard/system76/lemp9/acpi/lid.asl A src/mainboard/system76/lemp9/acpi/mainboard.asl A src/mainboard/system76/lemp9/acpi/s76.asl A src/mainboard/system76/lemp9/acpi/sleep.asl A src/mainboard/system76/lemp9/acpi_tables.c A src/mainboard/system76/lemp9/board_info.txt A src/mainboard/system76/lemp9/bootblock.c A src/mainboard/system76/lemp9/devicetree.cb A src/mainboard/system76/lemp9/dsdt.asl A src/mainboard/system76/lemp9/gpio.h A src/mainboard/system76/lemp9/hda_verb.c A src/mainboard/system76/lemp9/ramstage.c A src/mainboard/system76/lemp9/romstage.c A src/mainboard/system76/lemp9/spd/Makefile.inc A src/mainboard/system76/lemp9/spd/samsung-K4AAG165WA-BCTD.spd.hex A src/mainboard/system76/lemp9/variants/lemp9/data.vbt 28 files changed, 2,215 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/38463/1 diff --git a/src/mainboard/system76/Kconfig b/src/mainboard/system76/Kconfig new file mode 100644 index 0000000..62034a4 --- /dev/null +++ b/src/mainboard/system76/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_SYSTEM76 + +choice + prompt "Mainboard model" + +source "src/mainboard/system76/*/Kconfig.name" + +endchoice + +source "src/mainboard/system76/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "System76" + +endif diff --git a/src/mainboard/system76/Kconfig.name b/src/mainboard/system76/Kconfig.name new file mode 100644 index 0000000..7155721 --- /dev/null +++ b/src/mainboard/system76/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_SYSTEM76 + bool "System76" diff --git a/src/mainboard/system76/lemp9/Kconfig b/src/mainboard/system76/lemp9/Kconfig new file mode 100644 index 0000000..e4c0ee4 --- /dev/null +++ b/src/mainboard/system76/lemp9/Kconfig @@ -0,0 +1,107 @@ +if BOARD_SYSTEM76_LEMP9 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ADD_FSP_BINARIES + select BOARD_ROMSIZE_KB_16384 + select EC_ACPI + select EXCLUDE_EMMC_INTERFACE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SMI_HANDLER + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE +# select MAINBOARD_HAS_SPI_TPM_CR50 +# select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select PCIE_DEBUG_INFO + select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select USE_BLOBS + select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB + +config MAINBOARD_DIR + string + default system76/lemp9 + +config VARIANT_DIR + string + default "lemp9" if BOARD_SYSTEM76_LEMP9 + +config MAINBOARD_PART_NUMBER + string + default "lemp9" if BOARD_SYSTEM76_LEMP9 + +config MAINBOARD_SMBIOS_PRODUCT_NAME + string + default "Lemur Pro" + +config MAINBOARD_VERSION + string + default "lemp9" + +config CBFS_SIZE + hex + default 0xA00000 + +config SUBSYSTEM_VENDOR_ID + hex + default 0x1558 + +config SUBSYSTEM_DEVICE_ID + hex + default 0x1401 + +config CONSOLE_POST + bool + default y + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config UART_FOR_CONSOLE + int + default 2 + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_FILE + string + default "pci8086,9b41.rom" + +config VGA_BIOS_ID + string + default "8086,9b41" + +config FSP_M_XIP + bool + default y + +config POST_DEVICE + bool + default n + +#config DRIVER_TPM_SPI_BUS +# hex +# default 0x0 + +#config DRIVER_TPM_SPI_CHIP +# int +# default 2 + +endif diff --git a/src/mainboard/system76/lemp9/Kconfig.name b/src/mainboard/system76/lemp9/Kconfig.name new file mode 100644 index 0000000..4a4ab68 --- /dev/null +++ b/src/mainboard/system76/lemp9/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SYSTEM76_LEMP9 + bool "lemp9" diff --git a/src/mainboard/system76/lemp9/Makefile.inc b/src/mainboard/system76/lemp9/Makefile.inc new file mode 100644 index 0000000..b9082d2 --- /dev/null +++ b/src/mainboard/system76/lemp9/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += bootblock.c +ramstage-y += ramstage.c hda_verb.c +subdirs-y += spd diff --git a/src/mainboard/system76/lemp9/acpi/ac.asl b/src/mainboard/system76/lemp9/acpi/ac.asl new file mode 100644 index 0000000..7a55e45 --- /dev/null +++ b/src/mainboard/system76/lemp9/acpi/ac.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (AC) +{ + Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + + Name (ACFG, One) + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + Return (ACFG) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } +} diff --git a/src/mainboard/system76/lemp9/acpi/battery.asl b/src/mainboard/system76/lemp9/acpi/battery.asl new file mode 100644 index 0000000..bfda8a0 --- /dev/null +++ b/src/mainboard/system76/lemp9/acpi/battery.asl @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (BFCC, Zero) + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (^^PCI0.LPCB.EC0.ECOK) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + Else + { + Return (0x0F) + } + } + + Name (PBIF, Package (0x0D) + { + One, + 0xFFFFFFFF, + 0xFFFFFFFF, + One, + 0x39D0, + Zero, + Zero, + 0x40, + 0x40, + "BAT", + "0001", + "LION", + "Notebook" + }) + Method (IVBI, 0, NotSerialized) + { + PBIF [One] = 0xFFFFFFFF + PBIF [0x02] = 0xFFFFFFFF + PBIF [0x04] = 0xFFFFFFFF + PBIF [0x09] = " " + PBIF [0x0A] = " " + PBIF [0x0B] = " " + PBIF [0x0C] = " " + BFCC = Zero + } + + Method (UPBI, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF) + PBIF [One] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF) + PBIF [0x02] = Local0 + BFCC = Local0 + Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF) + PBIF [0x04] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF) + PBIF [0x05] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF) + PBIF [0x06] = Local0 + PBIF [0x09] = "BAT" + PBIF [0x0A] = "0001" + PBIF [0x0B] = "LION" + PBIF [0x0C] = "Notebook" + } + Else + { + IVBI () + } + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBI () + } + Else + { + IVBI () + } + + Return (PBIF) /* \_SB_.BAT0.PBIF */ + } + + Name (PBST, Package (0x04) + { + Zero, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0x3D90 + }) + Method (IVBS, 0, NotSerialized) + { + PBST [Zero] = Zero + PBST [One] = 0xFFFFFFFF + PBST [0x02] = 0xFFFFFFFF + PBST [0x03] = 0x2710 + } + + Method (UPBS, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = Zero + Local1 = Zero + If (^^AC.ACFG) + { + If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02)) + { + Local0 |= 0x02 + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) + } + } + Else + { + Local0 |= One + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) + } + + Local7 = (Local1 & 0x8000) + If ((Local7 == 0x8000)) + { + Local1 ^= 0xFFFF + } + + Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF) + Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF) + PBST [Zero] = Local0 + PBST [One] = Local1 + PBST [0x02] = Local2 + PBST [0x03] = Local3 + If ((BFCC != ^^PCI0.LPCB.EC0.BFC0)) + { + Notify (BAT0, 0x81) // Information Change + } + } + Else + { + IVBS () + } + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBS () + } + Else + { + IVBS () + } + + Return (PBST) /* \_SB_.BAT0.PBST */ + } +} diff --git a/src/mainboard/system76/lemp9/acpi/buttons.asl b/src/mainboard/system76/lemp9/acpi/buttons.asl new file mode 100644 index 0000000..4b59403 --- /dev/null +++ b/src/mainboard/system76/lemp9/acpi/buttons.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PWRB) +{ + Name (_HID, EisaId ("PNP0C0C")) + Name (_PRW, Package () { 0x29 /* GPP_D9 */, 3 }) +} + +Device (SLPB) +{ + Name (_HID, EisaId ("PNP0C0E")) + Name (_PRW, Package () { 0x29 /* GPP_D9 */, 3 }) +} diff --git a/src/mainboard/system76/lemp9/acpi/ec.asl b/src/mainboard/system76/lemp9/acpi/ec.asl new file mode 100644 index 0000000..56bf8f8 --- /dev/null +++ b/src/mainboard/system76/lemp9/acpi/ec.asl @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_GPE, 0x50 /* GPP_E16 */) // _GPE: General Purpose Events + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0062, // Range Minimum + 0x0062, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0066, // Range Minimum + 0x0066, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + }) + + #include "acpi/ec_ram.asl" + + Name (ECOK, Zero) + Method (_REG, 2, Serialized) // _REG: Region Availability + { + Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1)))) + If (((Arg0 == 0x03) && (Arg1 == One))) { + // Enable hardware touchpad lock, airplane mode, and keyboard backlight keys + ECOS = 1 + + // Enable software display brightness keys + WINF = 1 + + // Set current AC state + ^^^^AC.ACFG = ADP + // Update battery information and status + ^^^^BAT0.UPBI() + ^^^^BAT0.UPBS() + + PNOT () + + // EC is now available + ECOK = Arg1 + + // Reset System76 Device + ^^^^S76D.RSET() + } + } + + Method (PTS, 1, Serialized) { + Debug = Concatenate("EC: PTS: ", ToHexString(Arg0)) + If (ECOK) { + // Clear wake cause + WFNO = Zero + } + } + + Method (WAK, 1, Serialized) { + Debug = Concatenate("EC: WAK: ", ToHexString(Arg0)) + If (ECOK) { + // Set current AC state + ^^^^AC.ACFG = ADP + + // Update battery information and status + ^^^^BAT0.UPBI() + ^^^^BAT0.UPBS() + + // Notify of changes + Notify(^^^^AC, Zero) + Notify(^^^^BAT0, Zero) + + Sleep (1000) + + // Reset System76 Device + ^^^^S76D.RSET() + } + } + + Method (_Q0A, 0, NotSerialized) // Touchpad Toggle + { + Debug = "EC: Touchpad Toggle" + } + + Method (_Q0B, 0, NotSerialized) // Screen Toggle + { + Debug = "EC: Screen Toggle" + } + + Method (_Q0C, 0, NotSerialized) // Mute + { + Debug = "EC: Mute" + } + + Method (_Q0D, 0, NotSerialized) // Keyboard Backlight + { + Debug = "EC: Keyboard Backlight" + } + + Method (_Q0E, 0, NotSerialized) // Volume Down + { + Debug = "EC: Volume Down" + } + + Method (_Q0F, 0, NotSerialized) // Volume Up + { + Debug = "EC: Volume Up" + } + + Method (_Q10, 0, NotSerialized) // Switch Video Mode + { + Debug = "EC: Switch Video Mode" + } + + Method (_Q11, 0, NotSerialized) // Brightness Down + { + Debug = "EC: Brightness Down" + ^^^^HIDD.HPEM (20) + } + + Method (_Q12, 0, NotSerialized) // Brightness Up + { + Debug = "EC: Brightness Up" + ^^^^HIDD.HPEM (19) + } + + Method (_Q13, 0, NotSerialized) // Camera Toggle + { + Debug = "EC: Camera Toggle" + } + + Method (_Q14, 0, NotSerialized) // Airplane Mode + { + Debug = "EC: Airplane Mode" + // Only send HIDD message when hardware airplane mode not in use + If (ECOS == 2) { + ^^^^HIDD.HPEM (8) + } + } + + Method (_Q15, 0, NotSerialized) // Suspend Button + { + Debug = "EC: Suspend Button" + Notify (SLPB, 0x80) + } + + Method (_Q16, 0, NotSerialized) // AC Detect + { + Debug = "EC: AC Detect" + ^^^^AC.ACFG = ADP + Notify (AC, 0x80) // Status Change + Sleep (0x01F4) + If (BAT0) + { + Notify (^^^^BAT0, 0x81) // Information Change + Sleep (0x32) + Notify (^^^^BAT0, 0x80) // Status Change + Sleep (0x32) + } + } + + Method (_Q17, 0, NotSerialized) // BAT0 Update + { + Debug = "EC: BAT0 Update (17)" + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q19, 0, NotSerialized) // BAT0 Update + { + Debug = "EC: BAT0 Update (19)" + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q1B, 0, NotSerialized) // Lid Close + { + Debug = "EC: Lid Close" + Notify (LID0, 0x80) + } + + Method (_Q1C, 0, NotSerialized) // Thermal Trip + { + Debug = "EC: Thermal Trip" + /* TODO + Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change + Notify (\_TZ.TZ0, 0x80) // Thermal Status Change + */ + } + + Method (_Q1D, 0, NotSerialized) // Power Button + { + Debug = "EC: Power Button" + Notify (PWRB, 0x80) + } + + Method (_Q50, 0, NotSerialized) // Other Events + { + Local0 = OEM4 + If (Local0 == 0x8A) { + Debug = "EC: White Keyboard Backlight" + Notify (^^^^S76D, 0x80) + } ElseIf (Local0 == 0x9F) { + Debug = "EC: Color Keyboard Toggle" + Notify (^^^^S76D, 0x81) + } ElseIf (Local0 == 0x81) { + Debug = "EC: Color Keyboard Down" + Notify (^^^^S76D, 0x82) + } ElseIf (Local0 == 0x82) { + Debug = "EC: Color Keyboard Up" + Notify (^^^^S76D, 0x83) + } ElseIf (Local0 == 0x80) { + Debug = "EC: Color Keyboard Color Change" + Notify (^^^^S76D, 0x84) + } Else { + Debug = Concatenate("EC: Other: ", ToHexString(Local0)) + } + } +} diff --git a/src/mainboard/system76/lemp9/acpi/ec_ram.asl b/src/mainboard/system76/lemp9/acpi/ec_ram.asl new file mode 100644 index 0000000..9502f5f0 --- /dev/null +++ b/src/mainboard/system76/lemp9/acpi/ec_ram.asl @@ -0,0 +1,188 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) +Field (ERAM, ByteAcc, Lock, Preserve) +{ + NMSG, 8, + SLED, 4, + Offset (0x02), + MODE, 1, + FAN0, 1, + TME0, 1, + TME1, 1, + FAN1, 1, + , 2, + Offset (0x03), + LSTE, 1, + LSW0, 1, + LWKE, 1, + WAKF, 1, + , 2, + PWKE, 1, + MWKE, 1, + AC0, 8, + PSV, 8, + CRT, 8, + TMP, 8, + AC1, 8, + BBST, 8, + Offset (0x0B), + Offset (0x0C), + Offset (0x0D), + Offset (0x0E), + SLPT, 8, + SWEJ, 1, + SWCH, 1, + Offset (0x10), + ADP, 1, + AFLT, 1, + BAT0, 1, + BAT1, 1, + , 3, + PWOF, 1, + WFNO, 8, + BPU0, 32, + BDC0, 32, + BFC0, 32, + BTC0, 32, + BDV0, 32, + BST0, 32, + BPR0, 32, + BRC0, 32, + BPV0, 32, + BTP0, 16, + BRS0, 16, + BCW0, 32, + BCL0, 32, + BCG0, 32, + BG20, 32, + BMO0, 64, + BIF0, 64, + BSN0, 32, + BTY0, 64, + Offset (0x67), + Offset (0x68), + ECOS, 8, + LNXD, 8, + ECPS, 8, + Offset (0x6C), + BTMP, 16, + EVTN, 8, + Offset (0x72), + PRCL, 8, + PRC0, 8, + PRC1, 8, + PRCM, 8, + PRIN, 8, + PSTE, 8, + PCAD, 8, + PEWL, 8, + PWRL, 8, + PECD, 8, + PEHI, 8, + PECI, 8, + PEPL, 8, + PEPM, 8, + PWFC, 8, + PECC, 8, + PDT0, 8, + PDT1, 8, + PDT2, 8, + PDT3, 8, + PRFC, 8, + PRS0, 8, + PRS1, 8, + PRS2, 8, + PRS3, 8, + PRS4, 8, + PRCS, 8, + PEC0, 8, + PEC1, 8, + PEC2, 8, + PEC3, 8, + CMDR, 8, + CVRT, 8, + GTVR, 8, + FANT, 8, + SKNT, 8, + AMBT, 8, + MCRT, 8, + DIM0, 8, + DIM1, 8, + PMAX, 8, + PPDT, 8, + PECH, 8, + PMDT, 8, + TSD0, 8, + TSD1, 8, + TSD2, 8, + TSD3, 8, + CPUP, 16, + MCHP, 16, + SYSP, 16, + CPAP, 16, + MCAP, 16, + SYAP, 16, + CFSP, 16, + CPUE, 16, + Offset (0xC6), + Offset (0xC7), + VGAT, 8, + OEM1, 8, + OEM2, 8, + OEM3, 16, + OEM4, 8, + Offset (0xCE), + DUT1, 8, + DUT2, 8, + RPM1, 16, + RPM2, 16, + RPM4, 16, + Offset (0xD7), + DTHL, 8, + DTBP, 8, + AIRP, 8, + WINF, 8, + RINF, 8, + Offset (0xDD), + INF2, 8, + MUTE, 1, + Offset (0xE0), + RPM3, 16, + ECKS, 8, + Offset (0xE4), + , 4, + XTUF, 1, + EP12, 1, + Offset (0xE5), + INF3, 8, + Offset (0xE7), + GFOF, 8, + Offset (0xE9), + KPCR, 1, + Offset (0xEA), + Offset (0xF0), + PL1T, 16, + PL2T, 16, + TAUT, 8, + Offset (0xF8), + FCMD, 8, + FDAT, 8, + FBUF, 8, + FBF1, 8, + FBF2, 8, + FBF3, 8 +} diff --git a/src/mainboard/system76/lemp9/acpi/gpe.asl b/src/mainboard/system76/lemp9/acpi/gpe.asl new file mode 100644 index 0000000..d24d53e --- /dev/null +++ b/src/mainboard/system76/lemp9/acpi/gpe.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// GPP_D9 SCI +Method (_L29, 0, Serialized) { + Debug = Concatenate("GPE _L29: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) + If (\_SB.PCI0.LPCB.EC0.ECOK) { + If (\_SB.PCI0.LPCB.EC0.WFNO == One) { + Notify(\_SB.LID0, 0x80) + } + } +} diff --git a/src/mainboard/system76/lemp9/acpi/hid.asl b/src/mainboard/system76/lemp9/acpi/hid.asl new file mode 100644 index 0000000..c75fefa --- /dev/null +++ b/src/mainboard/system76/lemp9/acpi/hid.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (HIDD) +{ + Name (_HID, "INT33D5") + Name (HBSY, Zero) + Name (HIDX, Zero) + Name (HRDY, Zero) + + Method (HDEM, 0, Serialized) + { + HBSY = Zero + Return (HIDX) + } + + Method (HDMM, 0, Serialized) + { + Return (Zero) + } + + Method (HDSM, 1, Serialized) + { + HRDY = Arg0 + } + + Method (HPEM, 1, Serialized) + { + HBSY = One + HIDX = Arg0 + + Notify (HIDD, 0xC0) + Local0 = Zero + While (((Local0 < 0xFA) && HBSY)) + { + Sleep (0x04) + Local0++ + } + + If ((HBSY == One)) + { + HBSY = Zero + HIDX = Zero + Return (One) + } + Else + { + Return (Zero) + } + } +} diff --git a/src/mainboard/system76/lemp9/acpi/lid.asl b/src/mainboard/system76/lemp9/acpi/lid.asl new file mode 100644 index 0000000..0a86880 --- /dev/null +++ b/src/mainboard/system76/lemp9/acpi/lid.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D")) + Name (_PRW, Package () { 0x29 /* GPP_D9 */, 3 }) + + Method (_LID, 0, NotSerialized) { + DEBUG = "LID: _LID" + If (^^PCI0.LPCB.EC0.ECOK) { + Return (^^PCI0.LPCB.EC0.LSTE) + } Else { + Return (One) + } + } + + Method (_PSW, 1, NotSerialized) { + DEBUG = Concatenate("LID: _PSW: ", ToHexString(Arg0)) + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.LWKE = Arg0 + } + } +} diff --git a/src/mainboard/system76/lemp9/acpi/mainboard.asl b/src/mainboard/system76/lemp9/acpi/mainboard.asl new file mode 100644 index 0000000..20b5694 --- /dev/null +++ b/src/mainboard/system76/lemp9/acpi/mainboard.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define COLOR_KEYBOARD 0 + +Scope (\_SB) { + #include "ac.asl" + #include "battery.asl" + #include "buttons.asl" + #include "hid.asl" + #include "lid.asl" + #include "s76.asl" + #include "sleep.asl" +} + +Scope (_GPE) { + #include "gpe.asl" +} diff --git a/src/mainboard/system76/lemp9/acpi/s76.asl b/src/mainboard/system76/lemp9/acpi/s76.asl new file mode 100644 index 0000000..06ad9a6 --- /dev/null +++ b/src/mainboard/system76/lemp9/acpi/s76.asl @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Notifications: +// 0x80 - hardware backlight toggle +// 0x81 - backlight toggle +// 0x82 - backlight down +// 0x83 - backlight up +// 0x84 - backlight color change +Device (S76D) { + Name (_HID, "17761776") + Name (_UID, 0) + + Method (RSET, 0, Serialized) { + Debug = "S76D: RSET" + SAPL(0) + SKBL(0) + #if COLOR_KEYBOARD + SKBC(0xFFFFFF) + #endif + } + + Method (INIT, 0, Serialized) { + Debug = "S76D: INIT" + RSET() + If (^^PCI0.LPCB.EC0.ECOK) { + // Set flags to use software control + ^^PCI0.LPCB.EC0.ECOS = 2 + Return (0) + } Else { + Return (1) + } + } + + Method (FINI, 0, Serialized) { + Debug = "S76D: FINI" + RSET() + If (^^PCI0.LPCB.EC0.ECOK) { + // Set flags to use hardware control + ^^PCI0.LPCB.EC0.ECOS = 1 + Return (0) + } Else { + Return (1) + } + } + + // Get Airplane LED + Method (GAPL, 0, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + If (^^PCI0.LPCB.EC0.AIRP & 0x40) { + Return (1) + } + } + Return (0) + } + + // Set Airplane LED + Method (SAPL, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0) { + ^^PCI0.LPCB.EC0.AIRP |= 0x40 + } Else { + ^^PCI0.LPCB.EC0.AIRP &= 0xBF + } + } + } + +#if COLOR_KEYBOARD + // Set KB LED Brightness + Method (SKBL, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 6 + ^^PCI0.LPCB.EC0.FBUF = Arg0 + ^^PCI0.LPCB.EC0.FBF1 = 0 + ^^PCI0.LPCB.EC0.FBF2 = Arg0 + ^^PCI0.LPCB.EC0.FCMD = 0xCA + } + } + + // Set Keyboard Color + Method (SKBC, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 0x3 + ^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF) + ^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF) + ^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF) + ^^PCI0.LPCB.EC0.FCMD = 0xCA + Return (Arg0) + } Else { + Return (0) + } + } +#else + // Get KB LED + Method (GKBL, 0, Serialized) { + Local0 = 0 + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = One + ^^PCI0.LPCB.EC0.FCMD = 0xCA + Local0 = ^^PCI0.LPCB.EC0.FBUF + ^^PCI0.LPCB.EC0.FCMD = Zero + } + Return (Local0) + } + + // Set KB Led + Method (SKBL, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = Zero + ^^PCI0.LPCB.EC0.FBUF = Arg0 + ^^PCI0.LPCB.EC0.FCMD = 0xCA + } + } +#endif +} diff --git a/src/mainboard/system76/lemp9/acpi/sleep.asl b/src/mainboard/system76/lemp9/acpi/sleep.asl new file mode 100644 index 0000000..9a3ecaa --- /dev/null +++ b/src/mainboard/system76/lemp9/acpi/sleep.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) { + \_SB.PCI0.LPCB.EC0.PTS (Arg0) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) { + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/system76/lemp9/acpi_tables.c b/src/mainboard/system76/lemp9/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/system76/lemp9/acpi_tables.c diff --git a/src/mainboard/system76/lemp9/board_info.txt b/src/mainboard/system76/lemp9/board_info.txt new file mode 100644 index 0000000..f6784ef --- /dev/null +++ b/src/mainboard/system76/lemp9/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: System76 +Board name: lemp9 +Category: laptop +Release year: 2020 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/system76/lemp9/bootblock.c b/src/mainboard/system76/lemp9/bootblock.c new file mode 100644 index 0000000..3a24b28 --- /dev/null +++ b/src/mainboard/system76/lemp9/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <gpio.h> +#include "gpio.h" + +void bootblock_mainboard_init(void) { + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb new file mode 100644 index 0000000..4f075af --- /dev/null +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -0,0 +1,241 @@ +chip soc/intel/cannonlake + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + +# ACPI (soc/intel/cannonlake/acpi.c) + # Enable s0ix + register "s0ix_enable" = "0" + + # PM Timer Enabled + register "PmTimerDisabled" = "0" + + # Disable DPTF + register "dptf_enable" = "0" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "25" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "SaGv" = "SaGv_Enabled" + #register "enable_c6dram" = "1" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # SATA + register "SataMode" = "Sata_AHCI" + register "SataSalpSupport" = "0" + + register "SataPortsEnable[0]" = "0" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "0" + register "SataPortsEnable[4]" = "0" + register "SataPortsEnable[5]" = "0" + register "SataPortsEnable[6]" = "0" + register "SataPortsEnable[7]" = "0" + + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataPortsDevSlp[3]" = "0" + register "SataPortsDevSlp[4]" = "0" + register "SataPortsDevSlp[5]" = "0" + register "SataPortsDevSlp[6]" = "0" + register "SataPortsDevSlp[7]" = "0" + + # Audio + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + register "PchHdaAudioLinkDmic0" = "1" + register "PchHdaAudioLinkDmic1" = "1" + register "PchHdaAudioLinkSsp0" = "0" + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkSsp2" = "0" + register "PchHdaAudioLinkSndw1" = "0" + register "PchHdaAudioLinkSndw2" = "0" + register "PchHdaAudioLinkSndw3" = "0" + register "PchHdaAudioLinkSndw4" = "0" + + # USB + register "SsicPortEnable" = "0" + + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 3 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # NC + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by card reader + register "usb3_ports[6]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[7]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC + + + # PCI Express root port #6 x1, Clock 3 (card reader) + register "PcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[3]" = "5" + register "PcieClkSrcClkReq[3]" = "3" + + # PCI Express root port #8 x1, Clock 2 (WLAN) + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + register "PcieClkSrcUsage[2]" = "7" + register "PcieClkSrcClkReq[2]" = "2" + + # PCI Express root port #9 x4, Clock 4 (SSD2) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[4]" = "8" + register "PcieClkSrcClkReq[4]" = "4" + + # PCI Express root port #13 x4, Clock 5 (SSD1) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[5]" = "12" + register "PcieClkSrcClkReq[5]" = "5" + + # Misc + register "Device4Enable" = "0" + register "HeciEnabled" = "0" + register "Heci3Enabled" = "0" + register "AcousticNoiseMitigation" = "1" + #register "dmipwroptimize" = "1" + #register "satapwroptimize" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "2" # 500ms + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "12" + + # Serial IRQ Continuous + register "SerialIrqConfigSirqMode" = "1" + +# LPC (soc/intel/cannonlake/lpc.c) + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x80 - 0x8F + register "gen1_dec" = "0x000c0081" + # Address 0x88: Decode 0x68 - 0x6F + register "gen2_dec" = "0x00040069" + # Address 0x8C: Decode 0x3320 - 0x332F + register "gen3_dec" = "0x000c3321" + # Address 0x90: Disabled + register "gen4_dec" = "0x00000000" + +# PMC (soc/intel/cannonlake/pmc.c) + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_C" + register "gpe0_dw1" = "PMC_GPP_D" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + #chip drivers/intel/wifi + # register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + #end + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 on end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/system76/lemp9/dsdt.asl b/src/mainboard/system76/lemp9/dsdt.asl new file mode 100644 index 0000000..a42052f --- /dev/null +++ b/src/mainboard/system76/lemp9/dsdt.asl @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/cannonlake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + } + + // Chipset specific sleep states + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (\_SB.PCI0.LPCB) { + // PS/2 bus + #include <drivers/pc80/pc/ps2_controller.asl> + + // Embedded controller + #include "acpi/ec.asl" + } + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/system76/lemp9/gpio.h b/src/mainboard/system76/lemp9/gpio.h new file mode 100644 index 0000000..0d8737a --- /dev/null +++ b/src/mainboard/system76/lemp9/gpio.h @@ -0,0 +1,547 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +#define PAD_CFG_NC(pad) PAD_NC(pad, NONE) + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + // UART2 + // UART2_RXD + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + // UART2_TXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + // NC + PAD_CFG_NC(GPP_C22), + // NC + PAD_CFG_NC(GPP_C23), +}; + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +// GPD + // Power Management + // PM_BATLOW# + PAD_CFG_NC(GPD0), + // AC_PRESENT + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), + // NC + PAD_CFG_NC(GPD2), + // PWR_BTN# + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), + // SUSB#_PCH + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + // SUSC#_PCH + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + // SLP_A# + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + + // GPIO + // NC + PAD_CFG_NC(GPD7), + + // Clock Signals + // SUS_CLK + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + + // Power Management + // GPD9_RTD3 + PAD_CFG_NC(GPD9), + // NC + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + // NC + PAD_CFG_NC(GPD11), + +// GPP_A + // LPC + // SB_KBCRST# + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + // LPC_AD0 + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + // LPC_AD1 + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + // LPC_AD2 + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + // LPC_AD3 + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + // LPC_FRAME# + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + // SERIRQ with pull up + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + + // GSPI0 + // TODO - TPM_PIRQ# + PAD_CFG_NC(GPP_A7), + + // LPC + // PM_CLKRUN# with pull-up + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + // PCLK_KBC + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + // NC + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), + + // GSPI1 + // INTP_OUT + _PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000), + + // ISH_GP + // PCH_GPP_A12 + PAD_CFG_NC(GPP_A12), + + // Power Management + // SUSWARN# + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + + // LPC + // NC + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + + // Power Management + // SUS_PWR_ACK + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), + + // SD + // NC + PAD_CFG_NC(GPP_A16), + // LIGHT_KB_DET# + PAD_CFG_NC(GPP_A17), + + // ISH_GP + // NC + PAD_CFG_NC(GPP_A18), + // SATA_PWR_EN + PAD_CFG_GPO(GPP_A19, 1, DEEP), + // TEST_R + PAD_CFG_TERM_GPO(GPP_A20, 0, NONE, DEEP), + // NC + PAD_CFG_NC(GPP_A21), + // NC + PAD_CFG_NC(GPP_A22), + // NC + PAD_CFG_NC(GPP_A23), + +// GPP_B + // Power + // CORE_VID0 + PAD_CFG_NC(GPP_B0), + // CORE_VID1 + PAD_CFG_NC(GPP_B1), + + // Power Management + // CNVI_WAKE# + PAD_CFG_NC(GPP_B2), + + // CPU Misc + // GPP_B3 + _PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0000), + // NC + PAD_CFG_NC(GPP_B4), + + // Clock Signals + // NC + PAD_CFG_NC(GPP_B5), + // NC + PAD_CFG_NC(GPP_B6), + // WLAN_CLKREQ# + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + // LAN_CLKREQ# + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + // TBT_CLKREQ# + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + // SSD_CLKREQ# + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + + // Power Management + // EXT_PWR_GATE# + PAD_CFG_NC(GPP_B11), + // SLP_S0# + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + // PLT_RST# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + // SPKR + // PCH_SPKR + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + + // GSPI0 + // NC + PAD_CFG_NC(GPP_B15), + // PCH_GPP_B16 + PAD_CFG_NC(GPP_B16), + // PCH_GPP_B17 + PAD_CFG_NC(GPP_B17), + // PCH_GPP_B18 - strap for disabling no reboot mode + PAD_CFG_NC(GPP_B18), + + // GSPI1 + // NC + PAD_CFG_NC(GPP_B19), + // NC + PAD_CFG_NC(GPP_B20), + // NC + PAD_CFG_NC(GPP_B21), + // PCH_GPP_B22 + PAD_CFG_NC(GPP_B22), + + // SMBUS + // NC + PAD_CFG_NC(GPP_B23), + +// GPP_C + // SMBUS + // SMB_CLK_DDR + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + // SMB_DAT_DDR + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + // PCH_GPP_C2 with pull-up + PAD_CFG_NC(GPP_C2), + // NC + PAD_CFG_NC(GPP_C3), + // NC + PAD_CFG_NC(GPP_C4), + // NC + PAD_CFG_NC(GPP_C5), + // LAN_WAKEUP# + PAD_CFG_NC(GPP_C6), + // NC + PAD_CFG_NC(GPP_C7), + + // UART0 + // NC + PAD_CFG_NC(GPP_C8), + // NC + PAD_CFG_NC(GPP_C9), + // TBT_FRC_PWR + PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST), + // NC + PAD_CFG_NC(GPP_C11), + + // UART1 + // GPP_C12_RTD3 + PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST), + // SSD_PWR_DN# + PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST), + // TBTA_HRESET + PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST), + // NC + PAD_CFG_NC(GPP_C15), + + // I2C + // T_SDA + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + // T_SCL + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + // NC + PAD_CFG_NC(GPP_C18), + // SWI + PAD_CFG_NC(GPP_C19), + + // UART2 + // UART2_RXD + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + // UART2_TXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + // NC + PAD_CFG_NC(GPP_C22), + // NC + PAD_CFG_NC(GPP_C23), + +// GPP_D + // SPI1 + // NC + PAD_CFG_NC(GPP_D0), + // NC + PAD_CFG_NC(GPP_D1), + // NC + PAD_CFG_NC(GPP_D2), + // NC + PAD_CFG_NC(GPP_D3), + + // IMGCLKOUT + // NC + PAD_CFG_NC(GPP_D4), + + // I2C + // NC + PAD_CFG_NC(GPP_D5), + // NC + PAD_CFG_NC(GPP_D6), + // NC + PAD_CFG_NC(GPP_D7), + // SB_BLON + PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP), + + // GSPI2 + // SWI# + _PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000), + // NC + PAD_CFG_NC(GPP_D10), + // BOARD_ID + PAD_CFG_NC(GPP_D11), + // PCH_GPP_D12 + PAD_CFG_NC(GPP_D12), + + // UART0 + // GPP_D13_RTD3 + PAD_CFG_TERM_GPO(GPP_D13, 1, NONE, PLTRST), + // SSD2_PWR_DN# + PAD_CFG_TERM_GPO(GPP_D14, 1, NONE, PLTRST), + // NC + PAD_CFG_NC(GPP_D15), + // RTD3_3G_PW R_EN + PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK), + + // DMIC + // NC + PAD_CFG_NC(GPP_D17), + // NC + PAD_CFG_NC(GPP_D18), + // GPPC_DMIC_CLK + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + // GPPC_DMIC_DATA + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + + // SPI1 + // TPM_DET# + PAD_CFG_NC(GPP_D21), + // TPM_TCM_Detect + PAD_CFG_NC(GPP_D22), + + // I2S + // NC + PAD_CFG_NC(GPP_D23), + +// GPP_E + // SATA + // PCH_GPP_E0 with pull-up + PAD_CFG_NC(GPP_E0), + // SATAGP1 + PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), + // SATAGP2 + PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), + + // CPU Misc + // NC + PAD_CFG_NC(GPP_E3), + + // DEVSLP + // NC + PAD_CFG_NC(GPP_E4), + // DEVSLP1 + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + // DEVSLP2 + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), + + // CPU Misc + // NC + PAD_CFG_NC(GPP_E7), + + // SATA + // PCH_SATAHDD_LED# + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + // USB2 + // GP_BSSB_CLK + PAD_CFG_NC(GPP_E9), + // GPP_E10 + PAD_CFG_NC(GPP_E10), + // GPP_E11 + PAD_CFG_NC(GPP_E11), + // USB_OC#78 + PAD_CFG_NC(GPP_E12), + + // Display Signals + // MUX_HPD + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + // HDMI_HPD + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + // SMI# + _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), + // SCI# + _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000), + // EDP_HPD + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + // MDP_CTRLCLK + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + // MDP_CTRLDATA + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + // HDMI_CTRLCLK + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + // HDMI_CTRLDATA + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + // NC + PAD_CFG_NC(GPP_E22), + // NC + PAD_CFG_NC(GPP_E23), + +// GPP_F + // CNVI + // CNVI_GNSS_PA_BLANKING + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + + // GPIO + // NC + PAD_CFG_NC(GPP_F1), + // NC + PAD_CFG_NC(GPP_F2), + // NC + PAD_CFG_NC(GPP_F3), + + // CNVI + // CNVI_BRI_DT + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), + // CNVI_RGI_DT + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), + // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + // CNVI_MFUART2_TXD + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), + + // GPIO + // NC + PAD_CFG_NC(GPP_F10), + + // EMMC + // NC + PAD_CFG_NC(GPP_F11), + // NC + PAD_CFG_NC(GPP_F12), + // NC + PAD_CFG_NC(GPP_F13), + // NC + PAD_CFG_NC(GPP_F14), + // NC + PAD_CFG_NC(GPP_F15), + // NC + PAD_CFG_NC(GPP_F16), + // NC + PAD_CFG_NC(GPP_F17), + // NC + PAD_CFG_NC(GPP_F18), + // NC + PAD_CFG_NC(GPP_F19), + // NC + PAD_CFG_NC(GPP_F20), + // NC + PAD_CFG_NC(GPP_F21), + // NC + PAD_CFG_NC(GPP_F22), + + // A4WP + // A4WP_PRESENT + PAD_CFG_GPI(GPP_F23, DN_20K, DEEP), + +// GPP_G + // SD + // EDP_DET + PAD_CFG_NC(GPP_G0), + // NC + PAD_CFG_NC(GPP_G1), + // NC + PAD_CFG_NC(GPP_G2), + // ASM1543_I_SEL0 + PAD_CFG_NC(GPP_G3), + // ASM1543_I_SEL1 + PAD_CFG_NC(GPP_G4), + // BOARD_ID + PAD_CFG_NC(GPP_G5), + // NC + PAD_CFG_NC(GPP_G6), + // TBT_Detect + PAD_CFG_NC(GPP_G7), + +// GPP_H + // CNVI + // NC + PAD_CFG_NC(GPP_H0), + // CNVI_RST# + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), + // CNVI_CLKREQ + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), + // NC + PAD_CFG_NC(GPP_H3), + + // I2C + // SMD_7411 + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + // SMC_7411 + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + // NC + PAD_CFG_NC(GPP_H6), + // NC + PAD_CFG_NC(GPP_H7), + // NC + PAD_CFG_NC(GPP_H8), + // NC + PAD_CFG_NC(GPP_H9), + + // I2C + // NC + PAD_CFG_NC(GPP_H10), + // NC + PAD_CFG_NC(GPP_H11), + + // PCIE + // NC + PAD_CFG_NC(GPP_H12), + // NC + PAD_CFG_NC(GPP_H13), + // G_INT1 + PAD_CFG_NC(GPP_H14), + // NC + PAD_CFG_NC(GPP_H15), + + // Display Signals + // NC + PAD_CFG_NC(GPP_H16), + // NC + PAD_CFG_NC(GPP_H17), + + // CPU Power + // CPU_C10_GATE# + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + // TIMESYNC + // NC + PAD_CFG_NC(GPP_H19), + + // IMGCLKOUT + // NC + PAD_CFG_NC(GPP_H20), + + // GPIO + // GPPC_H21 + PAD_CFG_NC(GPP_H21), + // TBT_RTD3_PWR_EN_R + PAD_NC(GPP_H22, NONE), + // NC, WIGIG_PEWAKE + PAD_CFG_NC(GPP_H23), +}; + +#endif + +#endif diff --git a/src/mainboard/system76/lemp9/hda_verb.c b/src/mainboard/system76/lemp9/hda_verb.c new file mode 100644 index 0000000..4723a94 --- /dev/null +++ b/src/mainboard/system76/lemp9/hda_verb.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15581401, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581401), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41748245), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/system76/lemp9/ramstage.c b/src/mainboard/system76/lemp9/ramstage.c new file mode 100644 index 0000000..6572aad --- /dev/null +++ b/src/mainboard/system76/lemp9/ramstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) { + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/lemp9/romstage.c b/src/mainboard/system76/lemp9/romstage.c new file mode 100644 index 0000000..12cecca --- /dev/null +++ b/src/mainboard/system76/lemp9/romstage.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> + +//TODO: find correct values +static const struct cnl_mb_cfg memcfg = { + /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ + .spd[0] = { + .read_type = READ_SPD_CBFS, + .spd_spec = {.spd_index = 0}, + }, + .spd[1] = {.read_type = NOT_EXISTING}, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .spd[3] = {.read_type = NOT_EXISTING}, + + /* + * For each channel, there are 3 sets of DQ byte mappings, + * where each set has a package 0 and a package 1 value (package 0 + * represents the first 64-bit lpddr4 chip combination, and package 1 + * represents the second 64-bit lpddr4 chip combination). + * The first three sets are for CLK, CMD, and CTL. + * The fsp package actually expects 6 sets, but the last 3 sets are + * not used in CNL, so we only define the three sets that are used + * and let the meminit_lpddr4() routine take care of clearing the + * unused fields for the caller. + */ + .dq_map[DDR_CH0] = { + {0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0}, + //{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} + }, + .dq_map[DDR_CH1] = { + {0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC}, + //{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} + }, + + /* + * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + */ + .dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7}, + .dqs_map[DDR_CH1] = {1, 0, 2, 3, 4, 5, 6, 7}, + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + .rcomp_resistor = { 121, 81, 100 }, + + /* + * Rcomp target values. These will typically be the following + * values for Cannon Lake : { 80, 40, 40, 40, 30 } + */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + .dq_pins_interleaved = 1, + + /* + * VREF_CA configuraation. + * Set to 0 VREF_CA goes to both CH_A and CH_B, + * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, + * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + */ + .vref_ca_config = 2, + + /* Early Command Training Enabled */ + .ect = 0, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) { + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} diff --git a/src/mainboard/system76/lemp9/spd/Makefile.inc b/src/mainboard/system76/lemp9/spd/Makefile.inc new file mode 100644 index 0000000..c5797ef --- /dev/null +++ b/src/mainboard/system76/lemp9/spd/Makefile.inc @@ -0,0 +1,37 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 System76 +## Copyright (C) 2018 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = samsung-K4AAG165WA-BCTD + +SPD_BIN = $(obj)/spd.bin + +ifeq ($(SPD_SOURCES),) + SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) +else + SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) +endif + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/system76/lemp9/spd/samsung-K4AAG165WA-BCTD.spd.hex b/src/mainboard/system76/lemp9/spd/samsung-K4AAG165WA-BCTD.spd.hex new file mode 100644 index 0000000..f747f7c --- /dev/null +++ b/src/mainboard/system76/lemp9/spd/samsung-K4AAG165WA-BCTD.spd.hex @@ -0,0 +1,33 @@ +# Samsung K4AAG165WA-BCTD +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 F7 4B +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36 +35 57 41 2D 42 43 54 44 20 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/system76/lemp9/variants/lemp9/data.vbt b/src/mainboard/system76/lemp9/variants/lemp9/data.vbt new file mode 100644 index 0000000..f14d807 --- /dev/null +++ b/src/mainboard/system76/lemp9/variants/lemp9/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/38463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0a32bbc6f89a662085ab4a254676bc1fad7dc60 Gerrit-Change-Number: 38463 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

8 37

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2020