coreboot-gerrit February 2020

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Change in coreboot[master]: [WIP] mb/asus: Add Asus P8H61-M LX3 R2.0
by Angel Pons (Code Review) 20 Apr '20

20 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39099 ) Change subject: [WIP] mb/asus: Add Asus P8H61-M LX3 R2.0 ...................................................................... [WIP] mb/asus: Add Asus P8H61-M LX3 R2.0 Actually, I have the PLUS variant, but they use the same PCB. The only difference is the capacitor quality. TODO: Test thoroughly, it currently boots and S3 resume works fine. Change-Id: I385ee72673202d896041209ff2911995307cb6af Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig A src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name A src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c A src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt A src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb A src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c A src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads A src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c A src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c 14 files changed, 640 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39099/1 diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig new file mode 100644 index 0000000..03f1e8d --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig @@ -0,0 +1,47 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASUS_P8H61_M_LX3_R2_0 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_NCT6779D + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default asus/p8h61-m_lx3_r2_0 + +config MAINBOARD_PART_NUMBER + string + default "P8H61-M LX3 R2.0" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 +endif diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name new file mode 100644 index 0000000..6d10dcf --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P8H61_M_LX3_R2_0 + bool "P8H61-M LX3 R2.0" diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc b/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc new file mode 100644 index 0000000..7167e10 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c + +romstage-y += early_init.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl new file mode 100644 index 0000000..d8d3320 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl new file mode 100644 index 0000000..ab41034 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c new file mode 100644 index 0000000..23537a4 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt b/src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt new file mode 100644 index 0000000..b889d3f --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/us/Motherboards/P8H61M_LX3_R20 +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb b/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb new file mode 100644 index 0000000..99b484c --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb @@ -0,0 +1,106 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2020 Angel Pons <th3fanbus(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0 on + subsystemid 0x1043 0x844d inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0291" + + register "pcie_port_coalesce" = "0" + + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1c.0 on end # RP #1 + device pci 1c.1 on end # RP #2 + device pci 1c.2 on end # RP #3 + device pci 1c.3 on end # RP #4 + device pci 1c.4 on end # RP #5 + device pci 1c.5 on end # RP #6: RTL8111 GbE NIC + + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-8 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 + device pnp 2e.108 on end # GPIO0 + device pnp 2e.9 off end # GPIO1-8 + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 on end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # H/W Monitor, FP LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO Push-pull/Open-drain + device pnp 2e.14 off end # PORT80 UART + device pnp 2e.16 off end # Deep Sleep + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl new file mode 100644 index 0000000..c92a550 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c new file mode 100644 index 0000000..6406d44 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + /* Enable UART */ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states. */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x00); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x71); + pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e); + pnp_write_config(GLOBAL_DEV, 0x22, 0xd7); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x48); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Power RAM in S3. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads b/src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads new file mode 100644 index 0000000..f12133b --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads @@ -0,0 +1,29 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2020 Angel Pons <th3fanbus(a)gmail.com> +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c new file mode 100644 index 0000000..f7f726a --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c @@ -0,0 +1,224 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio63 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio57 = GPIO_RESET_RSMRST, + .gpio63 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c new file mode 100644 index 0000000..6332289 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x11060397, /* Codec Vendor / Device ID: VIA VT1708S */ + 0x10438415, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(0, 0x10438415), + AZALIA_PIN_CFG(0, 0x19, 0x410110f0), + AZALIA_PIN_CFG(0, 0x1a, 0x01a19036), + AZALIA_PIN_CFG(0, 0x1b, 0x0181303e), + AZALIA_PIN_CFG(0, 0x1c, 0x01014010), + AZALIA_PIN_CFG(0, 0x1d, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1e, 0x02a19037), + AZALIA_PIN_CFG(0, 0x1f, 0x503701f0), + AZALIA_PIN_CFG(0, 0x20, 0x585600f0), + AZALIA_PIN_CFG(0, 0x21, 0x474411f0), + AZALIA_PIN_CFG(0, 0x22, 0x410160f0), + AZALIA_PIN_CFG(0, 0x23, 0x410120f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; -- To view, visit https://review.coreboot.org/c/coreboot/+/39099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I385ee72673202d896041209ff2911995307cb6af Gerrit-Change-Number: 39099 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 17

Change in ...coreboot[master]: src/mainboard/asus/am1i-a/buildOpts.c: set a board type to AMD_PLATFO...
by Mike Banon (Code Review) 20 Apr '20

20 Apr '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33919 Change subject: src/mainboard/asus/am1i-a/buildOpts.c: set a board type to AMD_PLATFORM_DESKTOP ...................................................................... src/mainboard/asus/am1i-a/buildOpts.c: set a board type to AMD_PLATFORM_DESKTOP Original AMD_PLATFORM_MOBILE is incorrect because this board is a desktop one. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I02adedffe8624c38e7b93fadd0449ddf094388fd --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/33919/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index cba0894..98bc620 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -115,7 +115,7 @@ #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE -- To view, visit https://review.coreboot.org/c/coreboot/+/33919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02adedffe8624c38e7b93fadd0449ddf094388fd Gerrit-Change-Number: 33919 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

7 13

Change in ...coreboot[master]: src/mainboard/asus/am1i-a/buildOpts.c: guard UMA-related options by C...
by Mike Banon (Code Review) 20 Apr '20

20 Apr '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33916 Change subject: src/mainboard/asus/am1i-a/buildOpts.c: guard UMA-related options by CONFIG_GFXUMA ...................................................................... src/mainboard/asus/am1i-a/buildOpts.c: guard UMA-related options by CONFIG_GFXUMA Seems this guard has been accidentally removed during the creation of this file. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ie73c4d6cb557820ae7427fef15ca8110722c5b68 --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/33916/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 2a1f13d..dfd27cd 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -176,9 +176,11 @@ #define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 #define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT +#if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO #define OPTION_GFX_INIT_SVIEW FALSE +#endif #define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed -- To view, visit https://review.coreboot.org/c/coreboot/+/33916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie73c4d6cb557820ae7427fef15ca8110722c5b68 Gerrit-Change-Number: 33916 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: src/mainboard/asus/am1i-a/buildOpts.c: return the removed comments
by Mike Banon (Code Review) 20 Apr '20

20 Apr '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33915 Change subject: src/mainboard/asus/am1i-a/buildOpts.c: return the removed comments ...................................................................... src/mainboard/asus/am1i-a/buildOpts.c: return the removed comments These comments exist in some other buildOpts.c files, but not in this one. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ic0aab06f1956bc0bf9f96d6176643c113a1e4cc5 --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/33915/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 8ba5975..2a1f13d 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -43,8 +43,10 @@ #include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h> #include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h> +/* Select the CPU family. */ #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -165,6 +167,8 @@ #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 +// Specify the default values for the VRM controlling the VDDNB plane. +// If not specified, the values used for the core VRM will be applied #define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 #define BLDCFG_VRM_SLEW_RATE 10000 @@ -344,4 +348,5 @@ #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) +/* AGESA nonsense: this header depends on the definitions above */ #include <PlatformInstall.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0aab06f1956bc0bf9f96d6176643c113a1e4cc5 Gerrit-Change-Number: 33915 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

5 13

Change in ...coreboot[master]: src/mainboard/asus/am1i-a/buildOpts.c: detailed paths to the include ...
by Mike Banon (Code Review) 20 Apr '20

20 Apr '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33914 Change subject: src/mainboard/asus/am1i-a/buildOpts.c: detailed paths to the include files ...................................................................... src/mainboard/asus/am1i-a/buildOpts.c: detailed paths to the include files Make it clear which include files are being used, by using the detailed paths. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ic096848f23910e2ad9183e44d882450ab8d4fdf1 --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/33914/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 93d7738..b5b06d3 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -26,7 +26,21 @@ */ #include <stdlib.h> -#include <AGESA.h> +#include <vendorcode/amd/agesa/f16kb/AGESA.h> + +/* Include the files that instantiate the configuration definitions. */ +#include <vendorcode/amd/agesa/f16kb/Include/AdvancedApi.h> +#include <vendorcode/amd/agesa/f16kb/Include/GnbInterface.h> +#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h> +#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h> +#include <vendorcode/amd/agesa/f16kb/Proc/CPU/Family/cpuFamRegisters.h> +#include <vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.h> +#include <vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h> +#include <vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.h> +/* AGESA nonesense: the next three headers depend on heapManager.h */ +#include <vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.h> +#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h> +#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h> #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE @@ -232,20 +246,6 @@ #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - -/* Include the files that instantiate the configuration definitions. */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} -- To view, visit https://review.coreboot.org/c/coreboot/+/33914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic096848f23910e2ad9183e44d882450ab8d4fdf1 Gerrit-Change-Number: 33914 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

5 14

Change in ...coreboot[master]: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison c...
by Mike Banon (Code Review) 20 Apr '20

20 Apr '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33913 Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ...................................................................... src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience Reorder lines to make it more similar to i.e. buildOpts.c of Lenovo G505S. This is needed to improve the convenience of comparison during the debugging. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I1674252fab2fc6fbf9be2b37e97a6f5ff97a04b3 --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 39 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/33913/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 30c0699..93d7738 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -28,7 +28,6 @@ #include <stdlib.h> #include <AGESA.h> -#define INSTALL_FT3_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE #define INSTALL_G34_SOCKET_SUPPORT FALSE @@ -43,6 +42,7 @@ #define INSTALL_AM3_SOCKET_SUPPORT FALSE #define INSTALL_FM2_SOCKET_SUPPORT FALSE +#define INSTALL_FT3_SOCKET_SUPPORT TRUE #ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE @@ -66,7 +66,7 @@ #define BLDOPT_REMOVE_SRAT FALSE //TRUE #define BLDOPT_REMOVE_SLIT FALSE //TRUE #define BLDOPT_REMOVE_WHEA FALSE //TRUE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE #define BLDOPT_REMOVE_DMI TRUE //#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE @@ -86,28 +86,14 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE - +#define BLDCFG_VRM_CURRENT_LIMIT 15000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 +#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT #define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 +#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE @@ -138,34 +124,52 @@ #define BLDCFG_SCRUB_L3_RATE 0 #define BLDCFG_SCRUB_IC_RATE 0 #define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD FALSE #define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE #define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE //#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the + // core for C-state entry requests. A value + // of 0 in this field specifies that the core + // does not trap any IO addresses for C-state entry. + // Values greater than 0xFFF8 results in undefined behavior. + +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL #define BLDCFG_CFG_ABM_SUPPORT TRUE -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - #ifdef PCIEX_BASE_ADDRESS #define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) #endif -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_SLEW_RATE 10000 +#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE +#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 +#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT + +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define OPTION_GFX_INIT_SVIEW FALSE + #define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed +#define BLDCFG_IOMMU_SUPPORT FALSE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID +//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1674252fab2fc6fbf9be2b37e97a6f5ff97a04b3 Gerrit-Change-Number: 33913 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

7 23

Change in coreboot[master]: [WIP] drivers/pc80/rtc: Reorganize prototypes
by Kyösti Mälkki (Code Review) 20 Apr '20

20 Apr '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38199 ) Change subject: [WIP] drivers/pc80/rtc: Reorganize prototypes ...................................................................... [WIP] drivers/pc80/rtc: Reorganize prototypes Change-Id: Idea18f437c31ebe83dd61a185e614106a1f8f976 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- A src/arch/x86/include/arch/post.h M src/include/console/console.h M src/include/pc80/mc146818rtc.h M src/lib/bootblock.c 4 files changed, 41 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38199/1 diff --git a/src/arch/x86/include/arch/post.h b/src/arch/x86/include/arch/post.h new file mode 100644 index 0000000..7bdf6a6 --- /dev/null +++ b/src/arch/x86/include/arch/post.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_POST_H__ +#define __ARCH_POST_H__ + +#include <stdint.h> + +void cmos_post_init(void); +void cmos_post_code(u8 value); +void cmos_post_extra(u32 value); +void cmos_post_path(const struct device *dev); +int cmos_post_previous(u8 *code, u32 *extra); + +static inline void post_log_path(const struct device *dev) +{ + if (CONFIG(CMOS_POST) && dev) + cmos_post_path(dev); +} + +static inline void post_log_clear(void) +{ + if (CONFIG(CMOS_POST)) + cmos_post_extra(0); +} + +#endif diff --git a/src/include/console/console.h b/src/include/console/console.h index 94642cd..12fb77a 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -19,6 +19,7 @@ #include <stdint.h> #include <arch/cpu.h> #include <console/post_codes.h> +#include <console/vtxprintf.h> /* console.h is supposed to provide the log levels defined in here: */ #include <commonlib/loglevel.h> @@ -26,31 +27,10 @@ #define RAM_DEBUG (CONFIG(DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER) #define RAM_SPEW (CONFIG(DEBUG_RAM_SETUP) ? BIOS_SPEW : BIOS_NEVER) -#include <console/vtxprintf.h> - -struct device; - void post_code(u8 value); -void arch_post_code(u8 value); -void cmos_post_code(u8 value); -void cmos_post_extra(u32 value); -void cmos_post_path(const struct device *dev); -int cmos_post_previous(u8 *code, u32 *extra); - -static inline void post_log_path(const struct device *dev) -{ - if (CONFIG(CMOS_POST) && dev) - cmos_post_path(dev); -} - -static inline void post_log_clear(void) -{ - if (CONFIG(CMOS_POST)) - cmos_post_extra(0); -} - -/* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); +void arch_post_code(u8 value); + void __noreturn die(const char *fmt, ...); #define die_with_post_code(value, fmt, ...) \ do { post_code(value); die(fmt, ##__VA_ARGS__); } while (0) diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 353a09b..c9e054b 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -183,6 +183,5 @@ #endif /* CONFIG_ARCH_X86 */ -void cmos_post_init(void); #endif /* PC80_MC146818RTC_H */ diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 386f4e3..5995c45 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -15,11 +15,11 @@ */ #include <arch/exception.h> +#include <arch/post.h> #include <bootblock_common.h> #include <console/console.h> #include <delay.h> #include <option.h> -#include <pc80/mc146818rtc.h> #include <program_loading.h> #include <symbols.h> #include <timestamp.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/38199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idea18f437c31ebe83dd61a185e614106a1f8f976 Gerrit-Change-Number: 38199 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: drivers/pc80/rtc: Move CMOS_POST_BANK_x definitions
by Kyösti Mälkki (Code Review) 20 Apr '20

20 Apr '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38196 ) Change subject: drivers/pc80/rtc: Move CMOS_POST_BANK_x definitions ...................................................................... drivers/pc80/rtc: Move CMOS_POST_BANK_x definitions Change-Id: I8b56df6de7529772b0f1a59002f92c4f31486bf0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/rtc/post.c M src/include/pc80/mc146818rtc.h 2 files changed, 27 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/38196/1 diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c index 38ef241..8a8a762 100644 --- a/src/drivers/pc80/rtc/post.c +++ b/src/drivers/pc80/rtc/post.c @@ -18,6 +18,33 @@ #include <pc80/mc146818rtc.h> #include <smp/spinlock.h> +#if CONFIG(USE_OPTION_TABLE) +# include "option_table.h" +# define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3) +#else +# if (CONFIG_CMOS_POST_OFFSET != 0) +# define CMOS_POST_OFFSET CONFIG_CMOS_POST_OFFSET +# else +# error "Must configure CONFIG_CMOS_POST_OFFSET" +# endif + +/* + * 0 = Bank Select Magic + * 1 = Bank 0 POST + * 2 = Bank 1 POST + * 3-6 = BANK 0 Extra log + * 7-10 = BANK 1 Extra log + */ +#define CMOS_POST_BANK_OFFSET (CMOS_POST_OFFSET) +#define CMOS_POST_BANK_0_MAGIC 0x80 +#define CMOS_POST_BANK_0_OFFSET (CMOS_POST_OFFSET + 1) +#define CMOS_POST_BANK_0_EXTRA (CMOS_POST_OFFSET + 3) +#define CMOS_POST_BANK_1_MAGIC 0x81 +#define CMOS_POST_BANK_1_OFFSET (CMOS_POST_OFFSET + 2) +#define CMOS_POST_BANK_1_EXTRA (CMOS_POST_OFFSET + 7) + +#define CMOS_POST_EXTRA_DEV_PATH 0x01 + DECLARE_SPIN_LOCK(cmos_post_lock) int cmos_post_previous(u8 *code, u32 *extra) diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 92d8f2f..8cc2ed4 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -181,37 +181,6 @@ int cmos_checksum_valid(int range_start, int range_end, int cks_loc); void cmos_set_checksum(int range_start, int range_end, int cks_loc); -#if CONFIG(CMOS_POST) -#if CONFIG(USE_OPTION_TABLE) -# include "option_table.h" -# define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3) -#else -# if (CONFIG_CMOS_POST_OFFSET != 0) -# define CMOS_POST_OFFSET CONFIG_CMOS_POST_OFFSET -# else -# error "Must configure CONFIG_CMOS_POST_OFFSET" -# endif -#endif - -/* - * 0 = Bank Select Magic - * 1 = Bank 0 POST - * 2 = Bank 1 POST - * 3-6 = BANK 0 Extra log - * 7-10 = BANK 1 Extra log - */ -#define CMOS_POST_BANK_OFFSET (CMOS_POST_OFFSET) -#define CMOS_POST_BANK_0_MAGIC 0x80 -#define CMOS_POST_BANK_0_OFFSET (CMOS_POST_OFFSET + 1) -#define CMOS_POST_BANK_0_EXTRA (CMOS_POST_OFFSET + 3) -#define CMOS_POST_BANK_1_MAGIC 0x81 -#define CMOS_POST_BANK_1_OFFSET (CMOS_POST_OFFSET + 2) -#define CMOS_POST_BANK_1_EXTRA (CMOS_POST_OFFSET + 7) - -#define CMOS_POST_EXTRA_DEV_PATH 0x01 - -#endif /* CONFIG_CMOS_POST */ - #endif /* CONFIG_ARCH_X86 */ void cmos_post_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/38196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b56df6de7529772b0f1a59002f92c4f31486bf0 Gerrit-Change-Number: 38196 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/pc80/rtc: Drop CMOS_POST_EXTRA option
by Kyösti Mälkki (Code Review) 20 Apr '20

20 Apr '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38191 ) Change subject: drivers/pc80/rtc: Drop CMOS_POST_EXTRA option ...................................................................... drivers/pc80/rtc: Drop CMOS_POST_EXTRA option Change-Id: I379a5664776624600ff1c2919bffa77c877d87ab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M configs/config.google_meep_cros M configs/config.google_reef_cros M src/console/Kconfig M src/drivers/elog/elog.c M src/drivers/pc80/rtc/post.c 5 files changed, 4 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/38191/1 diff --git a/configs/config.google_meep_cros b/configs/config.google_meep_cros index f87b02b..9911614 100644 --- a/configs/config.google_meep_cros +++ b/configs/config.google_meep_cros @@ -14,7 +14,6 @@ # Event Logging CONFIG_CMOS_POST=y -CONFIG_CMOS_POST_EXTRA=y CONFIG_CMOS_POST_OFFSET=0x70 CONFIG_COLLECT_TIMESTAMPS=y CONFIG_ELOG=y diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros index 9bbb3b3..6dcda44 100644 --- a/configs/config.google_reef_cros +++ b/configs/config.google_reef_cros @@ -10,5 +10,4 @@ # CONFIG_CONSOLE_SERIAL is not set CONFIG_CMOS_POST=y CONFIG_CMOS_POST_OFFSET=0x70 -CONFIG_CMOS_POST_EXTRA=y CONFIG_PAYLOAD_NONE=y diff --git a/src/console/Kconfig b/src/console/Kconfig index cc18ec3..a5a833a 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -392,14 +392,6 @@ If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value defined in the mainboard option table. -config CMOS_POST_EXTRA - bool "Store extra logging info into CMOS" - depends on CMOS_POST - default n - help - This will enable extra logging of work that happens between post - codes into CMOS for debug. This uses an additional 8 bytes of CMOS. - config CONSOLE_POST bool "Show POST codes on the debug console" depends on !NO_POST diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 9bd2a61..11cbfba 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -776,7 +776,6 @@ if (ENV_RAMSTAGE || CONFIG(ELOG_PRERAM)) { elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); - /* Always zero with !CMOS_POST_EXTRA. */ if (extra) elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); } diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c index 8308504..38ef241 100644 --- a/src/drivers/pc80/rtc/post.c +++ b/src/drivers/pc80/rtc/post.c @@ -28,13 +28,11 @@ switch (cmos_read(CMOS_POST_BANK_OFFSET)) { case CMOS_POST_BANK_0_MAGIC: *code = cmos_read(CMOS_POST_BANK_1_OFFSET); - if (CONFIG(CMOS_POST_EXTRA)) - *extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); + *extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); break; case CMOS_POST_BANK_1_MAGIC: *code = cmos_read(CMOS_POST_BANK_0_OFFSET); - if (CONFIG(CMOS_POST_EXTRA)) - *extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); + *extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); break; } @@ -69,10 +67,8 @@ /* Initialize to zero */ cmos_write(0, CMOS_POST_BANK_0_OFFSET); cmos_write(0, CMOS_POST_BANK_1_OFFSET); - if (CONFIG(CMOS_POST_EXTRA)) { - cmos_write32(0, CMOS_POST_BANK_0_EXTRA); - cmos_write32(0, CMOS_POST_BANK_1_EXTRA); - } + cmos_write32(0, CMOS_POST_BANK_0_EXTRA); + cmos_write32(0, CMOS_POST_BANK_1_EXTRA); } cmos_write(magic, CMOS_POST_BANK_OFFSET); @@ -96,9 +92,6 @@ void cmos_post_extra(u32 value) { - if (!CONFIG(CMOS_POST_EXTRA)) - return; - spin_lock(&cmos_post_lock); switch (cmos_read(CMOS_POST_BANK_OFFSET)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/38191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I379a5664776624600ff1c2919bffa77c877d87ab Gerrit-Change-Number: 38191 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: drivers/pc80/rtc: Clean up post_log_path()
by Kyösti Mälkki (Code Review) 20 Apr '20

20 Apr '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38190 ) Change subject: drivers/pc80/rtc: Clean up post_log_path() ...................................................................... drivers/pc80/rtc: Clean up post_log_path() Change-Id: I605d39d907e083e73af4c72607216384e7ce166a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/rtc/post.c M src/include/console/console.h 2 files changed, 27 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/38190/1 diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c index 2893a41..8308504 100644 --- a/src/drivers/pc80/rtc/post.c +++ b/src/drivers/pc80/rtc/post.c @@ -94,8 +94,11 @@ spin_unlock(&cmos_post_lock); } -static void __unused cmos_post_extra(u32 value) +void cmos_post_extra(u32 value) { + if (!CONFIG(CMOS_POST_EXTRA)) + return; + spin_lock(&cmos_post_lock); switch (cmos_read(CMOS_POST_BANK_OFFSET)) { @@ -110,20 +113,11 @@ spin_unlock(&cmos_post_lock); } -#if CONFIG(CMOS_POST_EXTRA) -void post_log_path(const struct device *dev) +void cmos_post_path(const struct device *dev) { - if (dev) { - /* Encode path into lower 3 bytes */ - u32 path = dev_path_encode(dev); - /* Upper byte contains the log type */ - path |= CMOS_POST_EXTRA_DEV_PATH << 24; - cmos_post_extra(path); - } + /* Encode path into lower 3 bytes */ + u32 path = dev_path_encode(dev); + /* Upper byte contains the log type */ + path |= CMOS_POST_EXTRA_DEV_PATH << 24; + cmos_post_extra(path); } - -void post_log_clear(void) -{ - cmos_post_extra(0); -} -#endif /* CONFIG_CMOS_POST_EXTRA */ diff --git a/src/include/console/console.h b/src/include/console/console.h index 9e6c76e..94642cd 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -28,18 +28,27 @@ #include <console/vtxprintf.h> +struct device; + void post_code(u8 value); void arch_post_code(u8 value); void cmos_post_code(u8 value); +void cmos_post_extra(u32 value); +void cmos_post_path(const struct device *dev); int cmos_post_previous(u8 *code, u32 *extra); -#if CONFIG(CMOS_POST_EXTRA) -struct device; -void post_log_path(const struct device *dev); -void post_log_clear(void); -#else -#define post_log_path(x) do {} while (0) -#define post_log_clear() do {} while (0) -#endif + +static inline void post_log_path(const struct device *dev) +{ + if (CONFIG(CMOS_POST) && dev) + cmos_post_path(dev); +} + +static inline void post_log_clear(void) +{ + if (CONFIG(CMOS_POST)) + cmos_post_extra(0); +} + /* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); void __noreturn die(const char *fmt, ...); -- To view, visit https://review.coreboot.org/c/coreboot/+/38190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I605d39d907e083e73af4c72607216384e7ce166a Gerrit-Change-Number: 38190 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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