coreboot-gerrit February 2020

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Change in ...coreboot[master]: src/mainboard/asus/am1i-a/buildOpts.c: improve the RAM frequency rela...
by Mike Banon (Code Review) 17 Apr '20

17 Apr '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33920 Change subject: src/mainboard/asus/am1i-a/buildOpts.c: improve the RAM frequency related defines ...................................................................... src/mainboard/asus/am1i-a/buildOpts.c: improve the RAM frequency related defines This improvement is likely required for forcing a pair of 1866MHz CL9 RAM sticks to work faster than a mediocre 1333MHz CL9, but sadly alone it's not enough... Still it doesn't bring any downsides to a system operation, just no upsides yet. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ib2bc605b98ad99066549017697bb483ad3be3910 --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/33920/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 98bc620..48c5c56 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -117,22 +117,22 @@ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE #define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE #define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE #define BLDCFG_MEMORY_POWER_DOWN TRUE #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT #define BLDCFG_ONLINE_SPARE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY #define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE #define BLDCFG_USE_BURST_MODE FALSE -- To view, visit https://review.coreboot.org/c/coreboot/+/33920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2bc605b98ad99066549017697bb483ad3be3910 Gerrit-Change-Number: 33920 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/asus/am1i-a/buildOpts.c: add includes for adjusting RAM...
by Mike Banon (Code Review) 17 Apr '20

17 Apr '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33917 Change subject: src/mainboard/asus/am1i-a/buildOpts.c: add includes for adjusting RAM timings ...................................................................... src/mainboard/asus/am1i-a/buildOpts.c: add includes for adjusting RAM timings These tables may be used to adjust memory timing settings. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I782f76119c5ce9a3cc4bc07596d27dd42b615b6d --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/33917/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index dfd27cd..643b306 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -42,6 +42,9 @@ #include <vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.h> #include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h> #include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h> +/* These tables are optional and may be used to adjust memory timing settings */ +#include <vendorcode/amd/agesa/f16kb/Proc/Mem/mm.h> +#include <vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h> /* Select the CPU family. */ #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE -- To view, visit https://review.coreboot.org/c/coreboot/+/33917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I782f76119c5ce9a3cc4bc07596d27dd42b615b6d Gerrit-Change-Number: 33917 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: vendorcode/amd/agesa/f16kb: fix the IDS_HDT_CONSOLE compilation warni...
by Mike Banon (Code Review) 17 Apr '20

17 Apr '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36880 ) Change subject: vendorcode/amd/agesa/f16kb: fix the IDS_HDT_CONSOLE compilation warnings/errors ...................................................................... vendorcode/amd/agesa/f16kb: fix the IDS_HDT_CONSOLE compilation warnings/errors Fix the format-related warnings/errors which happen with IDS_HDT_CONSOLE enabled (IDSOPT_IDS_ENABLED TRUE and IDSOPT_TRACING_ENABLED TRUE at board/OptionsIds.h). Joined errors log before a fix is available at https://pastebin.com/RZQBvTEc and https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/XRD… Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I4c4f8f575b2f72451e7c60ba708d1f389d102e44 --- M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c M src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c M src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c M src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c M src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c M src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c M src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c M src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c 19 files changed, 38 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36880/1 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c index 714f970..ef18c82 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c @@ -155,7 +155,7 @@ UnusedMmioPair++; } IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair); - IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF, + IDS_HDT_CONSOLE (MAIN_FLOW, "%08llx%08llx %08llx%08llx", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF, MmioRange[MmioPair].Base & 0xFFFFFFFF, (MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF, MmioRange[MmioPair].Limit & 0xFFFFFFFF); @@ -172,7 +172,7 @@ NewMmioRange.Base = AmdAddMmioParams.BaseAddress; NewMmioRange.Limit = AmdAddMmioParams.BaseAddress + AmdAddMmioParams.Length; NewMmioRange.Attribute = AmdAddMmioParams.Attributes; - IDS_HDT_CONSOLE (MAIN_FLOW, "req %08x%08x %08x%08x\n", (NewMmioRange.Base >> 32) & 0xFFFFFFFF, + IDS_HDT_CONSOLE (MAIN_FLOW, "req %08llx%08llx %08llx%08llx\n", (NewMmioRange.Base >> 32) & 0xFFFFFFFF, NewMmioRange.Base & 0xFFFFFFFF, (NewMmioRange.Limit >> 32) & 0xFFFFFFFF, NewMmioRange.Limit & 0xFFFFFFFF); @@ -414,7 +414,7 @@ PciAddress.Address.Function = FUNC_1; for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) { IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair); - IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF, + IDS_HDT_CONSOLE (MAIN_FLOW, "%08llx%08llx %08llx%08llx", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF, MmioRange[MmioPair].Base & 0xFFFFFFFF, (MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF, MmioRange[MmioPair].Limit & 0xFFFFFFFF); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c index b3db886..3757ab9 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c @@ -148,7 +148,7 @@ } } } else { - IDS_HDT_CONSOLE (CPU_TRACE, " Force Ucode loaded from offset %x\n", ForceLoadMicrocodePatchPtr); + IDS_HDT_CONSOLE (CPU_TRACE, " Force Ucode loaded from offset %x\n", (UINT32)ForceLoadMicrocodePatchPtr); if (LoadMicrocode (ForceLoadMicrocodePatchPtr, StdHeader)) { Status = TRUE; } else { diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c index 30e194e..c09ff55 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c @@ -154,7 +154,7 @@ IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: Start\n\n"); - IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", &UserOptions.VersionString); + IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", (CHAR8 *)&UserOptions.VersionString); AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader); ASSERT (ResetParams != NULL); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c index 9da575c..7ee6dc5 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c @@ -165,7 +165,7 @@ PCI_ADDR PciAddress; UINTN Index; S3SaveTableRecordPtr = (UINT8 *) S3SaveTablePtr + sizeof (S3_SAVE_TABLE_HEADER); - IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore\n", ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); + IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore - Address: 0x%08x\n", (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); while ((UINT8 *) S3SaveTableRecordPtr < ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset)) { switch (*(UINT16 *) S3SaveTableRecordPtr) { case SAVE_STATE_IO_WRITE_OPCODE: diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c index c81c877..68976ee 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c @@ -268,7 +268,7 @@ } } S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08llx Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); S3SaveDebugPrintHexArray (StdHeader, Buffer, Count, Width); IDS_HDT_CONSOLE (S3_TRACE, "\n"); ); @@ -333,7 +333,7 @@ } } S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08llx Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); @@ -409,7 +409,7 @@ } } S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08llx Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); @@ -481,7 +481,7 @@ SaveOffsetPtr->OpCode = OpCode; SaveOffsetPtr->Length = InformationLength; S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", Information); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", (CHAR8 *)Information); ); LibAmdMemCopy ( (UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER), diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c index 4bea9fb..60cb936 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c @@ -138,7 +138,7 @@ FchParams = (FCH_DATA_BLOCK *) AllocHeapParams.BufferPtr; ASSERT (FchParams != NULL); - IDS_HDT_CONSOLE (FCH_TRACE, " FCH Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams); + IDS_HDT_CONSOLE (FCH_TRACE, " FCH Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, (UINT32)FchParams); // Load private data block with default *FchParams = InitEnvCfgDefault; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c index 9cbffd7..606c3fc 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c @@ -71,7 +71,7 @@ FchParams = (FCH_RESET_DATA_BLOCK *) AllocHeapParams.BufferPtr; ASSERT (FchParams != NULL); - IDS_HDT_CONSOLE (FCH_TRACE, " FCH Reset Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams); + IDS_HDT_CONSOLE (FCH_TRACE, " FCH Reset Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, (UINT32)FchParams); *FchParams = InitResetCfgDefault; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c index 34990c5..02d65ed 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c @@ -482,7 +482,7 @@ Index += 4; break; case 4: - IDS_HDT_CONSOLE (GNB_TRACE, "%08x%08", *(UINT32 *) ((UINT8 *) Buffer + Index), *(UINT32 *) ((UINT8 *) Buffer + Index + 4)); + IDS_HDT_CONSOLE (GNB_TRACE, "%08x%08x", *(UINT32 *) ((UINT8 *) Buffer + Index), *(UINT32 *) ((UINT8 *) Buffer + Index + 4)); Index += 8; break; default: diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c index ae0128a..1e8b679 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c @@ -255,7 +255,7 @@ ); IDS_HDT_CONSOLE (GFX_MISC, " UmaMode - %s\n", (Gfx->UmaInfo.UmaMode == UMA_NONE) ? "No UMA" : "UMA"); if (Gfx->UmaInfo.UmaMode != UMA_NONE) { - IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%x\n", Gfx->UmaInfo.UmaBase); + IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%llx\n", Gfx->UmaInfo.UmaBase); IDS_HDT_CONSOLE (GFX_MISC, " UmaSize - 0x%x\n", Gfx->UmaInfo.UmaSize); IDS_HDT_CONSOLE (GFX_MISC, " UmaAttributes - 0x%x\n", Gfx->UmaInfo.UmaAttributes); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c index 7b5f3ef..532b164 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c @@ -495,7 +495,7 @@ PpTable = (ATOM_PPLIB_POWERPLAYTABLE4*) &SystemInfoTableV3Ptr->ulPowerplayTable; ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) ((UINT8 *) (PpTable) + PpTable->usExtendendedHeaderOffset); IDS_HDT_CONSOLE (GFX_MISC, " ExtendedHeader usSize %d\n", ExtendedHeader->usSize); - IDS_HDT_CONSOLE (GFX_MISC, " SizeOf %d\n", sizeof(ATOM_PPLIB_EXTENDEDHEADER)); + IDS_HDT_CONSOLE (GFX_MISC, " SizeOf %ld\n", sizeof(ATOM_PPLIB_EXTENDEDHEADER)); IDS_HDT_CONSOLE (GFX_MISC, " ucHtcTmpLmt 0x%X\n", SystemInfoTableV3Ptr->sIntegratedSysInfo.ucHtcTmpLmt); IDS_HDT_CONSOLE (GFX_MISC, " ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11 0x%X\n", SystemInfoTableV3Ptr->sIntegratedSysInfo.ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c index 4e83c44..656f737 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c @@ -1158,7 +1158,7 @@ ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset); IDS_HDT_CONSOLE (GFX_MISC, " < --- SW State Table ---------> \n"); for (Index = 0; Index < StateArray->ucNumEntries; Index++) { - IDS_HDT_CONSOLE (GFX_MISC, " State #%d\n", Index + 1 + IDS_HDT_CONSOLE (GFX_MISC, " State #%ld\n", Index + 1 ); IDS_HDT_CONSOLE (GFX_MISC, " Classification 0x%x\n", NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification @@ -1173,7 +1173,7 @@ ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) ((UINT8 *) PpTable + PpTable->usExtendendedHeaderOffset); - IDS_HDT_CONSOLE (GNB_TRACE, "ExtendedHeader = %08x\n", ExtendedHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "ExtendedHeader = %08x\n", (UINT32)ExtendedHeader); VceClockInfoArray = (VCECLOCKINFOARRAY *) ((UINT8 *) PpTable + ExtendedHeader->usVCETableOffset + sizeof (ATOM_PPLIB_VCE_TABLE)); @@ -1203,7 +1203,7 @@ IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE Voltage Record Table ---> \n"); for (Index = 0; Index < VceClockVoltageLimitTable->numEntries; Index++) { EclkIndex = VceClockVoltageLimitTable->entries[Index].ucVCEClockInfoIndex; - IDS_HDT_CONSOLE (GFX_MISC, " VCE Voltage Record #%d\n", Index + IDS_HDT_CONSOLE (GFX_MISC, " VCE Voltage Record #%ld\n", Index ); IDS_HDT_CONSOLE (GFX_MISC, " ECLK = %d\n", VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16) @@ -1216,7 +1216,7 @@ IDS_HDT_CONSOLE (GFX_MISC, " < --- SAMU Voltage Record Table ---> \n"); for (Index = 0; Index < SamuClockVoltLimitTable->numEntries; Index++) { - IDS_HDT_CONSOLE (GFX_MISC, " SAMU Voltage Record #%d\n", Index + IDS_HDT_CONSOLE (GFX_MISC, " SAMU Voltage Record #%ld\n", Index ); IDS_HDT_CONSOLE (GFX_MISC, " SAMCLK = %d\n", SamuClockVoltLimitTable->entries[Index].usSAMClockLow | diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c index b26679b..d8b351c 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c @@ -371,7 +371,7 @@ BaseAddress |= Value; if ((BaseAddress & 0xfffffffffffffffe) != 0x0) { - IDS_HDT_CONSOLE (GNB_TRACE, " Enable IOMMU MMIO at address %x for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle)); + IDS_HDT_CONSOLE (GNB_TRACE, " Enable IOMMU MMIO at address %llx for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle)); GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessS3SaveWidth32, 0xFFFFFFFF, 0x0, StdHeader); GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessS3SaveWidth32, 0xFFFFFFFE, 0x1, StdHeader); } else { diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c index 27e7bce..c7993fd 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c @@ -557,7 +557,11 @@ EngineList->Type.Port.Address.Address.Device, EngineList->Type.Port.Address.Address.Function ); - IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control - 0x%02x\n", EngineList->Type.Port.PortData.MiscControls); + IDS_HDT_CONSOLE (PCIE_MISC, " MiscControls[LinkComplianceMode/LinkSafeMode/SbLink/ClkPmSupport] - 0x%02x/0x%02x/0x%02x/0x%02x\n\n", + EngineList->Type.Port.PortData.MiscControls.LinkComplianceMode, + EngineList->Type.Port.PortData.MiscControls.LinkSafeMode, + EngineList->Type.Port.PortData.MiscControls.SbLink, + EngineList->Type.Port.PortData.MiscControls.ClkPmSupport); IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Dev Number - %d\n", EngineList->Type.Port.NativeDevNumber); IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Func Number - %d\n", EngineList->Type.Port.NativeFunNumber); IDS_HDT_CONSOLE (PCIE_MISC, " Hotplug - %s\n", @@ -736,7 +740,7 @@ EngineDescriptor->EngineData.EndLane ); if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n SB link - %d\n MiscControls - 0x%02x\n" , + IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n MiscControls[LinkComplianceMode/LinkSafeMode/SbLink/ClkPmSupport] - 0x%02x/0x%02x/0x%02x/0x%02x\n" , ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.PortPresent, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ChannelType, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.DeviceNumber, @@ -745,8 +749,10 @@ ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkAspm, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkHotplug, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ResetId, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.LinkComplianceMode, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.LinkSafeMode, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.SbLink, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.ClkPmSupport ); } if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { @@ -784,7 +790,7 @@ for (ComplexIndex = 0; ComplexIndex < NumberOfComplexes; ++ComplexIndex) { CurrentComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexDescriptor, ComplexIndex); NumberOfEngines = PcieInputParserGetNumberOfEngines (CurrentComplexDescriptor); - IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %d\n", + IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %ld\n", ComplexDescriptor->SocketId, NumberOfEngines ); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c index 9113029..2c3f232 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c @@ -104,19 +104,19 @@ //Verify the SCS block signature ASSERT (*(UINT32 *)ScsDataPtr == GnbSmuInitLibV7136_macro0); if (*(UINT32 *)ScsDataPtr != GnbSmuInitLibV7136_macro0) { - IDS_HDT_CONSOLE (GNB_TRACE, "Verify SCS Binary fail\n", ScsDataPtr); + IDS_HDT_CONSOLE (GNB_TRACE, "Verify SCS Binary fail - ScsDataPtr: 0x%08x\n", (UINT32)ScsDataPtr); return AGESA_ERROR; } //Load SCS block - IDS_HDT_CONSOLE (GNB_TRACE, "Load SCS @%08x\n", ScsDataPtr); + IDS_HDT_CONSOLE (GNB_TRACE, "Load SCS @%08x\n", (UINT32)ScsDataPtr); DevObject.DevPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); DevObject.GnbHandle = GnbHandle; DevObject.StdHeader = StdHeader; GnbSmuServiceRequestV7 (&DevObject, 0x50, (UINT32) (UINTN) ScsDataPtr, 0); //Get SCS result and save to Heap - IDS_HDT_CONSOLE (GNB_TRACE, "Get SCS Result\n", ScsDataPtr); + IDS_HDT_CONSOLE (GNB_TRACE, "Get SCS Result - ScsDataPtr: 0x%08x\n", (UINT32)ScsDataPtr); Status = GnbSmuInitLibV7139_fun1 (GnbHandle, StdHeader); IDS_HDT_CONSOLE (GNB_TRACE, "Get SCS Result %s\n", (Status == AGESA_SUCCESS) ? "Success" : "Fail"); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c index d75bf3e..17ef27e 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c @@ -129,7 +129,7 @@ file = (FileCode >> 16); line = (FileCode & 0xFFFF); - IDS_HDT_CONSOLE (MAIN_FLOW, "ASSERT on File[%x] Line[%x]\n", (UINTN) file, (UINTN) line); + IDS_HDT_CONSOLE (MAIN_FLOW, "ASSERT on File[%lx] Line[%lx]\n", (UINTN) file, (UINTN) line); IDS_HDT_CONSOLE_FLUSH_BUFFER (NULL); IDS_HDT_CONSOLE_ASSERT (FileCode); // IdsErrorStop (FileCode); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c index b355d6b..ef40521 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c @@ -221,7 +221,7 @@ // Va.AdjustValue = Vref = (Vref - 15) << 1; Status = AgesaExternalVoltageAdjust ((UINTN)CallOutIdInfo.IdInformation, &Va); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDimm Vref = %c%d% ", (Va.AdjustValue < 0) ? '-':'+', (Va.AdjustValue < 0) ? (0 - Va.AdjustValue) : Va.AdjustValue ); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDimm Vref = %c%d ", (Va.AdjustValue < 0) ? '-':'+', (Va.AdjustValue < 0) ? (0 - Va.AdjustValue) : Va.AdjustValue ); if (Status != AGESA_SUCCESS) { IDS_HDT_CONSOLE (MEM_FLOW, "* Dimm Vref Callout Failed *"); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c index 6a9e873..5aab7c4 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c @@ -1242,7 +1242,7 @@ IDS_HDT_CONSOLE_DEBUG_CODE ( IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSmallest Max Positive Vref Offset from V-Nom for ChipSel %02x = + %02x\n", NBPtr->TechPtr->ChipSel, Data->SmallestPosMaxVrefperCS[NBPtr->TechPtr->ChipSel]); if (Data->SmallestPosMaxVrefperCS[NBPtr->TechPtr->ChipSel] == 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSmallest Max Negative Vref Offset from V-Nom for ChipSel %02x = 00\n"); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSmallest Max Negative Vref Offset from V-Nom for ChipSel %02x = 00\n", NBPtr->TechPtr->ChipSel); } else { IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSmallest Max Negative Vref Offset from V-Nom for ChipSel %02x = - %02x\n", NBPtr->TechPtr->ChipSel, Data->SmallestNegMaxVrefperCS[NBPtr->TechPtr->ChipSel]); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c index d497aec..13e5d18 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c @@ -389,7 +389,7 @@ AGESA_TESTPOINT (TpProcMemAfterAgesaReadSpd, &MemPtr->StdHeader); if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, (UINT32)SpdParam.Buffer); } else { DimmSPDPtr->DimmPresent = FALSE; } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c index 9bb9440..5ee5311 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c @@ -1072,7 +1072,7 @@ IDS_HDT_CONSOLE_DEBUG_CODE ( IDS_HDT_CONSOLE (MEM_FLOW, "Smallest Max Positive Vref Offset from V-Nom for ChipSel %02x = + %02x\n", TechPtr->ChipSel, Data->SmallestPosMaxVrefperCS[TechPtr->ChipSel]); if (Data->SmallestPosMaxVrefperCS[TechPtr->ChipSel] == 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "Smallest Max Negative Vref Offset from V-Nom for ChipSel %02x = 00\n"); + IDS_HDT_CONSOLE (MEM_FLOW, "Smallest Max Negative Vref Offset from V-Nom for ChipSel %02x = 00\n", TechPtr->ChipSel); } else { IDS_HDT_CONSOLE (MEM_FLOW, "Smallest Max Negative Vref Offset from V-Nom for ChipSel %02x = - %02x\n", TechPtr->ChipSel, Data->SmallestNegMaxVrefperCS[TechPtr->ChipSel]); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4f8f575b2f72451e7c60ba708d1f389d102e44 Gerrit-Change-Number: 36880 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: soc/intel/broadwell: Comment conflicting use of _ADR and _HID
by HAOUAS Elyes (Code Review) 16 Apr '20

16 Apr '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38350 ) Change subject: soc/intel/broadwell: Comment conflicting use of _ADR and _HID ...................................................................... soc/intel/broadwell: Comment conflicting use of _ADR and _HID Change-Id: I3e892c451ee9d4e576b568f7efaad2e390524fe0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/broadwell/acpi/serialio.asl 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/38350/1 diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl index 1b44e95..d6a763b 100644 --- a/src/soc/intel/broadwell/acpi/serialio.asl +++ b/src/soc/intel/broadwell/acpi/serialio.asl @@ -157,6 +157,7 @@ Device (SDMA) { // Serial IO DMA Controller + // FIXME: Device object requires either a _HID or _ADR, but not both Name (_HID, "INTL9C60") Name (_UID, 1) Name (_ADR, 0x00150000) @@ -194,6 +195,7 @@ Device (I2C0) { // Serial IO I2C0 Controller + // FIXME: Device object requires either a _HID or _ADR, but not both Method (_HID) { If (\ISWP ()) { @@ -265,6 +267,7 @@ Device (I2C1) { // Serial IO I2C1 Controller + // FIXME: Device object requires either a _HID or _ADR, but not both Method (_HID) { If (\ISWP ()) { @@ -336,6 +339,7 @@ Device (SPI0) { // Serial IO SPI0 Controller + // FIXME: Device object requires either a _HID or _ADR, but not both Method (_HID) { If (\ISWP ()) { @@ -392,6 +396,7 @@ Device (SPI1) { // Serial IO SPI1 Controller + // FIXME: Device object requires either a _HID or _ADR, but not both Method (_HID) { If (\ISWP ()) { @@ -460,6 +465,7 @@ Device (UAR0) { // Serial IO UART0 Controller + // FIXME: Device object requires either a _HID or _ADR, but not both Method (_HID) { If (\ISWP ()) { @@ -528,6 +534,7 @@ Device (UAR1) { // Serial IO UART1 Controller + // FIXME: Device object requires either a _HID or _ADR, but not both Method (_HID) { If (\ISWP ()) { @@ -584,6 +591,7 @@ Device (SDIO) { // Serial IO SDIO Controller + // FIXME: Device object requires either a _HID or _ADR, but not both Method (_HID) { If (\ISWP ()) { -- To view, visit https://review.coreboot.org/c/coreboot/+/38350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e892c451ee9d4e576b568f7efaad2e390524fe0 Gerrit-Change-Number: 38350 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 26

Change in coreboot[master]: src: Remove unused include <device/pci.h>
by HAOUAS Elyes (Code Review) 16 Apr '20

16 Apr '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38610 ) Change subject: src: Remove unused include <device/pci.h> ...................................................................... src: Remove unused include <device/pci.h> Change-Id: I73430fdbdf6306df701480ab6353c840c71f607b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/acpi.c M src/commonlib/storage/pci_sdhci.c M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/device/device_const.c M src/device/oprom/realmode/x86.c M src/device/oprom/realmode/x86_interrupts.c M src/device/oprom/yabel/device.c M src/device/oprom/yabel/interrupt.c M src/device/oprom/yabel/io.c M src/device/pci_ops.c M src/device/pci_rom.c M src/drivers/aspeed/common/aspeed_coreboot.h M src/drivers/intel/gma/intel_ddi.c M src/drivers/intel/gma/opregion.c M src/drivers/intel/gma/vbt.c M src/drivers/xgi/common/xgi_coreboot.c M src/drivers/xgi/common/xgi_coreboot.h M src/lib/hardwaremain.c M src/lib/reg_script.c M src/mainboard/google/kahlee/variants/treeya/mainboard.c M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/nehalem/acpi.c M src/northbridge/intel/nehalem/smi.c M src/northbridge/intel/pineview/acpi.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/sandybridge/acpi.c M src/northbridge/intel/sandybridge/common.c M src/northbridge/intel/x4x/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/sata.c M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/sata.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/cavium/cn81xx/sdram.c M src/soc/cavium/common/ecam.c M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/lpc.c M src/soc/intel/apollolake/pmc.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/xdci.c M src/soc/intel/baytrail/elog.c M src/soc/intel/baytrail/gpio.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/scc.c M src/soc/intel/baytrail/smm.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/elog.c M src/soc/intel/braswell/gpio.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/scc.c M src/soc/intel/braswell/smm.c M src/soc/intel/broadwell/gpio.c M src/soc/intel/broadwell/me_status.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/pch.c M src/soc/intel/broadwell/pmutil.c M src/soc/intel/broadwell/romstage/power_state.c M src/soc/intel/broadwell/romstage/report_platform.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/cannonlake/me.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/cannonlake/systemagent.c M src/soc/intel/common/block/include/intelblocks/imc.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/common/block/scs/early_mmc.c M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/bootblock/bootblock.c M src/soc/intel/denverton_ns/gpio_dnv.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/espi.c M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/icelake/systemagent.c M src/soc/intel/quark/i2c.c M src/soc/intel/quark/include/soc/pci_devs.h M src/soc/intel/quark/include/soc/storage_test.h M src/soc/intel/quark/romstage/report_platform.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/lpc.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/tigerlake/bootblock/report_platform.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/tigerlake/finalize.c M src/soc/intel/tigerlake/fsp_params_tgl.c M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/tigerlake/smmrelocate.c M src/soc/intel/tigerlake/systemagent.c M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/spi.c M src/southbridge/amd/cimx/sb800/spi.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/intel/bd82x6x/elog.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/common/gpio.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/rcba_pirq.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/common/watchdog.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801dx/i82801dx.c M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801gx/i82801gx.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801ix/smi.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/ibexpeak/madt.c M src/southbridge/intel/ibexpeak/pch.c M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/lp_gpio.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/rcba.c M src/southbridge/intel/lynxpoint/smi.c M src/vendorcode/eltan/security/verified_boot/vboot_check.h 139 files changed, 0 insertions(+), 139 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/38610/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 2f793b4..5b5e587 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -28,7 +28,6 @@ #include <arch/acpi.h> #include <arch/acpi_ivrs.h> #include <arch/acpigen.h> -#include <device/pci.h> #include <cbmem.h> #include <commonlib/helpers.h> #include <cpu/x86/lapic_def.h> diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c index 380f2db..abade3d 100644 --- a/src/commonlib/storage/pci_sdhci.c +++ b/src/commonlib/storage/pci_sdhci.c @@ -13,7 +13,6 @@ */ #include <commonlib/sdhci.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <stdint.h> #include <string.h> diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index d259460..7d7922e 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -14,7 +14,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 834ec04..2920822 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/pci.h> #include <commonlib/helpers.h> #include <cpu/x86/cache.h> #include <cpu/x86/mp.h> diff --git a/src/device/device_const.c b/src/device/device_const.c index c46f283..698648e 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -14,7 +14,6 @@ #include <console/console.h> #include <device/device.h> #include <device/path.h> -#include <device/pci.h> #include <device/pci_def.h> #include <device/resource.h> diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 8ba0241..095e427 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -17,7 +17,6 @@ #include <boot/coreboot_tables.h> #include <console/console.h> #include <delay.h> -#include <device/pci.h> #include <device/pci_ids.h> #include <pc80/i8259.h> #include <pc80/i8254.h> diff --git a/src/device/oprom/realmode/x86_interrupts.c b/src/device/oprom/realmode/x86_interrupts.c index c38da46..6ed547b 100644 --- a/src/device/oprom/realmode/x86_interrupts.c +++ b/src/device/oprom/realmode/x86_interrupts.c @@ -13,7 +13,6 @@ #include <arch/registers.h> #include <console/console.h> -#include <device/pci.h> #include <device/pci_ops.h> /* we use x86emu's register file representation */ diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c index 4a50068..4814829 100644 --- a/src/device/oprom/yabel/device.c +++ b/src/device/oprom/yabel/device.c @@ -39,7 +39,6 @@ #include "debug.h" #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <device/resource.h> diff --git a/src/device/oprom/yabel/interrupt.c b/src/device/oprom/yabel/interrupt.c index 338156f..b9a708c 100644 --- a/src/device/oprom/yabel/interrupt.c +++ b/src/device/oprom/yabel/interrupt.c @@ -45,7 +45,6 @@ #include <x86emu/x86emu.h> #include "../x86emu/prim_ops.h" -#include <device/pci.h> #include <device/pci_ops.h> diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index 051a601..ec54ab0 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -41,7 +41,6 @@ #include <device/oprom/include/io.h> #include "io.h" -#include <device/pci.h> #include <device/pci_ops.h> #include <device/resource.h> diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 431160e..3e5a2ee 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -13,7 +13,6 @@ #include <stdint.h> #include <console/console.h> -#include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_type.h> diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 3676f9c..25acc30 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -14,7 +14,6 @@ #include <console/console.h> #include <commonlib/endian.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <string.h> diff --git a/src/drivers/aspeed/common/aspeed_coreboot.h b/src/drivers/aspeed/common/aspeed_coreboot.h index d3b6981..088ea55 100644 --- a/src/drivers/aspeed/common/aspeed_coreboot.h +++ b/src/drivers/aspeed/common/aspeed_coreboot.h @@ -24,7 +24,6 @@ #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> /* coreboot <--> kernel code interface */ diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index d52b293..163a9ac 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -32,7 +32,6 @@ #include <console/console.h> #include <arch/acpi.h> #include <smbios.h> -#include <device/pci.h> #include <ec/google/chromeec/ec.h> #include <cpu/x86/tsc.h> #include <cpu/x86/cache.h> diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 56449d0..1f46a76 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -17,7 +17,6 @@ #include <string.h> #include <cbfs.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c index 603044a..93c3cf9 100644 --- a/src/drivers/intel/gma/vbt.c +++ b/src/drivers/intel/gma/vbt.c @@ -15,7 +15,6 @@ #include <device/pci_ops.h> #include <device/device.h> #include <string.h> -#include <device/pci.h> #include <drivers/intel/gma/opregion.h> #include "i915.h" diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index d65e007..82a0179 100644 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -17,7 +17,6 @@ #include <vbe.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/vga.h> diff --git a/src/drivers/xgi/common/xgi_coreboot.h b/src/drivers/xgi/common/xgi_coreboot.h index a850087..0d368ac 100644 --- a/src/drivers/xgi/common/xgi_coreboot.h +++ b/src/drivers/xgi/common/xgi_coreboot.h @@ -25,7 +25,6 @@ #include <device/mmio.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include "initdef.h" diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index eba5f12..dc8fbb1 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -27,7 +27,6 @@ #include <cbmem.h> #include <version.h> #include <device/device.h> -#include <device/pci.h> #include <delay.h> #include <stdlib.h> #include <boot/tables.h> diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 299fd75..8eeda05 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -20,7 +20,6 @@ #include <delay.h> #include <device/device.h> #include <device/resource.h> -#include <device/pci.h> #include <stdint.h> #include <reg_script.h> diff --git a/src/mainboard/google/kahlee/variants/treeya/mainboard.c b/src/mainboard/google/kahlee/variants/treeya/mainboard.c index cd42b56..6d981d2 100644 --- a/src/mainboard/google/kahlee/variants/treeya/mainboard.c +++ b/src/mainboard/google/kahlee/variants/treeya/mainboard.c @@ -21,7 +21,6 @@ #include <smbios.h> #include <variant/gpio.h> #include <device/mmio.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <drivers/generic/bayhub/bh720.h> diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index 82b6221..6035b7e 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -19,7 +19,6 @@ #include <arch/acpi.h> #include <arch/acpigen.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ops.h> diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index d92e858..a9b687b 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <arch/acpi.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include "haswell.h" #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 3a9f6a2..66f26dd 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -18,7 +18,6 @@ #include <arch/acpi.h> #include <arch/acpigen.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include "i945.h" diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index 462cdc0..43b13c2 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -20,7 +20,6 @@ #include <types.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include "nehalem.h" diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c index 8c19852..c3433a3 100644 --- a/src/northbridge/intel/nehalem/smi.c +++ b/src/northbridge/intel/nehalem/smi.c @@ -15,7 +15,6 @@ #include <types.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include "nehalem.h" diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c index 9dd8e31..2e12305 100644 --- a/src/northbridge/intel/pineview/acpi.c +++ b/src/northbridge/intel/pineview/acpi.c @@ -18,7 +18,6 @@ #include <arch/acpigen.h> #include <arch/acpi.h> #include <device/device.h> -#include <device/pci.h> #include <northbridge/intel/pineview/pineview.h> #include <types.h> diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index c3cd380..2625fe6 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <device/pci.h> #include <northbridge/intel/pineview/pineview.h> #include <northbridge/intel/pineview/chip.h> #include <option.h> diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 4afb546..9665972 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -20,7 +20,6 @@ #include <commonlib/helpers.h> #include <arch/acpi.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include "sandybridge.h" #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/northbridge/intel/sandybridge/common.c b/src/northbridge/intel/sandybridge/common.c index 8bfd476..d141c99 100644 --- a/src/northbridge/intel/sandybridge/common.c +++ b/src/northbridge/intel/sandybridge/common.c @@ -18,7 +18,6 @@ #include <types.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include "sandybridge.h" enum platform_type get_platform_type(void) diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index a91d227..d25eb2b 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -20,7 +20,6 @@ #include <arch/acpi.h> #include <arch/acpigen.h> #include <device/device.h> -#include <device/pci.h> #include "x4x.h" unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 7b70ec6..4534f6a 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -27,7 +27,6 @@ #include <cpu/x86/smm.h> #include <cbmem.h> #include <device/device.h> -#include <device/pci.h> #include <amdblocks/acpimmio.h> #include <amdblocks/acpi.h> #include <soc/acpi.h> diff --git a/src/soc/amd/picasso/sata.c b/src/soc/amd/picasso/sata.c index d67f5b4..3d2571d 100644 --- a/src/soc/amd/picasso/sata.c +++ b/src/soc/amd/picasso/sata.c @@ -14,7 +14,6 @@ */ #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <amdblocks/sata.h> diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 0dff4bc..757656e 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -19,7 +19,6 @@ #include <cpu/x86/smm.h> #include <cpu/x86/msr.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <cbmem.h> #include <amdblocks/amd_pci_util.h> diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 13020ed..2cd4519 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -27,7 +27,6 @@ #include <cpu/x86/smm.h> #include <cbmem.h> #include <device/device.h> -#include <device/pci.h> #include <amdblocks/acpimmio.h> #include <amdblocks/acpi.h> #include <soc/acpi.h> diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c index d67f5b4..3d2571d 100644 --- a/src/soc/amd/stoneyridge/sata.c +++ b/src/soc/amd/stoneyridge/sata.c @@ -14,7 +14,6 @@ */ #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <amdblocks/sata.h> diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 1b2afec..1c10339 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -18,7 +18,6 @@ #include <bootstate.h> #include <cpu/x86/smm.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <cbmem.h> #include <amdblocks/amd_pci_util.h> diff --git a/src/soc/cavium/cn81xx/sdram.c b/src/soc/cavium/cn81xx/sdram.c index 71d6b48..1142a8a 100644 --- a/src/soc/cavium/cn81xx/sdram.c +++ b/src/soc/cavium/cn81xx/sdram.c @@ -32,7 +32,6 @@ #include <soc/ecam.h> #include <device/pci_ops.h> #include <device/mmio.h> -#include <device/pci.h> size_t sdram_size_mb(void) { diff --git a/src/soc/cavium/common/ecam.c b/src/soc/cavium/common/ecam.c index 89c69db..a3fc94c 100644 --- a/src/soc/cavium/common/ecam.c +++ b/src/soc/cavium/common/ecam.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> -#include <device/pci.h> #include <soc/addressmap.h> #include <soc/ecam.h> diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index a07c462..8a51224 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -17,7 +17,6 @@ #include <bootblock_common.h> #include <cpu/x86/pae.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 636dd03..660157c 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/rtc.h> #include <soc/gpio.h> diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 286cd8a..1d59766 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <device/mmio.h> #include <device/device.h> -#include <device/pci.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <soc/iomap.h> diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 559adad..715b922 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -24,7 +24,6 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include <intelblocks/msr.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/apollolake/xdci.c b/src/soc/intel/apollolake/xdci.c index 0a85f26..e918f15 100644 --- a/src/soc/intel/apollolake/xdci.c +++ b/src/soc/intel/apollolake/xdci.c @@ -16,7 +16,6 @@ #include <device/mmio.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <intelblocks/xdci.h> #include <soc/pci_devs.h> #include <timer.h> diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index d7a0460..18708a9 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cbmem.h> #include <device/device.h> -#include <device/pci.h> #include <elog.h> #include <soc/iomap.h> #include <soc/pmc.h> diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 3460a5f..fcc89c2 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -15,7 +15,6 @@ #include <arch/io.h> #include <device/mmio.h> -#include <device/pci.h> #include <console/console.h> #include <soc/gpio.h> #include <soc/pmc.h> diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 51174fc..b4b06f3 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -18,7 +18,6 @@ #include <arch/io.h> #include <device/device.h> #include <device/mmio.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index a6b4fe3..c56c042 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -17,7 +17,6 @@ #include <cbmem.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <reg_script.h> #include <soc/iosf.h> diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 9f10f70..0aa6f23 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -15,7 +15,6 @@ */ #include <device/device.h> -#include <device/pci.h> #include <console/console.h> #include <arch/io.h> #include <device/mmio.h> diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index f68b7ce..33720b4 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -26,7 +26,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> #include <cpu/x86/tsc.h> -#include <device/pci.h> #include <ec/google/chromeec/ec.h> #include <drivers/intel/gma/opregion.h> #include <soc/acpi.h> diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c index 6efcef1..7a82725 100644 --- a/src/soc/intel/braswell/elog.c +++ b/src/soc/intel/braswell/elog.c @@ -19,7 +19,6 @@ #include <cbmem.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <elog.h> #include <soc/iomap.h> #include <soc/pm.h> diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c index 14f95e1..d22e04e 100644 --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <arch/io.h> #include <device/mmio.h> -#include <device/pci.h> #include <soc/gpio.h> #include <soc/pm.h> #include <soc/smm.h> diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 18cb04d..11930d6 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -19,7 +19,6 @@ #include <assert.h> #include <device/device.h> #include <device/mmio.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <console/console.h> #include <soc/iomap.h> diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c index 5c874e1..08f4831 100644 --- a/src/soc/intel/braswell/scc.c +++ b/src/soc/intel/braswell/scc.c @@ -18,7 +18,6 @@ #include <cbmem.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <soc/iosf.h> #include <soc/nvs.h> #include <soc/ramstage.h> diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index c108a36..2f6610c 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -21,7 +21,6 @@ #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> #include <device/device.h> -#include <device/pci.h> #include <soc/iomap.h> #include <soc/pm.h> #include <soc/smm.h> diff --git a/src/soc/intel/broadwell/gpio.c b/src/soc/intel/broadwell/gpio.c index 81ad9d4..2831f85 100644 --- a/src/soc/intel/broadwell/gpio.c +++ b/src/soc/intel/broadwell/gpio.c @@ -16,7 +16,6 @@ #include <stdint.h> #include <arch/io.h> #include <device/device.h> -#include <device/pci.h> #include <soc/gpio.h> #include <soc/iomap.h> #include <soc/pm.h> diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c index d89f108..d494d71 100644 --- a/src/soc/intel/broadwell/me_status.c +++ b/src/soc/intel/broadwell/me_status.c @@ -15,7 +15,6 @@ #include <device/pci_ops.h> #include <console/console.h> -#include <device/pci.h> #include <string.h> #include <soc/pci_devs.h> #include <soc/me.h> diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 48492d3..837347c 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -17,7 +17,6 @@ #include <cbmem.h> #include <cpu/x86/smm.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index e6c2319..74536c9 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <device/pci_ops.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include <soc/iobp.h> #include <soc/pch.h> diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 00db615..5857cec 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -22,7 +22,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> #include <soc/iomap.h> diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index 1970c31..09ca8c0 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -18,7 +18,6 @@ #include <cbmem.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include <reg_script.h> #include <stdint.h> diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c index d60ed38..88be982 100644 --- a/src/soc/intel/broadwell/romstage/report_platform.c +++ b/src/soc/intel/broadwell/romstage/report_platform.c @@ -16,7 +16,6 @@ #include <arch/cpu.h> #include <device/pci_ops.h> #include <console/console.h> -#include <device/pci.h> #include <string.h> #include <cpu/x86/msr.h> #include <soc/cpu.h> diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 2bdeecc..2342e37 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -15,7 +15,6 @@ */ #include <device/device.h> -#include <device/pci.h> #include <console/console.h> #include <arch/io.h> #include <cpu/x86/cache.h> diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 7bf351a..c88b006 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -16,7 +16,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 67dd452..380acce 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/x86/name.h> -#include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/mp_init.h> #include <soc/bootblock.h> diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index f01b499..6ec1afe 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -15,7 +15,6 @@ #include <arch/cpu.h> #include <console/console.h> -#include <device/pci.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 002e8ea..2f45d37 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <console/post_codes.h> #include <cpu/x86/smm.h> -#include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelblocks/tco.h> diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dc4a2a8..b90266b 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -16,7 +16,6 @@ #include <cbmem.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/lpss.h> diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index c4eb884..84f66b26 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -16,7 +16,6 @@ */ #include <device/device.h> -#include <device/pci.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index 0414470..868b7c1 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -17,7 +17,6 @@ #include <bootstate.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <device/pci.h> #include <intelblocks/cse.h> #include <soc/me.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index aded9c0..e5cb8ed 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -24,7 +24,6 @@ #include <device/mmio.h> #include <cbmem.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index e99a9a2..ff81fe1 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index 3f01f14..e4d387b 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <delay.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <intelblocks/systemagent.h> #include <soc/cpu.h> diff --git a/src/soc/intel/common/block/include/intelblocks/imc.h b/src/soc/intel/common/block/include/intelblocks/imc.h index fc3c241..38564fb 100644 --- a/src/soc/intel/common/block/include/intelblocks/imc.h +++ b/src/soc/intel/common/block/include/intelblocks/imc.h @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <device/pci.h> #include <stdint.h> #ifndef SOC_INTEL_COMMON_BLOCK_IMC_H diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index bc89e4c..badda2b 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -19,7 +19,6 @@ #include <assert.h> #include <console/console.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <intelblocks/lpc_lib.h> #include <lib.h> diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c index 8036450..3285f6e 100644 --- a/src/soc/intel/common/block/scs/early_mmc.c +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -20,7 +20,6 @@ #include <commonlib/sdhci.h> #include <compiler.h> #include <console/console.h> -#include <device/pci.h> #include <intelblocks/mmc.h> #include <soc/iomap.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 1a215eb..b0ec217 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -16,7 +16,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include <intelblocks/pcr.h> #include <intelblocks/tco.h> diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 1273c0f..73b6026 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -18,7 +18,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <device/device.h> -#include <device/pci.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 163f76a..9552bb0 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -22,7 +22,6 @@ #include <arch/smp/mpspec.h> #include <cpu/x86/smm.h> #include <string.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index 47c76b5..6612cfd 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -16,7 +16,6 @@ #include <bootblock_common.h> #include <cpu/x86/mtrr.h> -#include <device/pci.h> #include <FsptUpd.h> #include <intelblocks/fast_spi.h> #include <soc/bootblock.h> diff --git a/src/soc/intel/denverton_ns/gpio_dnv.c b/src/soc/intel/denverton_ns/gpio_dnv.c index b083768..c79d282 100644 --- a/src/soc/intel/denverton_ns/gpio_dnv.c +++ b/src/soc/intel/denverton_ns/gpio_dnv.c @@ -19,7 +19,6 @@ #include <device/mmio.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <soc/iomap.h> #include <soc/pcr.h> diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index d05e76b..7326ab1 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -17,7 +17,6 @@ */ #include <device/device.h> -#include <device/pci.h> #include <console/console.h> #include <arch/io.h> #include <cpu/x86/smm.h> diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c index ef95f7e..648a27c 100644 --- a/src/soc/intel/denverton_ns/soc_util.c +++ b/src/soc/intel/denverton_ns/soc_util.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <device/pci.h> #include <device/pci_def.h> #include <device/device.h> #include <string.h> diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index 660aab9..4202fd2 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -17,7 +17,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/mp_init.h> #include <soc/bootblock.h> diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index e058442..b7a8512 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -15,7 +15,6 @@ #include <arch/cpu.h> #include <console/console.h> -#include <device/pci.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index efde625..acf9583 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -14,7 +14,6 @@ */ #include <device/device.h> -#include <device/pci.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 6afa61e..0d14124 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <console/post_codes.h> #include <cpu/x86/smm.h> -#include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelblocks/tco.h> diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 448b82c..a6a6117 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/lpss.h> diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 7b6168b..ac7e3af 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -23,7 +23,6 @@ #include <device/mmio.h> #include <cbmem.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 0bedc9e6..8d53bb9 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -16,7 +16,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> diff --git a/src/soc/intel/icelake/systemagent.c b/src/soc/intel/icelake/systemagent.c index 930e78e..36d38e7 100644 --- a/src/soc/intel/icelake/systemagent.c +++ b/src/soc/intel/icelake/systemagent.c @@ -14,7 +14,6 @@ */ #include <device/device.h> -#include <device/pci.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> #include <soc/systemagent.h> diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 6430030..e8aed2d 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -19,7 +19,6 @@ #include <delay.h> #include <device/device.h> #include <device/i2c_simple.h> -#include <device/pci.h> #include <soc/i2c.h> #include <soc/ramstage.h> #include <soc/reg_access.h> diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index a24f28f..e16aff7 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -18,7 +18,6 @@ #ifndef _QUARK_PCI_DEVS_H_ #define _QUARK_PCI_DEVS_H_ -#include <device/pci.h> #include <device/pci_def.h> /* DEVICE 0 (Memory Controller Hub) */ diff --git a/src/soc/intel/quark/include/soc/storage_test.h b/src/soc/intel/quark/include/soc/storage_test.h index 1c93f1c..a8bdd8b 100644 --- a/src/soc/intel/quark/include/soc/storage_test.h +++ b/src/soc/intel/quark/include/soc/storage_test.h @@ -18,7 +18,6 @@ #include <commonlib/sd_mmc_ctrlr.h> #include <device/device.h> -#include <device/pci.h> #include <timer.h> #ifdef __SIMPLE_DEVICE__ diff --git a/src/soc/intel/quark/romstage/report_platform.c b/src/soc/intel/quark/romstage/report_platform.c index cbbf43f..3e2b069 100644 --- a/src/soc/intel/quark/romstage/report_platform.c +++ b/src/soc/intel/quark/romstage/report_platform.c @@ -16,7 +16,6 @@ #include <arch/cpu.h> #include <console/console.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <soc/cpu.h> diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 4a519cf..10a72e3 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/x86/name.h> -#include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/mp_init.h> #include <soc/bootblock.h> diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index f5273f6..08210cb 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -19,7 +19,6 @@ #include <bootstate.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index e5d32d7..1ccaad0 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -22,7 +22,6 @@ #include <console/post_codes.h> #include <cpu/x86/mp.h> #include <cpu/x86/smm.h> -#include <device/pci.h> #include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index 6e6d655..4a1b283 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -14,7 +14,6 @@ */ #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/itss.h> diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 71ffb9a..7ff9eda 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -16,7 +16,6 @@ */ #include <device/device.h> -#include <device/pci.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/ioapic.h> diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index d53d91e..937f72b 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -17,7 +17,6 @@ #include <bootstate.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <device/pci.h> #include <intelblocks/cse.h> #include <soc/iomap.h> #include <soc/me.h> diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 2b2141b..dee0915 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -23,7 +23,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 62fc7e4..ae90068 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 127994d..4126674 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -23,7 +23,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/mp_init.h> #include <soc/bootblock.h> diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 5f4f081..c41807e 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -21,7 +21,6 @@ #include <arch/cpu.h> #include <console/console.h> -#include <device/pci.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index d07a582..18f5f80 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -20,7 +20,6 @@ */ #include <device/device.h> -#include <device/pci.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index aed5cc0..65ade16 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -25,7 +25,6 @@ #include <console/console.h> #include <console/post_codes.h> #include <cpu/x86/smm.h> -#include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelblocks/tco.h> diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 305748e..6aec3a1 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/lpss.h> diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 84a93ae..1dc3507 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -30,7 +30,6 @@ #include <device/mmio.h> #include <cbmem.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index 9e21a23..cd28a3a 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -16,7 +16,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 9c8f645..37e4abe 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -20,7 +20,6 @@ */ #include <device/device.h> -#include <device/pci.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> #include <soc/systemagent.h> diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index d586d33..f8a1151 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <device/mmio.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 9656027..53644b5 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -18,7 +18,6 @@ #include <spi_flash.h> #include <spi-generic.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <Proc/Fch/FchPlatform.h> diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index fcb4fa1..2256221 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -18,7 +18,6 @@ #include <spi_flash.h> #include <spi-generic.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <types.h> diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 51c37a1..db153fd 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -19,7 +19,6 @@ #include <device/mmio.h> #include <arch/acpi.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index e96c38d..65cab72 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -16,7 +16,6 @@ #include <arch/io.h> #include <arch/acpi.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <stdint.h> #include <elog.h> diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 5c2b130..3e19d61 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <delay.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <string.h> diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index 9731d75..19d33ae 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -17,7 +17,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> -#include <device/pci.h> #include "gpio.h" diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index ff0410a..5aea7d6 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -18,7 +18,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> -#include <device/pci.h> #include <assert.h> #include <security/vboot/vboot_common.h> diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 366fe08..f2ddeb0 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rcba_pirq.h> #include <southbridge/intel/common/rcba.h> diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 1348174..632b393 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -16,7 +16,6 @@ #include <device/device.h> -#include <device/pci.h> #include <console/console.h> #include <arch/io.h> #include <cpu/x86/cache.h> diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 8285200..4ff9ff4 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -28,7 +28,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <spi_flash.h> #include <spi-generic.h> #include <timer.h> diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c index 2eaedab..cace9d5 100644 --- a/src/southbridge/intel/common/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <southbridge/intel/common/pmbase.h> diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index cbfb0af..2496d19 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -20,7 +20,6 @@ #include <string.h> #include <arch/acpi.h> #include <device/device.h> -#include <device/pci.h> #include <version.h> #include "i82371eb.h" diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c index 765bcb2..759e726 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.c +++ b/src/southbridge/intel/i82801dx/i82801dx.c @@ -15,7 +15,6 @@ */ #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include "i82801dx.h" diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index dc53220..2209292 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -16,7 +16,6 @@ #include <device/device.h> -#include <device/pci.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/io.h> diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 6aab741..151a777 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include "i82801gx.h" #include "sata.h" diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 753c336a..9686ff8 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -19,7 +19,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> -#include <device/pci.h> #include <console/console.h> #include "chip.h" #include "i82801ix.h" diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 5f73f41..5650c75 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -17,7 +17,6 @@ #include <device/device.h> -#include <device/pci.h> #include <console/console.h> #include <arch/io.h> #include <device/pci_ops.h> diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index ebd427f..3c6e293 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -19,7 +19,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> -#include <device/pci.h> #include <console/console.h> #include "chip.h" #include "i82801jx.h" diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c index 3676a47..15b9510 100644 --- a/src/southbridge/intel/ibexpeak/madt.c +++ b/src/southbridge/intel/ibexpeak/madt.c @@ -19,7 +19,6 @@ #include <arch/acpi.h> #include <arch/smp/mpspec.h> #include <device/device.h> -#include <device/pci.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c index 9148b44..f8bcc10 100644 --- a/src/southbridge/intel/ibexpeak/pch.c +++ b/src/southbridge/intel/ibexpeak/pch.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <device/pci_ops.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 6f12c70..15f9604 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -16,7 +16,6 @@ #include <arch/io.h> #include <arch/acpi.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <stdint.h> #include <elog.h> diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index 1919d58..115229f 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -17,7 +17,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> -#include <device/pci.h> #include "pch.h" #include "lp_gpio.h" diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index cb50c12..cdd2065 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -19,7 +19,6 @@ #include <delay.h> #include <device/pci_ops.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index cc49477..095fe64 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -21,7 +21,6 @@ #include <arch/io.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> #include <security/vboot/vbnv.h> diff --git a/src/southbridge/intel/lynxpoint/rcba.c b/src/southbridge/intel/lynxpoint/rcba.c index 57253cb..d843547 100644 --- a/src/southbridge/intel/lynxpoint/rcba.c +++ b/src/southbridge/intel/lynxpoint/rcba.c @@ -15,7 +15,6 @@ #include <device/pci_def.h> #include <device/device.h> -#include <device/pci.h> #include "pch.h" void pch_config_rcba(const struct rcba_config_instruction *rcba_config) diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index e5c390e..0d6a548 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -16,7 +16,6 @@ #include <bootstate.h> #include <device/device.h> -#include <device/pci.h> #include <console/console.h> #include <arch/io.h> #include <cpu/intel/smm_reloc.h> diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.h b/src/vendorcode/eltan/security/verified_boot/vboot_check.h index bd28492..d432ee3 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.h +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.h @@ -19,7 +19,6 @@ #include <cbfs.h> #include <device/device.h> -#include <device/pci.h> #include <lib.h> #include CONFIG_VENDORCODE_ELTAN_VBOOT_MANIFEST #include <console/console.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/38610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73430fdbdf6306df701480ab6353c840c71f607b Gerrit-Change-Number: 38610 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 2

Change in ...coreboot[master]: autoport: Support bigger ACPI tables
by Iru Cai (vimacs) (Code Review) 16 Apr '20

16 Apr '20

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31759 to review the following change. Change subject: autoport: Support bigger ACPI tables ...................................................................... autoport: Support bigger ACPI tables DSDT can be bigger than 0x10000 bytes. Change-Id: Iaadcfd0964c1c516e9e39d6cbfe41ec9a8c45e9d Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/log_reader.go 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/31759/1 diff --git a/util/autoport/log_reader.go b/util/autoport/log_reader.go index d9a687a..0aaf6a9 100644 --- a/util/autoport/log_reader.go +++ b/util/autoport/log_reader.go @@ -107,12 +107,12 @@ curTable := "" for scanner.Scan() { line := scanner.Text() - /* Only supports ACPI tables up to 0x10000 in size, FIXME if needed */ - is_hexline, _ := regexp.MatchString(" *[0-9A-Fa-f]{4}: ", line) + /* Only supports ACPI tables up to 0x100000 in size, FIXME if needed */ + is_hexline, _ := regexp.MatchString(" *[0-9A-Fa-f]{4,5}: ", line) switch { case len(line) >= 6 && line[5] == '@': curTable = line[0:4] - Tables[curTable] = make([]byte, 0, 100000) + Tables[curTable] = make([]byte, 0, 0x100000) case is_hexline: Tables[curTable] = l.AssignHexLine(line, Tables[curTable]) } -- To view, visit https://review.coreboot.org/c/coreboot/+/31759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaadcfd0964c1c516e9e39d6cbfe41ec9a8c45e9d Gerrit-Change-Number: 31759 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: trogdor: add support for Bubs variant
by mturney mturney (Code Review) 15 Apr '20

15 Apr '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37069 ) Change subject: trogdor: add support for Bubs variant ...................................................................... trogdor: add support for Bubs variant Change-Id: I4d9bc98863c4f33c19e295b642f48c51921ed984 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- A payloads/libpayload/configs/config.bubs M src/mainboard/google/trogdor/Kconfig M src/mainboard/google/trogdor/Kconfig.name M src/mainboard/google/trogdor/reset.c 4 files changed, 24 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/37069/1 diff --git a/payloads/libpayload/configs/config.bubs b/payloads/libpayload/configs/config.bubs new file mode 100644 index 0000000..7e162e5 --- /dev/null +++ b/payloads/libpayload/configs/config.bubs @@ -0,0 +1,8 @@ +CONFIG_LP_CHROMEOS=y +CONFIG_LP_ARCH_ARM64=y +CONFIG_LP_TIMER_ARM64_ARCH=y +CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_QUALCOMM_QUPV3_SERIAL_CONSOLE=y +CONFIG_LP_USB=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index 56b3a72..6377c3a 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -8,20 +8,20 @@ def_bool y select BOARD_ROMSIZE_KB_8192 select COMMON_CBFS_SPI_WRAPPER - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_RTC - select EC_GOOGLE_CHROMEEC_SPI - select RTC + select EC_GOOGLE_CHROMEEC if BOARD_GOOGLE_TROGDOR + select EC_GOOGLE_CHROMEEC_RTC if BOARD_GOOGLE_TROGDOR + select EC_GOOGLE_CHROMEEC_SPI if BOARD_GOOGLE_TROGDOR + select RTC if BOARD_GOOGLE_TROGDOR select SOC_QUALCOMM_SC7180 select SPI_FLASH select SPI_FLASH_WINBOND select MAINBOARD_HAS_CHROMEOS config VBOOT - select EC_GOOGLE_CHROMEEC_SWITCHES + select EC_GOOGLE_CHROMEEC_SWITCHES if BOARD_GOOGLE_TROGDOR select VBOOT_VBNV_FLASH - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select VBOOT_MOCK_SECDATA + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if BOARD_GOOGLE_BUBS + select VBOOT_MOCK_SECDATA if BOARD_GOOGLE_BUBS config MAINBOARD_DIR string @@ -46,5 +46,6 @@ config MAINBOARD_PART_NUMBER string default "Trogdor" if BOARD_GOOGLE_TROGDOR + default "Bubs" if BOARD_GOOGLE_BUBS endif # BOARD_GOOGLE_TROGDOR_COMMON diff --git a/src/mainboard/google/trogdor/Kconfig.name b/src/mainboard/google/trogdor/Kconfig.name index 425c9bf..ba17254 100644 --- a/src/mainboard/google/trogdor/Kconfig.name +++ b/src/mainboard/google/trogdor/Kconfig.name @@ -1,4 +1,10 @@ +comment "Trogdor" config BOARD_GOOGLE_TROGDOR bool "Trogdor" select BOARD_GOOGLE_TROGDOR_COMMON + +config BOARD_GOOGLE_BUBS + bool "Bubs" + select BOARD_GOOGLE_TROGDOR_COMMON + diff --git a/src/mainboard/google/trogdor/reset.c b/src/mainboard/google/trogdor/reset.c index 558f63d..f099dda 100644 --- a/src/mainboard/google/trogdor/reset.c +++ b/src/mainboard/google/trogdor/reset.c @@ -21,5 +21,6 @@ but this works well enough for our purposes. */ void do_board_reset(void) { - google_chromeec_reboot(0, EC_REBOOT_COLD, 0); + if (CONFIG(BOARD_GOOGLE_TROGDOR)) + google_chromeec_reboot(0, EC_REBOOT_COLD, 0); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d9bc98863c4f33c19e295b642f48c51921ed984 Gerrit-Change-Number: 37069 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

6 18

Change in coreboot[master]: mb/lenovo/x60: Add VBOOT support
by Arthur Heymans (Code Review) 15 Apr '20

15 Apr '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37148 ) Change subject: mb/lenovo/x60: Add VBOOT support ...................................................................... mb/lenovo/x60: Add VBOOT support This also adds vboot support for the i945 platform in general. It's relatively slow to boot. It takes 1.5s to get to the payload. In timestamps there are entries related to TPM, which are somewhat weird given that the TPM is not enabled on this device (buggy). TESTED: boot X60, with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y you can force the recovery bootpath. Change-Id: Ia9666194e98b7d23b97eaff08e6177684e35eca7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x60/Kconfig M src/mainboard/lenovo/x60/cmos.layout A src/mainboard/lenovo/x60/vboot-rwa.fmd M src/northbridge/intel/i945/Kconfig 4 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/37148/1 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index a1a5fec..3b5fa85 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -26,6 +26,20 @@ select I945_LVDS select INTEL_GMA_HAVE_VBT +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x78 + config MAINBOARD_DIR string default lenovo/x60 diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index bfc78bc..4de7c06 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -94,6 +94,8 @@ 1040 8 r 0 RCVENMT 1048 4 r 0 C0DRT1 1052 4 r 0 C1DRT1 + +1056 128 r 0 vbnv # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/lenovo/x60/vboot-rwa.fmd b/src/mainboard/lenovo/x60/vboot-rwa.fmd new file mode 100644 index 0000000..b21cff3 --- /dev/null +++ b/src/mainboard/lenovo/x60/vboot-rwa.fmd @@ -0,0 +1,19 @@ +FLASH@0xffe00000 0x200000 { + BIOS { + RW_SECTION_A 0x100000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + RW_VPD(PRESERVE) 0x1000 + CONSOLE 0x10000 + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index a0550ec..a624bf4 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -29,6 +29,10 @@ select PARALLEL_MP select C_ENVIRONMENT_BOOTBLOCK +config VBOOT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n config NORTHBRIDGE_INTEL_SUBTYPE_I945GM -- To view, visit https://review.coreboot.org/c/coreboot/+/37148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9666194e98b7d23b97eaff08e6177684e35eca7 Gerrit-Change-Number: 37148 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 25

Change in coreboot[master]: mainboard/puff: Tune ALC5682I rise_fall times on i2c
by Edward O'Callaghan (Code Review) 15 Apr '20

15 Apr '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38459 ) Change subject: mainboard/puff: Tune ALC5682I rise_fall times on i2c ...................................................................... mainboard/puff: Tune ALC5682I rise_fall times on i2c Tunes the headphone amp i2c with measured signal shape. BUG=b:147192377 BRANCH=none TEST=builds Change-Id: I60f73bcf60ed140f595c953be371b982a63f7b95 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/38459/1 diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index e3ccc61..e23dc90 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -107,8 +107,8 @@ }, .i2c[4] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, + .rise_time_ns = 60, + .fall_time_ns = 60, }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/38459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60f73bcf60ed140f595c953be371b982a63f7b95 Gerrit-Change-Number: 38459 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: Documentation/vboot: Drop deprecated options from example
by Arthur Heymans (Code Review) 14 Apr '20

14 Apr '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37149 ) Change subject: Documentation/vboot: Drop deprecated options from example ...................................................................... Documentation/vboot: Drop deprecated options from example 4K keys are now default. Change-Id: I16599d0e8b874f9e8a56100fea06d6e4f94a5c00 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/security/vboot/index.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/37149/1 diff --git a/Documentation/security/vboot/index.md b/Documentation/security/vboot/index.md index 400c2b5..12b49de 100644 --- a/Documentation/security/vboot/index.md +++ b/Documentation/security/vboot/index.md @@ -229,7 +229,7 @@ # The keys were made using the following command # # 3rdparty/vboot/scripts/keygeneration/create_new_keys.sh \ -# --4k --4k-root --output $PWD/keys +# --output $PWD/keys # # # The "magic" numbers below are derived from the GBB section in -- To view, visit https://review.coreboot.org/c/coreboot/+/37149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16599d0e8b874f9e8a56100fea06d6e4f94a5c00 Gerrit-Change-Number: 37149 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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