coreboot-gerrit February 2020

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Change in ...coreboot[master]: src/mainboard/asus/am1i-a/buildOpts.c: uncomment the RAM speed-relate...
by Mike Banon (Code Review) 11 Apr '20

11 Apr '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33918 Change subject: src/mainboard/asus/am1i-a/buildOpts.c: uncomment the RAM speed-related defines ...................................................................... src/mainboard/asus/am1i-a/buildOpts.c: uncomment the RAM speed-related defines Not sure why they have been commented out. Bringing them back does not affect a system operation, and they may be useful later while fixing the low RAM speeds. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ic0468d329c6efa9abffc8859a542aae0cf702863 --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 25 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/33918/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 643b306..cba0894 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -265,31 +265,31 @@ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE*/ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define DDR2100_FREQUENCY 1050 ///< DDR 2100 +#define DDR2133_FREQUENCY 1066 ///< DDR 2133 +#define DDR2400_FREQUENCY 1200 ///< DDR 2400 +#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode /* * Agesa optional capabilities selection. -- To view, visit https://review.coreboot.org/c/coreboot/+/33918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0468d329c6efa9abffc8859a542aae0cf702863 Gerrit-Change-Number: 33918 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/sony: Add Sony VPCEH2K1E
by Angel Pons (Code Review) 11 Apr '20

11 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30973 Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ...................................................................... src/mainboard/sony: Add Sony VPCEH2K1E Run autoport. It has a Nvidia graphics card and a Nuvoton NPCE795 EC. Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/sony/vpceh2k1e/Kconfig A src/mainboard/sony/vpceh2k1e/Kconfig.name A src/mainboard/sony/vpceh2k1e/Makefile.inc A src/mainboard/sony/vpceh2k1e/acpi/ec.asl A src/mainboard/sony/vpceh2k1e/acpi/platform.asl A src/mainboard/sony/vpceh2k1e/acpi/superio.asl A src/mainboard/sony/vpceh2k1e/acpi_tables.c A src/mainboard/sony/vpceh2k1e/board_info.txt A src/mainboard/sony/vpceh2k1e/devicetree.cb A src/mainboard/sony/vpceh2k1e/dsdt.asl A src/mainboard/sony/vpceh2k1e/gpio.c A src/mainboard/sony/vpceh2k1e/hda_verb.c A src/mainboard/sony/vpceh2k1e/mainboard.c A src/mainboard/sony/vpceh2k1e/romstage.c 14 files changed, 700 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/30973/1 diff --git a/src/mainboard/sony/vpceh2k1e/Kconfig b/src/mainboard/sony/vpceh2k1e/Kconfig new file mode 100644 index 0000000..7d1f6ca --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/Kconfig @@ -0,0 +1,44 @@ +if BOARD_SONY_VPCEH2K1E + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select CPU_INTEL_SOCKET_RPGA989 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default sony_corporation/vpceh2k1e + +config MAINBOARD_PART_NUMBER + string + default "VPCEH2K1E" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x908b + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x104d + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/sony/vpceh2k1e/Kconfig.name b/src/mainboard/sony/vpceh2k1e/Kconfig.name new file mode 100644 index 0000000..3de2fcc --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SONY_VPCEH2K1E + bool "VPCEH2K1E" diff --git a/src/mainboard/sony/vpceh2k1e/Makefile.inc b/src/mainboard/sony/vpceh2k1e/Makefile.inc new file mode 100644 index 0000000..3dae61e --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/sony/vpceh2k1e/acpi/ec.asl b/src/mainboard/sony/vpceh2k1e/acpi/ec.asl new file mode 100644 index 0000000..9988369 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi/ec.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/sony/vpceh2k1e/acpi/platform.asl b/src/mainboard/sony/vpceh2k1e/acpi/platform.asl new file mode 100644 index 0000000..15d53d9 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi/platform.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/sony/vpceh2k1e/acpi/superio.asl b/src/mainboard/sony/vpceh2k1e/acpi/superio.asl new file mode 100644 index 0000000..8bfc1a0 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi/superio.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/sony/vpceh2k1e/acpi_tables.c b/src/mainboard/sony/vpceh2k1e/acpi_tables.c new file mode 100644 index 0000000..7d634a0 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi_tables.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/sony/vpceh2k1e/board_info.txt b/src/mainboard/sony/vpceh2k1e/board_info.txt new file mode 100644 index 0000000..689ca8f --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/board_info.txt @@ -0,0 +1,5 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/sony/vpceh2k1e/devicetree.cb b/src/mainboard/sony/vpceh2k1e/devicetree.cb new file mode 100644 index 0000000..d96ae12 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/devicetree.cb @@ -0,0 +1,63 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + subsystemid 0x104d 0x908b inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x000c0601" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x00040069" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x9" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge PCI-LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 off end # Internal graphics + end +end diff --git a/src/mainboard/sony/vpceh2k1e/dsdt.asl b/src/mainboard/sony/vpceh2k1e/dsdt.asl new file mode 100644 index 0000000..675703b --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/sony/vpceh2k1e/gpio.c b/src/mainboard/sony/vpceh2k1e/gpio.c new file mode 100644 index 0000000..5a16e8e --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/gpio.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio9 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio49 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/sony/vpceh2k1e/hda_verb.c b/src/mainboard/sony/vpceh2k1e/hda_verb.c new file mode 100644 index 0000000..d2c4fa3 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/hda_verb.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec Vendor / Device ID: Conexant */ + 0x104d5a00, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x104d5a00), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x03211040), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x400001f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x03a15030), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x400001f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x400001f0), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x400001f0), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x90170110), + + /* NID 0x20. */ + AZALIA_PIN_CFG(0x0, 0x20, 0x400001f0), + + /* NID 0x22. */ + AZALIA_PIN_CFG(0x0, 0x22, 0x400001f0), + + /* NID 0x23. */ + AZALIA_PIN_CFG(0x0, 0x23, 0x90a70150), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/sony/vpceh2k1e/mainboard.c b/src/mainboard/sony/vpceh2k1e/mainboard.c new file mode 100644 index 0000000..08cb738 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/mainboard.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(struct device *dev) +{ + /* FIXME: trim this down or remove if necessary */ + if (0) { + int i; + const u8 dmp[256] = { + /* 00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0x94, 0x94, 0x94, 0x94, 0x94, + /* 10 */ 0x94, 0x94, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x14, 0xc0, 0x00, + /* 40 */ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x2d, 0x29, 0x00, 0x31, 0x00, 0x00, 0x00, 0x00, + /* 60 */ 0x41, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x6e, 0x0a, 0x28, 0x0a, 0x01, 0x01, 0x26, 0x00, 0x00, 0x00, + /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* c0 */ 0x10, 0x02, 0x00, 0x00, 0x09, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, + /* d0 */ 0x00, 0xff, 0x00, 0x00, 0x01, 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0b, 0x1a, + /* e0 */ 0x28, 0x28, 0x28, 0x00, 0x00, 0x00, 0x58, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + + printk(BIOS_DEBUG, "Replaying EC dump ..."); + for (i = 0; i < 256; i++) + ec_write (i, dmp[i]); + printk(BIOS_DEBUG, "done\n"); + } + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/sony/vpceh2k1e/romstage.c b/src/mainboard/sony/vpceh2k1e/romstage.c new file mode 100644 index 0000000..0e1c365 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/romstage.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c01); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0601); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 0, 1, -1 }, + { 1, 1, 3 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 0, 1, -1 }, + { 1, 0, -1 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Gerrit-Change-Number: 30973 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 20

Change in coreboot[master]: cpu/x86/mtrr: Add function to set MTRR with CR0.CD set
by Arthur Heymans (Code Review) 10 Apr '20

10 Apr '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36382 ) Change subject: cpu/x86/mtrr: Add function to set MTRR with CR0.CD set ...................................................................... cpu/x86/mtrr: Add function to set MTRR with CR0.CD set MTRRs should only be changed when CR0.CD is set. In a CAR environment this is a rather fragile thing to do. This is why it is best to implement this in assembly. Change-Id: I4ff59d35ade125f60ed0002a386f41fd8ad54073 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/mtrr/earlymtrr.c A src/cpu/x86/mtrr/set_mtrr.S M src/include/cpu/x86/mtrr.h 4 files changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/36382/1 diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index caa6e9c..4052c52 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -3,6 +3,9 @@ romstage-y += earlymtrr.c bootblock-y += earlymtrr.c +bootblock-y += set_mtrr.S +verstage-y += set_mtrr.S + bootblock-y += debug.c romstage-y += debug.c postcar-y += debug.c diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 02dfbdc..2f6a64d 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -52,3 +52,17 @@ maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1; wrmsr(MTRR_PHYS_MASK(reg), maskm); } + +void set_var_mtrr_uncached( + unsigned int reg, unsigned int base, unsigned int size, + unsigned int type) +{ + /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ + /* FIXME: It only support 4G less range */ + msr_t basem, maskm; + basem.lo = base | type; + basem.hi = 0; + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; + maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1; + set_var_mtrr_uncached_asm(reg, basem, maskm); +} diff --git a/src/cpu/x86/mtrr/set_mtrr.S b/src/cpu/x86/mtrr/set_mtrr.S new file mode 100644 index 0000000..43c19f7 --- /dev/null +++ b/src/cpu/x86/mtrr/set_mtrr.S @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> +.global set_var_mtrr_uncached_asm + /* ARG0: mtrr_num + * ARG1: mtrr_base.lo + * ARG2: mtrr_base.hi + * ARG3: mtrr_mask.lo + * ARG4: mtrr_mask.hi + */ +.code32 +set_var_mtrr_uncached_asm: + /* Callee saved registers */ + pushl %ebp + movl %esp, %ebp + addl $8, %ebp + pushl %ebx + pushl %edx + pushl %esi + pushl %edi + + movl 0(%ebp), %ecx + movl 4(%ebp), %ebx + movl 8(%ebp), %edx + movl 12(%ebp), %esi + movl 16(%ebp), %edi + + /* Disable caching before setting MTRR */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + /* MTRR_PHYS_BASE */ + imul $2, %ecx, %ecx + addl $MTRR_PHYS_BASE(0), %ecx + movl %ebx, %eax + wrmsr + /* MTRR_PHYS_MASK */ + addl $1, %ecx + movl %esi, %eax + movl %edi, %edx + wrmsr + + /* Enable cache again. */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + movl %eax, %cr0 + + /* Restore Callee saved registers */ + popl %edi + popl %esi + popl %edx + popl %ebx + popl %ebp + ret diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 29256c8..103388f 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -107,6 +107,10 @@ void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, unsigned int type); int get_free_var_mtrr(void); +void set_var_mtrr_uncached(unsigned int reg, unsigned int base, + unsigned int size, unsigned int type); +__attribute__((cdecl)) void set_var_mtrr_uncached_asm(unsigned int reg, + msr_t base, msr_t mask); asmlinkage void display_mtrrs(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/36382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ff59d35ade125f60ed0002a386f41fd8ad54073 Gerrit-Change-Number: 36382 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: soc/amd: Use common functions to pass UMA information to ramstage
by Arthur Heymans (Code Review) 08 Apr '20

08 Apr '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36292 ) Change subject: soc/amd: Use common functions to pass UMA information to ramstage ...................................................................... soc/amd: Use common functions to pass UMA information to ramstage This removes the custom implementation using the BIOSRAM scratchpad space. Change-Id: I97a14044a93d1188cacc488006abe50a112d0eb8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/pi/Makefile.inc M src/soc/amd/common/block/pi/agesawrapper.c A src/soc/amd/common/block/pi/uma.c M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/southbridge.c 10 files changed, 65 insertions(+), 122 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36292/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index edb3882..03cea2e 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -139,45 +139,6 @@ /* pm2 read/write - access registers at 0xfed80400 - currently unused by any soc */ #endif -#if SUPPORTS_ACPIMMIO_BIOSRAM_BASE -/* biosram read/write - access registers at 0xfed80500 */ - -uint8_t biosram_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); -} - -uint16_t biosram_read16(uint8_t reg) /* Must be 1 byte at a time */ -{ - return (biosram_read8(reg + sizeof(uint8_t)) << 8 | biosram_read8(reg)); -} - -uint32_t biosram_read32(uint8_t reg) -{ - uint32_t value = biosram_read16(reg + sizeof(uint16_t)) << 16; - return value | biosram_read16(reg); -} - -void biosram_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); -} - -void biosram_write16(uint8_t reg, uint16_t value) -{ - biosram_write8(reg, value & 0xff); - value >>= 8; - biosram_write8(reg + sizeof(uint8_t), value & 0xff); -} - -void biosram_write32(uint8_t reg, uint32_t value) -{ - biosram_write16(reg, value & 0xffff); - value >>= 16; - biosram_write16(reg + sizeof(uint16_t), value & 0xffff); -} -#endif /* SUPPORTS_ACPIMMIO_BIOSRAM_BASE */ - #if SUPPORTS_ACPIMMIO_CMOSRAM_BASE /* cmosram read/write - access registers at 0xfed80600 - currently unused by any soc */ #endif diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 59ab9e5..879b9b9 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -194,14 +194,6 @@ void pm2_write16(uint8_t reg, uint16_t value); void pm2_write32(uint8_t reg, uint32_t value); -/* Access BIOS RAM storage at 0xfed80500 */ -uint8_t biosram_read8(uint8_t reg); -uint16_t biosram_read16(uint8_t reg); -uint32_t biosram_read32(uint8_t reg); -void biosram_write8(uint8_t reg, uint8_t value); -void biosram_write16(uint8_t reg, uint16_t value); -void biosram_write32(uint8_t reg, uint32_t value); - /* Access ACPI registers at 0xfed80800 */ uint8_t acpi_read8(uint8_t reg); uint16_t acpi_read16(uint8_t reg); diff --git a/src/soc/amd/common/block/pi/Makefile.inc b/src/soc/amd/common/block/pi/Makefile.inc index 5afbb3e..41995f6 100644 --- a/src/soc/amd/common/block/pi/Makefile.inc +++ b/src/soc/amd/common/block/pi/Makefile.inc @@ -1,11 +1,13 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PI),y) +romstage-y += uma.c romstage-y += agesawrapper.c romstage-y += def_callouts.c romstage-y += heapmanager.c romstage-y += image.c romstage-y += refcode_loader.c +ramstage-y += uma.c ramstage-y += agesawrapper.c ramstage-y += amd_late_init.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += amd_resume_final.c diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 022a8bc..77afeab 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -205,8 +205,8 @@ top = PostParams->MemConfig.Sub4GCacheTop; save_ram_top(top); - save_uma_size(PostParams->MemConfig.UmaSize * 64 * KiB); - save_uma_base((u64)PostParams->MemConfig.UmaBase * 64 * KiB); + save_uma((u64)PostParams->MemConfig.UmaBase * 64 * KiB, + PostParams->MemConfig.UmaSize * 64 * KiB); print_init_post_settings(PostParams); diff --git a/src/soc/amd/common/block/pi/uma.c b/src/soc/amd/common/block/pi/uma.c new file mode 100644 index 0000000..5d46855 --- /dev/null +++ b/src/soc/amd/common/block/pi/uma.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <romstage_handoff.h> +#include <soc/southbridge.h> +#include <console/console.h> + + +struct save_uma { + uint64_t base; + uint32_t size; +}; + +void save_uma(uint64_t uma_base, uint32_t uma_size) +{ + struct save_uma save = { + .base = uma_base, + .size = uma_size + }; + if (save_romstage_info(&save, sizeof(save))) { + printk(BIOS_DEBUG, "Saving uma information failed!\n"); + return; + } +} + +void get_uma(uint64_t *uma_base, uint32_t *uma_size) +{ + struct save_uma save; + if (get_romstage_info(&save, sizeof(save))) { + printk(BIOS_ERR, "Getting saved uma information failed!\n"); + return; + } + *uma_base = save.base; + *uma_size = save.size; +} diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 36135f9..f52c622 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -261,14 +261,16 @@ void domain_set_resources(struct device *dev) { - uint64_t uma_base = get_uma_base(); - uint32_t uma_size = get_uma_size(); + uint64_t uma_base; + uint32_t uma_size; uint32_t mem_useable = (uintptr_t)cbmem_top(); msr_t tom = rdmsr(TOP_MEM); msr_t high_tom = rdmsr(TOP_MEM2); uint64_t high_mem_useable; int idx = 0x10; + get_uma(&uma_base, &uma_size); + /* 0x0 -> 0x9ffff */ ram_resource(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 00e7b0f..1562dc7 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -576,27 +576,3 @@ * on entry into BS_DEV_ENABLE. */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); - -void save_uma_size(uint32_t size) -{ - biosram_write32(BIOSRAM_UMA_SIZE, size); -} - -void save_uma_base(uint64_t base) -{ - biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); - biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); -} - -uint32_t get_uma_size(void) -{ - return biosram_read32(BIOSRAM_UMA_SIZE); -} - -uint64_t get_uma_base(void) -{ - uint64_t base; - base = biosram_read32(BIOSRAM_UMA_BASE); - base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); - return base; -} diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index dd514ab..4504621 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -353,35 +353,19 @@ /** * @brief Save the UMA bize returned by AGESA * - * @param size = in bytes + * @param base, size = in bytes * * @return none */ -void save_uma_size(uint32_t size); +void save_uma(uint64_t uma_base, uint32_t uma_size); /** - * @brief Save the UMA base address returned by AGESA + * @brief Get the UMA bize returned by AGESA * - * @param base = 64bit base address + * @param Pointer base, size = in bytes * * @return none */ -void save_uma_base(uint64_t base); -/** - * @brief Get the saved UMA size - * - * @param none - * - * @return size in bytes - */ -uint32_t get_uma_size(void); -/** - * @brief Get the saved UMA base - * - * @param none - * - * @return 64bit base address - */ -uint64_t get_uma_base(void); +void get_uma(uint64_t *uma_base, uint32_t *uma_size); /* * Call the mainboard to get the USB Over Current Map. The mainboard * returns the map and 0 on Success or -1 on error or no map. There is diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 044a1b0..c6f7058 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -413,14 +413,16 @@ void domain_set_resources(struct device *dev) { - uint64_t uma_base = get_uma_base(); - uint32_t uma_size = get_uma_size(); + uint64_t uma_base; + uint32_t uma_size; uint32_t mem_useable = (uintptr_t)cbmem_top(); msr_t tom = rdmsr(TOP_MEM); msr_t high_tom = rdmsr(TOP_MEM2); uint64_t high_mem_useable; int idx = 0x10; + get_uma(&uma_base, &uma_size); + /* 0x0 -> 0x9ffff */ ram_resource(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index d7a09aa..96e587d 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -36,6 +36,7 @@ #include <agesa_headers.h> #include <soc/nvs.h> #include <types.h> +#include <romstage_handoff.h> /* * Table of devices that need their AOAC registers enabled and waited @@ -648,27 +649,3 @@ * on entry into BS_DEV_ENABLE. */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); - -void save_uma_size(uint32_t size) -{ - biosram_write32(BIOSRAM_UMA_SIZE, size); -} - -void save_uma_base(uint64_t base) -{ - biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); - biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); -} - -uint32_t get_uma_size(void) -{ - return biosram_read32(BIOSRAM_UMA_SIZE); -} - -uint64_t get_uma_base(void) -{ - uint64_t base; - base = biosram_read32(BIOSRAM_UMA_BASE); - base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); - return base; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/36292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a14044a93d1188cacc488006abe50a112d0eb8 Gerrit-Change-Number: 36292 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: lib/romstage_handoff: Add methods to pass on romstage information
by Arthur Heymans (Code Review) 08 Apr '20

08 Apr '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36291 ) Change subject: lib/romstage_handoff: Add methods to pass on romstage information ...................................................................... lib/romstage_handoff: Add methods to pass on romstage information Add 2 generic function that can be used to pass on information from romstage to ramstage. The implementation is such that the saving can be done even if cbmem is not set up initially. TODO: Does it need guarding because it needlessly increases .bss usage? Change-Id: I71bbe1b776cbc74468a6218b315894602b6152ba Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/include/commonlib/cbmem_id.h M src/include/romstage_handoff.h M src/lib/romstage_handoff.c 3 files changed, 79 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/36291/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 30bf88a..89d9478 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -77,6 +77,7 @@ #define CBMEM_ID_ROM2 0x524f4d32 #define CBMEM_ID_ROM3 0x524f4d33 #define CBMEM_ID_FMAP 0x464d4150 +#define CBMEM_ID_ROMSTAGE_SAVE 0xa7d1f2f3 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index db998ec..bbb0869 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -21,4 +21,11 @@ /* Return 1 if resuming or 0 if not. */ int romstage_handoff_is_resume(void); +/* Returns 0 on success, 1 if the info was copied to a buffer to be migrated + to cbmem later on, < 0 on failure. */ +int save_romstage_info(void *info, size_t info_size); + +/* Return 0 on success, else < 0 on failure */ +int get_romstage_info(void *info, size_t info_size); + #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c index 04ead0a..2f26194 100644 --- a/src/lib/romstage_handoff.c +++ b/src/lib/romstage_handoff.c @@ -77,3 +77,74 @@ return handoff->s3_resume; } + +static u8 save_buffer[256]; +static size_t used_buffer_size; +static int is_migrated; + +static void migrate_save_buffer(int is_recovery) +{ + if (used_buffer_size) + printk(BIOS_DEBUG, "Migrating the romstage save buffer to cbmem\n"); + is_migrated = 1; + save_romstage_info(save_buffer, used_buffer_size); +} + +ROMSTAGE_CBMEM_INIT_HOOK(migrate_save_buffer); + +int save_romstage_info(void *info, size_t save_size) +{ + const struct cbmem_entry *e; + + printk(BIOS_SPEW, "Romstage save: saving %p, size %zu\n", + info, save_size); + + e = cbmem_entry_find(CBMEM_ID_ROMSTAGE_SAVE); + if (e != NULL) { + if (cbmem_entry_size(e) > save_size) { + memcpy(cbmem_entry_start(e), info, save_size); + return 0; + } + cbmem_entry_remove(e); + } + + e = cbmem_entry_add(CBMEM_ID_ROMSTAGE_SAVE, save_size); + if (e == NULL && is_migrated) { + printk(BIOS_ERR, "Can't copy romstage save buffer to cbmem!\n"); + return -1; + } + + if (e != NULL) { + memcpy(cbmem_entry_start(e), info, save_size); + return 0; + } + + /* Cbmem is not yet up, save it for later */ + printk(BIOS_SPEW, "Romstage save: cbmem not yet up, saving info buffer for later\n"); + if (sizeof(save_buffer) < save_size) { + printk(BIOS_ERR, "Romstage save: buffer too small!\n"); + return -1; + } + memcpy(save_buffer, info, save_size); + used_buffer_size = save_size; + return 1; +} + +int get_romstage_info(void *info, size_t save_size) +{ + const struct cbmem_entry *e; + e = cbmem_entry_find(CBMEM_ID_ROMSTAGE_SAVE); + + if (e == NULL) { + printk(BIOS_ERR, "Can't find romstage save\n"); + return -1; + } + + if (save_size > cbmem_entry_size(e)) { + printk(BIOS_ERR, "Romstage save: requested size too large!\n"); + return -1; + } + + memcpy(info, cbmem_entry_start(e), save_size); + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71bbe1b776cbc74468a6218b315894602b6152ba Gerrit-Change-Number: 36291 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: rules.h: Add ENV_EARLY_RAM
by Marshall Dawson (Code Review) 08 Apr '20

08 Apr '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37486 ) Change subject: rules.h: Add ENV_EARLY_RAM ...................................................................... rules.h: Add ENV_EARLY_RAM Add a definition for environments where the x86's reset vector is in DRAM and a unique linker file must be used to coordinate regions across stages. Change-Id: I03703ae37a835de08ad8c905bafa504bdc41e959 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/include/rules.h 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/37486/1 diff --git a/src/include/rules.h b/src/include/rules.h index fa60ede..1947ede 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -255,8 +255,10 @@ #if CONFIG(ARCH_X86) /* Indicates memory layout is determined with arch/x86/car.ld. */ #define ENV_CACHE_AS_RAM (ENV_ROMSTAGE_OR_BEFORE && !CONFIG(RESET_VECTOR_IN_RAM)) +/* Reset vector is in DRAM, and memory layout is determined by its own .ld file. */ +#define ENV_EARLY_RAM (ENV_ROMSTAGE_OR_BEFORE && CONFIG(RESET_VECTOR_IN_RAM)) /* No .data sections with execute-in-place from ROM. */ -#define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM +#define ENV_STAGE_HAS_DATA_SECTION (!ENV_CACHE_AS_RAM && !ENV_EARLY_RAM) /* No .bss sections for stage with CAR teardown. */ #define ENV_STAGE_HAS_BSS_SECTION 1 #else -- To view, visit https://review.coreboot.org/c/coreboot/+/37486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03703ae37a835de08ad8c905bafa504bdc41e959 Gerrit-Change-Number: 37486 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: program.ld: Qualify .bss linking with ENV_EARLY_RAM
by Marshall Dawson (Code Review) 08 Apr '20

08 Apr '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37487 ) Change subject: program.ld: Qualify .bss linking with ENV_EARLY_RAM ...................................................................... program.ld: Qualify .bss linking with ENV_EARLY_RAM Systems with ENV_EARLY_RAM need to position .bss in a consistent location across early stages, and not necessarily within the program region. Skip the default .bss section for these designs. A subsequent patch will add the early linker script. Change-Id: Icde1cfd02611b8cce634aa76f5c192d5b637cf44 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/lib/program.ld 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/37487/1 diff --git a/src/lib/program.ld b/src/lib/program.ld index a9d4e48..1c8f99e 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -125,7 +125,7 @@ } #endif -#if ENV_STAGE_HAS_BSS_SECTION && !ENV_CACHE_AS_RAM +#if (ENV_STAGE_HAS_BSS_SECTION && !ENV_CACHE_AS_RAM && !ENV_EARLY_RAM) .bss . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; -- To view, visit https://review.coreboot.org/c/coreboot/+/37487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icde1cfd02611b8cce634aa76f5c192d5b637cf44 Gerrit-Change-Number: 37487 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: vc/amd/fsp/picasso: Add file for GUIDs
by Marshall Dawson (Code Review) 05 Apr '20

05 Apr '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38697 ) Change subject: vc/amd/fsp/picasso: Add file for GUIDs ...................................................................... vc/amd/fsp/picasso: Add file for GUIDs Begin a file for GUIDs used by the FSP. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Ied5c5085ea8ed55439192be8a44fa401aeb559a7 --- A src/vendorcode/amd/fsp/picasso/FspGuids.h 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/38697/1 diff --git a/src/vendorcode/amd/fsp/picasso/FspGuids.h b/src/vendorcode/amd/fsp/picasso/FspGuids.h new file mode 100644 index 0000000..9281b4e --- /dev/null +++ b/src/vendorcode/amd/fsp/picasso/FspGuids.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __FSP_GUIDS__ +#define __FSP_GUIDS__ + +#include <uuid.h> + +#define AMD_FSP_TSEG_HOB_GUID \ + GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \ + 0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c) + +#endif /* __FSP_GUIDS__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5c5085ea8ed55439192be8a44fa401aeb559a7 Gerrit-Change-Number: 38697 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: drivers/intel: Make FSP_USE_REPO an SOC optin instead of list dependency
by Mimoja (Code Review) 04 Apr '20

04 Apr '20

Mimoja has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37582 ) Change subject: drivers/intel: Make FSP_USE_REPO an SOC optin instead of list dependency ...................................................................... drivers/intel: Make FSP_USE_REPO an SOC optin instead of list dependency For quite a bit now we are extending the FSP_USE_REPO option to be available for all Intel SOCs. This results in an list beeing not only hard to maintain but also prune to errors. To change that behaviour this commit is introducing the HAVE_INTEL_FSP_REPO config for SOCs that are supported from withing 3rdparty/fsp. All other interactions with FSP_USE_REPO stay the same. Change-Id: I68ae373ce591f06073064aa75aac32ceca8fa1cc Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig 7 files changed, 11 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37582/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8c8ac59..9d1aa88 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -53,10 +53,7 @@ config FSP_USE_REPO bool "Use the IntelFSP based binaries" depends on ADD_FSP_BINARIES - depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ - SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ - SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE || \ - SOC_INTEL_DENVERTON_NS + depends on HAVE_INTEL_FSP_REPO help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig index 1eebeb6..16f43df 100644 --- a/src/soc/intel/Kconfig +++ b/src/soc/intel/Kconfig @@ -46,3 +46,8 @@ than the one in non-topswap bootblock. This string will be passed onto ifittool (-A -n option). ifittool will not parse the region for MCU entries, and only locate the region and insert its address into FIT. + +config HAVE_INTEL_FSP_REPO + bool "Use FSP Blobs from fsp submodule" + help + This SOC has FSP binaries living in 3rdparty/fsp. diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 0b3b30a..8dc7628 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -44,6 +44,7 @@ select GENERIC_GPIO_LIB select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER + select HAVE_INTEL_FSP_REPO select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA select NO_FIXED_XIP_ROM_SIZE diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 40c2fd7..8b55ac7 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -64,6 +64,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_M_XIP select GENERIC_GPIO_LIB + select HAVE_INTEL_FSP_REPO select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 9445977..0289cf4 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -33,6 +33,7 @@ select SOC_INTEL_COMMON_RESET select PLATFORM_USES_FSP2_0 select IOAPIC + select HAVE_INTEL_FSP_REPO select HAVE_SMI_HANDLER select CACHE_MRC_SETTINGS select PARALLEL_MP diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 4077619..1dd8bf1 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -20,6 +20,7 @@ select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP + select HAVE_INTEL_FSP_REPO select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 31f809a..cde9909 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -38,6 +38,7 @@ select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select HAVE_INTEL_FSP_REPO select IOAPIC select MRC_SETTINGS_PROTECT select NO_FIXED_XIP_ROM_SIZE -- To view, visit https://review.coreboot.org/c/coreboot/+/37582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68ae373ce591f06073064aa75aac32ceca8fa1cc Gerrit-Change-Number: 37582 Gerrit-PatchSet: 1 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Convert TSEG and BERT info to cbmem
by Marshall Dawson (Code Review) 04 Apr '20

04 Apr '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36114 ) Change subject: soc/amd/picasso: Convert TSEG and BERT info to cbmem ...................................................................... soc/amd/picasso: Convert TSEG and BERT info to cbmem Remove the convoluted memory map calculation for cbmem_top() and put the two reserved regions into cbmem. There is no compellng reason to keep these regions above cbmem. AMD can lock any region with Tvalid and the appropriate mask. The memory pointed to by the BERT table simply needs to be reserved from the OS. Change-Id: I6fa0544d642bbd8e2b3c21c3d186459ac8f6d477 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/memmap.c M src/soc/amd/picasso/romstage.c 3 files changed, 52 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/36114/1 diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index b54a8ef..cf1d2d4 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -41,6 +41,6 @@ #define EARLY_DRAM_MTRR_TOP \ (EARLY_DRAM_MTRR_BASE + EARLY_DRAM_MTRR_SIZE) -#define EARLY_RAMSTAGE_MTRR_SZ (32 * MiB) +#define EARLY_RAMSTAGE_MTRR_SZ (32 * MiB + CONFIG_SMM_TSEG_SIZE) #endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 09af7e4..7b21bb8 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -28,6 +28,8 @@ #include <soc/iomap.h> #include <amdblocks/acpimmio.h> +#define BERT_REGION_MAX_SIZE 0x100000 + void backup_top_of_low_cacheable(uintptr_t ramtop) { biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); @@ -38,24 +40,19 @@ return biosram_read32(BIOSRAM_CBMEM_TOP); } -#if CONFIG(ACPI_BERT) - #if CONFIG_SMM_TSEG_SIZE == 0x0 - #define BERT_REGION_MAX_SIZE 0x100000 - #else - /* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */ - #define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE - #endif -#else - #define BERT_REGION_MAX_SIZE 0 -#endif - void bert_reserved_region(void **start, size_t *size) { - if (CONFIG(ACPI_BERT)) - *start = cbmem_top(); - else - start = NULL; - *size = BERT_REGION_MAX_SIZE; + const struct cbmem_entry *bert; + + *start = 0; + *size = 0; + + bert = cbmem_entry_find(CBMEM_ID_BERT_RAW_DATA); + if (!bert) + return; + + *start = cbmem_entry_start(bert); + *size = cbmem_entry_size(bert); } void *cbmem_top(void) @@ -66,19 +63,7 @@ return 0; /* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() - - CONFIG_SMM_TSEG_SIZE - - BERT_REGION_MAX_SIZE, 8*MiB); -} - -static uintptr_t smm_region_start(void) -{ - return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; -} - -static size_t smm_region_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; + return (void *)ALIGN_DOWN(restore_top_of_low_cacheable(), 8 * MiB); } /* @@ -106,12 +91,39 @@ void smm_region(uintptr_t *start, size_t *size) { static int once; + const struct cbmem_entry *smm; - *start = smm_region_start(); - *size = smm_region_size(); + *start = 0; + *size = 0; + + smm = cbmem_entry_find(CBMEM_ID_SMM_TSEG_SPACE); + if (!smm) + return; + + *start = ALIGN_UP((uintptr_t)cbmem_entry_start(smm), CONFIG_SMM_TSEG_SIZE); + *size = CONFIG_SMM_TSEG_SIZE; if (!once) { clear_tvalid(); once = 1; } } + +/* Add or find TSEG and BERT storage prior to ramstage. ramstage may need + * to be recovered from cached space in TSEG. BERT storage is consumed at + * ROMSTAGE_CBMEM_INIT_HOOK and ordering can't be enforced for a hook. + */ +static void alloc_reserved_in_cbmem(int unused) +{ + void *p; + + /* Make large enough so TSEG can have alignment = size, allowing a + * good mask. + */ + p = cbmem_add(CBMEM_ID_SMM_TSEG_SPACE, 2 * CONFIG_SMM_TSEG_SIZE); + + if (CONFIG(ACPI_BERT)) + p = cbmem_add(CBMEM_ID_BERT_RAW_DATA, BERT_REGION_MAX_SIZE); +} + +ROMSTAGE_CBMEM_INIT_HOOK(alloc_reserved_in_cbmem) diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index eb39cc4..f4ae24b 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -78,27 +78,24 @@ static void set_mtrrs_for_ramstage(void) { - uintptr_t smm_base; - size_t smm_size; - uintptr_t smm_top; uintptr_t mem_top; uintptr_t ramstage_wb_base; size_t ramstage_wb_size; int mtrr; - smm_region(&smm_base, &smm_size); - smm_top = smm_base + smm_size; - mem_top = (uintptr_t)cbmem_top(); - /* Cache anticipated ramstage location through the top of TSEG */ - ramstage_wb_base = mem_top - EARLY_RAMSTAGE_MTRR_SZ; - ramstage_wb_size = smm_top - ramstage_wb_base; + /* Cache anticipated ramstage location through the top of cbmem. + * Unlike some other implementations, TSEG is in cbmem so it will + * be cached as well. + */ + ramstage_wb_size = EARLY_RAMSTAGE_MTRR_SZ; + ramstage_wb_base = mem_top - ramstage_wb_size; - /* Make sure MTRR base and size are usable */ + /* Ensure base and size are usable in a single MTRR pair */ if (ramstage_wb_size != 1 << fms(ramstage_wb_size)) { ramstage_wb_size = 1 << (1 + fms(ramstage_wb_size)); - ramstage_wb_base = smm_top - ramstage_wb_size; + ramstage_wb_base = mem_top - ramstage_wb_size; } if (mem_top - EARLY_RAMSTAGE_MTRR_SZ < EARLY_DRAM_MTRR_TOP) { printk(BIOS_WARNING, "Warning: Skipping ramstage cacheable due to configuration\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/36114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fa0544d642bbd8e2b3c21c3d186459ac8f6d477 Gerrit-Change-Number: 36114 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2020